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At the last VLSI Circuits Symposium in Kyoto, Japan, IBM scientists unveiled a prototype embedded SRAM chipset capable of reaching speeds beyond 6GHz. Their accomplishment is nearly twice as fast as the SRAMs available today.
Embedded SRAMs hold data that is frequently accessed by the processor. The faster the access, the faster the data transfer from SRAM to CPU. "As the technology reduces electronic dimensions to achieve higher densities and to follow Moore‘s Law, variability in processes that produce electronic devices makes this task increasingly difficult," said Rajiv Joshi, research staff member at IBM‘s T. J. Watson research center.
Overcoming variations
Researchers have been looking for ways to overcome the effects of process variability, especially variations in the device turn-on characteristics when a device is placed in a sea of devices. Those variations can make memories lose stored data, rendering them "unstable."
Different techniques have been proposed to improve the stability of SRAM cells, such as dynamic or dual-cell power supplies based on read or write operations, or adding more transistors to a six-transistor SRAM cell.
IBM researchers have demonstrated a novel hardware-based solution to eliminate "half select" problems, improve Vmin and increase performance for multiport applications by using 8T SRAM arrays.
Half-select occurs when word line is on while column select is off, which leads to poor stability. A novel write-byte concept generates local-write word lines, which are only selected when the write control for the selected block is on, avoiding half-select disturb conditions. Thus, the separate read port eliminates half-select during read, and write byte eliminates half-select during write.
Edge-capture circuit
An on-chip edge-capture circuit has been used for the first time to measure chip-internal signal parameters, such as word-line pulse width, and to calibrate the SRAM cell performance.
On-chip pulse characterization techniques show that tiny pulses, on the order of 50-60ps wide, can be measured to accurately determine how fast the SRAM cells can function. "This can definitely show that, indeed, the storage element is capable of functioning at a speed of 6.6-plus GHz," said Joshi.
The chip was fabricated in a 65nm silicon-on-insulator process, part of Joshi‘s research at IBM. He has been instrumental in developing novel interconnect processes and structures for aluminum, tungsten and copper technologies used in IBM processes. He holds 114 U.S. patents, in addition to several pending patents, and is an IEEE fellow.
- Nicolas Mokhoff
EE Times
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