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0001 /** 0002 * flexcan.c - FLEXCAN CAN controller driver 0003 * 0004 * Copyright (c) 2005-2006 Varma Electronics Oy 0005 * Copyright (c) 2009 Sascha Hauer, Pengutronix 0006 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix 0007 * 0008 * Based on code originally by Andrey Volkov <[e-mail]> 0009 * 0010 * LICENCE: 0011 * This program is free software; you can redistribute it and/or 0012 * modify it under the terms of the GNU General Public License as 0013 * published by the Free Software Foundation version 2. 0014 * 0015 * This program is distributed in the hope that it will be useful, 0016 * but WITHOUT ANY WARRANTY; without even the implied warranty of 0017 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 0018 * GNU General Public License for more details. 0019 * 0020 */ 0021 0022 #include <linux/netdevice.h> 0023 #include <linux/can.h> 0024 #include <linux/can/dev.h> 0025 #include <linux/can/error.h> 0026 #include <linux/can/platform/flexcan.h> 0027 #include <linux/clk.h> 0028 #include <linux/delay.h> 0029 #include <linux/if_arp.h> 0030 #include <linux/if_ether.h> 0031 #include <linux/interrupt.h> 0032 #include <linux/io.h> 0033 #include <linux/kernel.h> 0034 #include <linux/list.h> 0035 #include <linux/module.h> 0036 #include <linux/platform_device.h> 0037 0038 #include <mach/clock.h> 0039 0040 #define DRV_NAME "flexcan" 0041 0042 /** 8 for RX fifo and 2 error handling */ 0043 #define FLEXCAN_NAPI_WEIGHT (8 + 2) 0044 0045 /** FLEXCAN module configuration register (CANMCR) bits */ 0046 #define FLEXCAN_MCR_MDIS BIT(31) 0047 #define FLEXCAN_MCR_FRZ BIT(30) 0048 #define FLEXCAN_MCR_FEN BIT(29) 0049 #define FLEXCAN_MCR_HALT BIT(28) 0050 #define FLEXCAN_MCR_NOT_RDY BIT(27) 0051 #define FLEXCAN_MCR_WAK_MSK BIT(26) 0052 #define FLEXCAN_MCR_SOFTRST BIT(25) 0053 #define FLEXCAN_MCR_FRZ_ACK BIT(24) 0054 #define FLEXCAN_MCR_SUPV BIT(23) 0055 #define FLEXCAN_MCR_SLF_WAK BIT(22) 0056 #define FLEXCAN_MCR_WRN_EN BIT(21) 0057 #define FLEXCAN_MCR_LPM_ACK BIT(20) 0058 #define FLEXCAN_MCR_WAK_SRC BIT(19) 0059 #define FLEXCAN_MCR_DOZE BIT(18) 0060 #define FLEXCAN_MCR_SRX_DIS BIT(17) 0061 #define FLEXCAN_MCR_BCC BIT(16) 0062 #define FLEXCAN_MCR_LPRIO_EN BIT(13) 0063 #define FLEXCAN_MCR_AEN BIT(12) 0064 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0xf) 0065 #define FLEXCAN_MCR_IDAM_A (0 << 8) 0066 #define FLEXCAN_MCR_IDAM_B (1 << 8) 0067 #define FLEXCAN_MCR_IDAM_C (2 << 8) 0068 #define FLEXCAN_MCR_IDAM_D (3 << 8) 0069 0070 /** FLEXCAN control register (CANCTRL) bits */ 0071 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24) 0072 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22) 0073 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19) 0074 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16) 0075 #define FLEXCAN_CTRL_BOFF_MSK BIT(15) 0076 #define FLEXCAN_CTRL_ERR_MSK BIT(14) 0077 #define FLEXCAN_CTRL_CLK_SRC BIT(13) 0078 #define FLEXCAN_CTRL_LPB BIT(12) 0079 #define FLEXCAN_CTRL_TWRN_MSK BIT(11) 0080 #define FLEXCAN_CTRL_RWRN_MSK BIT(10) 0081 #define FLEXCAN_CTRL_SMP BIT(7) 0082 #define FLEXCAN_CTRL_BOFF_REC BIT(6) 0083 #define FLEXCAN_CTRL_TSYN BIT(5) 0084 #define FLEXCAN_CTRL_LBUF BIT(4) 0085 #define FLEXCAN_CTRL_LOM BIT(3) 0086 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07) 0087 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK) 0088 #define FLEXCAN_CTRL_ERR_STATE \ 0089 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \ 0090 FLEXCAN_CTRL_BOFF_MSK) 0091 #define FLEXCAN_CTRL_ERR_ALL \ 0092 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) 0093 0094 /** FLEXCAN error and status register (ESR) bits */ 0095 #define FLEXCAN_ESR_TWRN_INT BIT(17) 0096 #define FLEXCAN_ESR_RWRN_INT BIT(16) 0097 #define FLEXCAN_ESR_BIT1_ERR BIT(15) 0098 #define FLEXCAN_ESR_BIT0_ERR BIT(14) 0099 #define FLEXCAN_ESR_ACK_ERR BIT(13) 0100 #define FLEXCAN_ESR_CRC_ERR BIT(12) 0101 #define FLEXCAN_ESR_FRM_ERR BIT(11) 0102 #define FLEXCAN_ESR_STF_ERR BIT(10) 0103 #define FLEXCAN_ESR_TX_WRN BIT(9) 0104 #define FLEXCAN_ESR_RX_WRN BIT(8) 0105 #define FLEXCAN_ESR_IDLE BIT(7) 0106 #define FLEXCAN_ESR_TXRX BIT(6) 0107 #define FLEXCAN_EST_FLT_CONF_SHIFT (4) 0108 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT) 0109 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT) 0110 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT) 0111 #define FLEXCAN_ESR_BOFF_INT BIT(2) 0112 #define FLEXCAN_ESR_ERR_INT BIT(1) 0113 #define FLEXCAN_ESR_WAK_INT BIT(0) 0114 #define FLEXCAN_ESR_ERR_BUS \ 0115 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \ 0116 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \ 0117 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR) 0118 #define FLEXCAN_ESR_ERR_STATE \ 0119 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT) 0120 #define FLEXCAN_ESR_ERR_ALL \ 0121 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE) 0122 0123 /** FLEXCAN interrupt flag register (IFLAG) bits */ 0124 #define FLEXCAN_TX_BUF_ID 8 0125 #define FLEXCAN_IFLAG_BUF(x) BIT(x) 0126 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7) 0127 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6) 0128 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5) 0129 #define FLEXCAN_IFLAG_DEFAULT \ 0130 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \ 0131 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID)) 0132 0133 /** FLEXCAN message buffers */ 0134 #define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24) 0135 #define FLEXCAN_MB_CNT_SRR BIT(22) 0136 #define FLEXCAN_MB_CNT_IDE BIT(21) 0137 #define FLEXCAN_MB_CNT_RTR BIT(20) 0138 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16) 0139 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff) 0140 0141 #define FLEXCAN_MB_CODE_MASK (0xf0ffffff) 0142 0143 /** Structure of the message buffer */ 0144 struct flexcan_mb { 0145 u32 can_ctrl; 0146 u32 can_id; 0147 u32 data[2]; 0148 }; 0149 0150 /** Structure of the hardware registers */ 0151 struct flexcan_regs { 0152 u32 mcr; /** 0x00 */ 0153 u32 ctrl; /** 0x04 */ 0154 u32 timer; /** 0x08 */ 0155 u32 _reserved1; /** 0x0c */ 0156 u32 rxgmask; /** 0x10 */ 0157 u32 rx14mask; /** 0x14 */ 0158 u32 rx15mask; /** 0x18 */ 0159 u32 ecr; /** 0x1c */ 0160 u32 esr; /** 0x20 */ 0161 u32 imask2; /** 0x24 */ 0162 u32 imask1; /** 0x28 */ 0163 u32 iflag2; /** 0x2c */ 0164 u32 iflag1; /** 0x30 */ 0165 u32 _reserved2[19]; 0166 struct flexcan_mb cantxfg[64]; 0167 }; 0168 0169 struct flexcan_priv { 0170 struct can_priv can; 0171 struct net_device *dev; 0172 struct napi_struct napi; 0173 0174 void __iomem *base; 0175 u32 reg_esr; 0176 u32 reg_ctrl_default; 0177 0178 struct clk *clk; 0179 struct flexcan_platform_data *pdata; 0180 }; 0181 0182 static struct can_bittiming_const flexcan_bittiming_const = { 0183 .name = DRV_NAME, 0184 .tseg1_min = 4, 0185 .tseg1_max = 16, 0186 .tseg2_min = 2, 0187 .tseg2_max = 8, 0188 .sjw_max = 4, 0189 .brp_min = 1, 0190 .brp_max = 256, 0191 .brp_inc = 1, 0192 }; 0193 0194 /** 0195 * Swtich transceiver on or off 0196 */ 0197 static void flexcan_transceiver_switch(const struct flexcan_priv *priv, int on) 0198 { 0199 if (priv->pdata && priv->pdata->transceiver_switch) 0200 priv->pdata->transceiver_switch(on); 0201 } 0202 0203 static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv, 0204 u32 reg_esr) 0205 { 0206 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 0207 (reg_esr & FLEXCAN_ESR_ERR_BUS); 0208 } 0209 0210 static inline void flexcan_chip_enable(struct flexcan_priv *priv) 0211 { 0212 struct flexcan_regs __iomem *regs = priv->base; 0213 u32 reg; 0214 0215 reg = readl(&regs->mcr); 0216 reg &= ~FLEXCAN_MCR_MDIS; 0217 writel(reg, &regs->mcr); 0218 0219 udelay(10); 0220 } 0221 0222 static inline void flexcan_chip_disable(struct flexcan_priv *priv) 0223 { 0224 struct flexcan_regs __iomem *regs = priv->base; 0225 u32 reg; 0226 0227 reg = readl(&regs->mcr); 0228 reg |= FLEXCAN_MCR_MDIS; 0229 writel(reg, &regs->mcr); 0230 } 0231 0232 static int flexcan_get_berr_counter(const struct net_device *dev, 0233 struct can_berr_counter *bec) 0234 { 0235 const struct flexcan_priv *priv = netdev_priv(dev); 0236 struct flexcan_regs __iomem *regs = priv->base; 0237 u32 reg = readl(&regs->ecr); 0238 0239 bec->txerr = (reg >> 0) & 0xff; 0240 bec->rxerr = (reg >> 8) & 0xff; 0241 0242 return 0; 0243 } 0244 0245 static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev) 0246 { 0247 const struct flexcan_priv *priv = netdev_priv(dev); 0248 struct net_device_stats *stats = &dev->stats; 0249 struct flexcan_regs __iomem *regs = priv->base; 0250 struct can_frame *cf = (struct can_frame *)skb->data; 0251 u32 can_id; 0252 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16); 0253 0254 if (can_dropped_invalid_skb(dev, skb)) 0255 return NETDEV_TX_OK; 0256 0257 netif_stop_queue(dev); 0258 0259 if (cf->can_id & CAN_EFF_FLAG) { 0260 can_id = cf->can_id & CAN_EFF_MASK; 0261 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR; 0262 } else { 0263 can_id = (cf->can_id & CAN_SFF_MASK) << 18; 0264 } 0265 0266 if (cf->can_id & CAN_RTR_FLAG) 0267 ctrl |= FLEXCAN_MB_CNT_RTR; 0268 0269 if (cf->can_dlc > 0) { 0270 u32 data = be32_to_cpup((__be32 *)&cf->data[0]); 0271 writel(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[0]); 0272 } 0273 if (cf->can_dlc > 3) { 0274 u32 data = be32_to_cpup((__be32 *)&cf->data[4]); 0275 writel(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[1]); 0276 } 0277 0278 writel(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id); 0279 writel(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); 0280 0281 kfree_skb(skb); 0282 0283 /** tx_packets is incremented in flexcan_irq */ 0284 stats->tx_bytes += cf->can_dlc; 0285 0286 return NETDEV_TX_OK; 0287 } 0288 0289 static void do_bus_err(struct net_device *dev, 0290 struct can_frame *cf, u32 reg_esr) 0291 { 0292 struct flexcan_priv *priv = netdev_priv(dev); 0293 int rx_errors = 0, tx_errors = 0; 0294 0295 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 0296 0297 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) { 0298 dev_dbg(dev->dev.parent, "BIT1_ERR irq\n"); 0299 cf->data[2] |= CAN_ERR_PROT_BIT1; 0300 tx_errors = 1; 0301 } 0302 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) { 0303 dev_dbg(dev->dev.parent, "BIT0_ERR irq\n"); 0304 cf->data[2] |= CAN_ERR_PROT_BIT0; 0305 tx_errors = 1; 0306 } 0307 if (reg_esr & FLEXCAN_ESR_ACK_ERR) { 0308 dev_dbg(dev->dev.parent, "ACK_ERR irq\n"); 0309 cf->can_id |= CAN_ERR_ACK; 0310 cf->data[3] |= CAN_ERR_PROT_LOC_ACK; 0311 tx_errors = 1; 0312 } 0313 if (reg_esr & FLEXCAN_ESR_CRC_ERR) { 0314 dev_dbg(dev->dev.parent, "CRC_ERR irq\n"); 0315 cf->data[2] |= CAN_ERR_PROT_BIT; 0316 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 0317 rx_errors = 1; 0318 } 0319 if (reg_esr & FLEXCAN_ESR_FRM_ERR) { 0320 dev_dbg(dev->dev.parent, "FRM_ERR irq\n"); 0321 cf->data[2] |= CAN_ERR_PROT_FORM; 0322 rx_errors = 1; 0323 } 0324 if (reg_esr & FLEXCAN_ESR_STF_ERR) { 0325 dev_dbg(dev->dev.parent, "STF_ERR irq\n"); 0326 cf->data[2] |= CAN_ERR_PROT_STUFF; 0327 rx_errors = 1; 0328 } 0329 0330 priv->can.can_stats.bus_error++; 0331 if (rx_errors) 0332 dev->stats.rx_errors++; 0333 if (tx_errors) 0334 dev->stats.tx_errors++; 0335 } 0336 0337 static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr) 0338 { 0339 struct sk_buff *skb; 0340 struct can_frame *cf; 0341 0342 skb = alloc_can_err_skb(dev, &cf); 0343 if (unlikely(!skb)) 0344 return 0; 0345 0346 do_bus_err(dev, cf, reg_esr); 0347 netif_receive_skb(skb); 0348 0349 dev->stats.rx_packets++; 0350 dev->stats.rx_bytes += cf->can_dlc; 0351 0352 return 1; 0353 } 0354 0355 static void do_state(struct net_device *dev, 0356 struct can_frame *cf, enum can_state new_state) 0357 { 0358 struct flexcan_priv *priv = netdev_priv(dev); 0359 struct can_berr_counter bec; 0360 0361 flexcan_get_berr_counter(dev, &bec); 0362 0363 switch (priv->can.state) { 0364 case CAN_STATE_ERROR_ACTIVE: 0365 /** 0366 * from: ERROR_ACTIVE 0367 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 0368 * => : there was a warning int 0369 */ 0370 if (new_state >= CAN_STATE_ERROR_WARNING && 0371 new_state <= CAN_STATE_BUS_OFF) { 0372 dev_dbg(dev->dev.parent, "Error Warning IRQ\n"); 0373 priv->can.can_stats.error_warning++; 0374 0375 cf->can_id |= CAN_ERR_CRTL; 0376 cf->data[1] = (bec.txerr > bec.rxerr) ? 0377 CAN_ERR_CRTL_TX_WARNING : 0378 CAN_ERR_CRTL_RX_WARNING; 0379 } 0380 case CAN_STATE_ERROR_WARNING: /** fallthrough */ 0381 /** 0382 * from: ERROR_ACTIVE, ERROR_WARNING 0383 * to : ERROR_PASSIVE, BUS_OFF 0384 * => : error passive int 0385 */ 0386 if (new_state >= CAN_STATE_ERROR_PASSIVE && 0387 new_state <= CAN_STATE_BUS_OFF) { 0388 dev_dbg(dev->dev.parent, "Error Passive IRQ\n"); 0389 priv->can.can_stats.error_passive++; 0390 0391 cf->can_id |= CAN_ERR_CRTL; 0392 cf->data[1] = (bec.txerr > bec.rxerr) ? 0393 CAN_ERR_CRTL_TX_PASSIVE : 0394 CAN_ERR_CRTL_RX_PASSIVE; 0395 } 0396 break; 0397 case CAN_STATE_BUS_OFF: 0398 dev_err(dev->dev.parent, 0399 "BUG! hardware recovered automatically from BUS_OFF\n"); 0400 break; 0401 default: 0402 break; 0403 } 0404 0405 /** process state changes depending on the new state */ 0406 switch (new_state) { 0407 case CAN_STATE_ERROR_ACTIVE: 0408 dev_dbg(dev->dev.parent, "Error Active\n"); 0409 cf->can_id |= CAN_ERR_PROT; 0410 cf->data[2] = CAN_ERR_PROT_ACTIVE; 0411 break; 0412 case CAN_STATE_BUS_OFF: 0413 cf->can_id |= CAN_ERR_BUSOFF; 0414 can_bus_off(dev); 0415 break; 0416 default: 0417 break; 0418 } 0419 } 0420 0421 static int flexcan_poll_state(struct net_device *dev, u32 reg_esr) 0422 { 0423 struct flexcan_priv *priv = netdev_priv(dev); 0424 struct sk_buff *skb; 0425 struct can_frame *cf; 0426 enum can_state new_state; 0427 int flt; 0428 0429 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK; 0430 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) { 0431 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN | 0432 FLEXCAN_ESR_RX_WRN)))) 0433 new_state = CAN_STATE_ERROR_ACTIVE; 0434 else 0435 new_state = CAN_STATE_ERROR_WARNING; 0436 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE)) 0437 new_state = CAN_STATE_ERROR_PASSIVE; 0438 else 0439 new_state = CAN_STATE_BUS_OFF; 0440 0441 /** state hasn't changed */ 0442 if (likely(new_state == priv->can.state)) 0443 return 0; 0444 0445 skb = alloc_can_err_skb(dev, &cf); 0446 if (unlikely(!skb)) 0447 return 0; 0448 0449 do_state(dev, cf, new_state); 0450 priv->can.state = new_state; 0451 netif_receive_skb(skb); 0452 0453 dev->stats.rx_packets++; 0454 dev->stats.rx_bytes += cf->can_dlc; 0455 0456 return 1; 0457 } 0458 0459 static void flexcan_read_fifo(const struct net_device *dev, 0460 struct can_frame *cf) 0461 { 0462 const struct flexcan_priv *priv = netdev_priv(dev); 0463 struct flexcan_regs __iomem *regs = priv->base; 0464 struct flexcan_mb __iomem *mb = &regs->cantxfg[0]; 0465 u32 reg_ctrl, reg_id; 0466 0467 reg_ctrl = readl(&mb->can_ctrl); 0468 reg_id = readl(&mb->can_id); 0469 if (reg_ctrl & FLEXCAN_MB_CNT_IDE) 0470 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 0471 else 0472 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK; 0473 0474 if (reg_ctrl & FLEXCAN_MB_CNT_RTR) 0475 cf->can_id |= CAN_RTR_FLAG; 0476 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf); 0477 0478 *(__be32 *)(cf->data + 0) = cpu_to_be32(readl(&mb->data[0])); 0479 *(__be32 *)(cf->data + 4) = cpu_to_be32(readl(&mb->data[1])); 0480 0481 /** mark as read */ 0482 writel(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1); 0483 readl(&regs->timer); 0484 } 0485 0486 static int flexcan_read_frame(struct net_device *dev) 0487 { 0488 struct net_device_stats *stats = &dev->stats; 0489 struct can_frame *cf; 0490 struct sk_buff *skb; 0491 0492 skb = alloc_can_skb(dev, &cf); 0493 if (unlikely(!skb)) { 0494 stats->rx_dropped++; 0495 return 0; 0496 } 0497 0498 flexcan_read_fifo(dev, cf); 0499 netif_receive_skb(skb); 0500 0501 stats->rx_packets++; 0502 stats->rx_bytes += cf->can_dlc; 0503 0504 return 1; 0505 } 0506 0507 static int flexcan_poll(struct napi_struct *napi, int quota) 0508 { 0509 struct net_device *dev = napi->dev; 0510 const struct flexcan_priv *priv = netdev_priv(dev); 0511 struct flexcan_regs __iomem *regs = priv->base; 0512 u32 reg_iflag1, reg_esr; 0513 int work_done = 0; 0514 0515 /** 0516 * The error bits are cleared on read, 0517 * use saved value from irq handler. 0518 */ 0519 reg_esr = readl(&regs->esr) | priv->reg_esr; 0520 0521 /** handle state changes */ 0522 work_done += flexcan_poll_state(dev, reg_esr); 0523 0524 /** handle RX-FIFO */ 0525 reg_iflag1 = readl(&regs->iflag1); 0526 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE && 0527 work_done < quota) { 0528 work_done += flexcan_read_frame(dev); 0529 reg_iflag1 = readl(&regs->iflag1); 0530 } 0531 0532 /** report bus errors */ 0533 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota) 0534 work_done += flexcan_poll_bus_err(dev, reg_esr); 0535 0536 if (work_done < quota) { 0537 napi_complete(napi); 0538 /** enable IRQs */ 0539 writel(FLEXCAN_IFLAG_DEFAULT, &regs->imask1); 0540 writel(priv->reg_ctrl_default, &regs->ctrl); 0541 } 0542 0543 return work_done; 0544 } 0545 0546 static irqreturn_t flexcan_irq(int irq, void *dev_id) 0547 { 0548 struct net_device *dev = dev_id; 0549 struct net_device_stats *stats = &dev->stats; 0550 struct flexcan_priv *priv = netdev_priv(dev); 0551 struct flexcan_regs __iomem *regs = priv->base; 0552 u32 reg_iflag1, reg_esr; 0553 0554 reg_iflag1 = readl(&regs->iflag1); 0555 reg_esr = readl(&regs->esr); 0556 writel(FLEXCAN_ESR_ERR_INT, &regs->esr); /** ACK err IRQ */ 0557 0558 /** 0559 * schedule NAPI in case of: 0560 * - rx IRQ 0561 * - state change IRQ 0562 * - bus error IRQ and bus error reporting is activated 0563 */ 0564 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) || 0565 (reg_esr & FLEXCAN_ESR_ERR_STATE) || 0566 flexcan_has_and_handle_berr(priv, reg_esr)) { 0567 /** 0568 * The error bits are cleared on read, 0569 * save them for later use. 0570 */ 0571 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS; 0572 writel(FLEXCAN_IFLAG_DEFAULT & ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, 0573 &regs->imask1); 0574 writel(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, 0575 &regs->ctrl); 0576 napi_schedule(&priv->napi); 0577 } 0578 0579 /** FIFO overflow */ 0580 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) { 0581 writel(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1); 0582 dev->stats.rx_over_errors++; 0583 dev->stats.rx_errors++; 0584 } 0585 0586 /** transmission complete interrupt */ 0587 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) { 0588 /** tx_bytes is incremented in flexcan_start_xmit */ 0589 stats->tx_packets++; 0590 writel((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1); 0591 netif_wake_queue(dev); 0592 } 0593 0594 return IRQ_HANDLED; 0595 } 0596 0597 static void flexcan_set_bittiming(struct net_device *dev) 0598 { 0599 const struct flexcan_priv *priv = netdev_priv(dev); 0600 const struct can_bittiming *bt = &priv->can.bittiming; 0601 struct flexcan_regs __iomem *regs = priv->base; 0602 u32 reg; 0603 0604 reg = readl(&regs->ctrl); 0605 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) | 0606 FLEXCAN_CTRL_RJW(0x3) | 0607 FLEXCAN_CTRL_PSEG1(0x7) | 0608 FLEXCAN_CTRL_PSEG2(0x7) | 0609 FLEXCAN_CTRL_PROPSEG(0x7) | 0610 FLEXCAN_CTRL_LPB | 0611 FLEXCAN_CTRL_SMP | 0612 FLEXCAN_CTRL_LOM); 0613 0614 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) | 0615 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) | 0616 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) | 0617 FLEXCAN_CTRL_RJW(bt->sjw - 1) | 0618 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1); 0619 0620 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 0621 reg |= FLEXCAN_CTRL_LPB; 0622 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 0623 reg |= FLEXCAN_CTRL_LOM; 0624 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) 0625 reg |= FLEXCAN_CTRL_SMP; 0626 0627 dev_info(dev->dev.parent, "writing ctrl=0x%08x\n", reg); 0628 writel(reg, &regs->ctrl); 0629 0630 /** print chip status */ 0631 dev_dbg(dev->dev.parent, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__, 0632 readl(&regs->mcr), readl(&regs->ctrl)); 0633 } 0634 0635 /** 0636 * flexcan_chip_start 0637 * 0638 * this functions is entered with clocks enabled 0639 * 0640 */ 0641 static int flexcan_chip_start(struct net_device *dev) 0642 { 0643 struct flexcan_priv *priv = netdev_priv(dev); 0644 struct flexcan_regs __iomem *regs = priv->base; 0645 unsigned int i; 0646 int err; 0647 u32 reg_mcr, reg_ctrl; 0648 0649 /** enable module */ 0650 flexcan_chip_enable(priv); 0651 0652 /** soft reset */ 0653 writel(FLEXCAN_MCR_SOFTRST, &regs->mcr); 0654 udelay(10); 0655 0656 reg_mcr = readl(&regs->mcr); 0657 if (reg_mcr & FLEXCAN_MCR_SOFTRST) { 0658 dev_err(dev->dev.parent, 0659 "Failed to softreset can module (mcr=0x%08x)\n", 0660 reg_mcr); 0661 err = -ENODEV; 0662 goto out; 0663 } 0664 0665 flexcan_set_bittiming(dev); 0666 0667 /** 0668 * MCR 0669 * 0670 * enable freeze 0671 * enable fifo 0672 * halt now 0673 * only supervisor access 0674 * enable warning int 0675 * choose format C 0676 * 0677 */ 0678 reg_mcr = readl(&regs->mcr); 0679 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT | 0680 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | 0681 FLEXCAN_MCR_IDAM_C; 0682 dev_dbg(dev->dev.parent, "%s: writing mcr=0x%08x", __func__, reg_mcr); 0683 writel(reg_mcr, &regs->mcr); 0684 0685 /** 0686 * CTRL 0687 * 0688 * disable timer sync feature 0689 * 0690 * disable auto busoff recovery 0691 * transmit lowest buffer first 0692 * 0693 * enable tx and rx warning interrupt 0694 * enable bus off interrupt 0695 * (== FLEXCAN_CTRL_ERR_STATE) 0696 * 0697 * _note_: we enable the "error interrupt" 0698 * (FLEXCAN_CTRL_ERR_MSK), too. Otherwise we don't get any 0699 * warning or bus passive interrupts. 0700 */ 0701 reg_ctrl = readl(&regs->ctrl); 0702 reg_ctrl &= ~FLEXCAN_CTRL_TSYN; 0703 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF | 0704 FLEXCAN_CTRL_ERR_STATE | FLEXCAN_CTRL_ERR_MSK; 0705 0706 /** save for later use */ 0707 priv->reg_ctrl_default = reg_ctrl; 0708 dev_dbg(dev->dev.parent, "%s: writing ctrl=0x%08x", __func__, reg_ctrl); 0709 writel(reg_ctrl, &regs->ctrl); 0710 0711 for (i = 0; i < ARRAY_SIZE(regs->cantxfg); i++) { 0712 writel(0, &regs->cantxfg[i].can_ctrl); 0713 writel(0, &regs->cantxfg[i].can_id); 0714 writel(0, &regs->cantxfg[i].data[0]); 0715 writel(0, &regs->cantxfg[i].data[1]); 0716 0717 /** put MB into rx queue */ 0718 writel(FLEXCAN_MB_CNT_CODE(0x4), &regs->cantxfg[i].can_ctrl); 0719 } 0720 0721 /** acceptance mask/acceptance code (accept everything) */ 0722 writel(0x0, &regs->rxgmask); 0723 writel(0x0, &regs->rx14mask); 0724 writel(0x0, &regs->rx15mask); 0725 0726 flexcan_transceiver_switch(priv, 1); 0727 0728 /** synchronize with the can bus */ 0729 reg_mcr = readl(&regs->mcr); 0730 reg_mcr &= ~FLEXCAN_MCR_HALT; 0731 writel(reg_mcr, &regs->mcr); 0732 0733 priv->can.state = CAN_STATE_ERROR_ACTIVE; 0734 0735 /** enable FIFO interrupts */ 0736 writel(FLEXCAN_IFLAG_DEFAULT, &regs->imask1); 0737 0738 /** print chip status */ 0739 dev_dbg(dev->dev.parent, "%s: reading mcr=0x%08x ctrl=0x%08x\n", 0740 __func__, readl(&regs->mcr), readl(&regs->ctrl)); 0741 0742 return 0; 0743 0744 out: 0745 flexcan_chip_disable(priv); 0746 return err; 0747 } 0748 0749 /** 0750 * flexcan_chip_stop 0751 * 0752 * this functions is entered with clocks enabled 0753 * 0754 */ 0755 static void flexcan_chip_stop(struct net_device *dev) 0756 { 0757 struct flexcan_priv *priv = netdev_priv(dev); 0758 struct flexcan_regs __iomem *regs = priv->base; 0759 u32 reg; 0760 0761 /** Disable all interrupts */ 0762 writel(0, &regs->imask1); 0763 0764 /** Disable + halt module */ 0765 reg = readl(&regs->mcr); 0766 reg |= FLEXCAN_MCR_MDIS | FLEXCAN_MCR_HALT; 0767 writel(reg, &regs->mcr); 0768 0769 flexcan_transceiver_switch(priv, 0); 0770 priv->can.state = CAN_STATE_STOPPED; 0771 0772 return; 0773 } 0774 0775 static int flexcan_open(struct net_device *dev) 0776 { 0777 struct flexcan_priv *priv = netdev_priv(dev); 0778 int err; 0779 0780 clk_enable(priv->clk); 0781 0782 err = open_candev(dev); 0783 if (err) 0784 goto out; 0785 0786 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev); 0787 if (err) 0788 goto out_close; 0789 0790 /** start chip and queuing */ 0791 err = flexcan_chip_start(dev); 0792 if (err) 0793 goto out_close; 0794 napi_enable(&priv->napi); 0795 netif_start_queue(dev); 0796 0797 return 0; 0798 0799 out_close: 0800 close_candev(dev); 0801 out: 0802 clk_disable(priv->clk); 0803 0804 return err; 0805 } 0806 0807 static int flexcan_close(struct net_device *dev) 0808 { 0809 struct flexcan_priv *priv = netdev_priv(dev); 0810 0811 netif_stop_queue(dev); 0812 napi_disable(&priv->napi); 0813 flexcan_chip_stop(dev); 0814 0815 free_irq(dev->irq, dev); 0816 clk_disable(priv->clk); 0817 0818 close_candev(dev); 0819 0820 return 0; 0821 } 0822 0823 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode) 0824 { 0825 int err; 0826 0827 switch (mode) { 0828 case CAN_MODE_START: 0829 err = flexcan_chip_start(dev); 0830 if (err) 0831 return err; 0832 0833 netif_wake_queue(dev); 0834 break; 0835 0836 default: 0837 return -EOPNOTSUPP; 0838 } 0839 0840 return 0; 0841 } 0842 0843 static const struct net_device_ops flexcan_netdev_ops = { 0844 .ndo_open = flexcan_open, 0845 .ndo_stop = flexcan_close, 0846 .ndo_start_xmit = flexcan_start_xmit, 0847 }; 0848 0849 static int __devinit register_flexcandev(struct net_device *dev) 0850 { 0851 struct flexcan_priv *priv = netdev_priv(dev); 0852 struct flexcan_regs __iomem *regs = priv->base; 0853 u32 reg, err; 0854 0855 clk_enable(priv->clk); 0856 0857 /** select "bus clock", chip must be disabled */ 0858 flexcan_chip_disable(priv); 0859 reg = readl(&regs->ctrl); 0860 reg |= FLEXCAN_CTRL_CLK_SRC; 0861 writel(reg, &regs->ctrl); 0862 0863 flexcan_chip_enable(priv); 0864 0865 /** set freeze, halt and activate FIFO, restrict register access */ 0866 reg = readl(&regs->mcr); 0867 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | 0868 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV; 0869 writel(reg, &regs->mcr); 0870 0871 /** 0872 * Currently we only support newer versions of this core 0873 * featuring a RX FIFO. Older cores found on some Coldfire 0874 * derivates are not yet supported. 0875 */ 0876 reg = readl(&regs->mcr); 0877 if (!(reg & FLEXCAN_MCR_FEN)) { 0878 dev_err(dev->dev.parent, 0879 "Could not enable RX FIFO, unsupported core\n"); 0880 err = -ENODEV; 0881 goto out; 0882 } 0883 0884 err = register_candev(dev); 0885 0886 out: 0887 /** disable core and turn off clocks */ 0888 flexcan_chip_disable(priv); 0889 clk_disable(priv->clk); 0890 0891 return err; 0892 } 0893 0894 static void __devexit unregister_flexcandev(struct net_device *dev) 0895 { 0896 unregister_candev(dev); 0897 } 0898 0899 static int __devinit flexcan_probe(struct platform_device *pdev) 0900 { 0901 struct net_device *dev; 0902 struct flexcan_priv *priv; 0903 struct resource *mem; 0904 struct clk *clk; 0905 void __iomem *base; 0906 resource_size_t mem_size; 0907 int err, irq; 0908 0909 clk = clk_get(&pdev->dev, NULL); 0910 if (IS_ERR(clk)) { 0911 dev_err(&pdev->dev, "no clock defined\n"); 0912 err = PTR_ERR(clk); 0913 goto failed_clock; 0914 } 0915 0916 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 0917 irq = platform_get_irq(pdev, 0); 0918 if (!mem || irq <= 0) { 0919 err = -ENODEV; 0920 goto failed_get; 0921 } 0922 0923 mem_size = resource_size(mem); 0924 if (!request_mem_region(mem->start, mem_size, pdev->name)) { 0925 err = -EBUSY; 0926 goto failed_req; 0927 } 0928 0929 base = ioremap(mem->start, mem_size); 0930 if (!base) { 0931 err = -ENOMEM; 0932 goto failed_map; 0933 } 0934 0935 dev = alloc_candev(sizeof(struct flexcan_priv), 0); 0936 if (!dev) { 0937 err = -ENOMEM; 0938 goto failed_alloc; 0939 } 0940 0941 dev->netdev_ops = &flexcan_netdev_ops; 0942 dev->irq = irq; 0943 dev->flags |= IFF_ECHO; /** we support local echo in hardware */ 0944 0945 priv = netdev_priv(dev); 0946 priv->can.clock.freq = clk_get_rate(clk); 0947 priv->can.bittiming_const = &flexcan_bittiming_const; 0948 priv->can.do_set_mode = flexcan_set_mode; 0949 priv->can.do_get_berr_counter = flexcan_get_berr_counter; 0950 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 0951 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES | 0952 CAN_CTRLMODE_BERR_REPORTING; 0953 priv->base = base; 0954 priv->dev = dev; 0955 priv->clk = clk; 0956 priv->pdata = pdev->dev.platform_data; 0957 0958 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT); 0959 0960 dev_set_drvdata(&pdev->dev, dev); 0961 SET_NETDEV_DEV(dev, &pdev->dev); 0962 0963 err = register_flexcandev(dev); 0964 if (err) { 0965 dev_err(&pdev->dev, "registering netdev failed\n"); 0966 goto failed_register; 0967 } 0968 0969 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 0970 priv->base, dev->irq); 0971 0972 return 0; 0973 0974 failed_register: 0975 free_candev(dev); 0976 failed_alloc: 0977 iounmap(base); 0978 failed_map: 0979 release_mem_region(mem->start, mem_size); 0980 failed_req: 0981 clk_put(clk); 0982 failed_get: 0983 failed_clock: 0984 return err; 0985 } 0986 0987 static int __devexit flexcan_remove(struct platform_device *pdev) 0988 { 0989 struct net_device *dev = platform_get_drvdata(pdev); 0990 struct flexcan_priv *priv = netdev_priv(dev); 0991 struct resource *mem; 0992 0993 unregister_flexcandev(dev); 0994 platform_set_drvdata(pdev, NULL); 0995 free_candev(dev); 0996 iounmap(priv->base); 0997 0998 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 0999 release_mem_region(mem->start, resource_size(mem)); 1000 1001 clk_put(priv->clk); 1002 1003 return 0; 1004 } 1005 1006 static struct platform_driver flexcan_driver = { 1007 .driver.name = DRV_NAME, 1008 .probe = flexcan_probe, 1009 .remove = __devexit_p(flexcan_remove), 1010 }; 1011 1012 static int __init flexcan_init(void) 1013 { 1014 pr_info("%s netdevice driver\n", DRV_NAME); 1015 return platform_driver_register(&flexcan_driver); 1016 } 1017 1018 static void __exit flexcan_exit(void) 1019 { 1020 platform_driver_unregister(&flexcan_driver); 1021 pr_info("%s: driver removed\n", DRV_NAME); 1022 } 1023 1024 module_init(flexcan_init); 1025 module_exit(flexcan_exit); 1026 1027 MODULE_AUTHOR("Sascha Hauer <[e-mail]>, " 1028 "Marc Kleine-Budde <[e-mail]>"); 1029 MODULE_LICENSE("GPL v2"); 1030 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");