Test Point Insertion for Test Coverage Improvement in DFT : 新思科技

CharlseLib 2012-04-15

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Test Point Insertion for Test Coverage Improvement in DFT

Hongwei Wang
STMicroelectronics (Shenzhen) R&D Co., Ltd.

hongwei.wang@st.com

Abstract

In a complex ASIC design, there are usually some uncontrollable or unobservable logics. Because these logics are unable or difficult to control and/or observe, it is very difficult or impossible to test them. The consequence is low test coverage, and this will lead to the part’s reliability problem. Test Point Insertion is an efficient technique to improve a design’s testability and improve its test coverage by adding some simple controllable and/or observable logic.

This paper presents an example of Test Point Insertion. This is a real project of using DFT Compiler and TertaMAX to improve test coverage. We will analyze and explain the main causes which lower test coverage, and then provide a solution for test coverage improvement. By comparing the results of both pre and post Test Point Insertion, we can see that test coverage and test efficiency have been greatly improved with just a few test point insertions and the addition of a few logic gates. This paper analyzes the causes that lead to low test coverage and introduces the test design flow using Test Point Insertion technique. Test Point Insertion technique can solve two typical test issues that lower test coverage: shadow logic between digital logic and black box, and the un-bonded pads in a multi-die chip.

Key words: Test Point Insertion, Test Coverage , DFT.

1. Frequetly Problems

To speed up ASIC design and reduce the turnaround time of marketing and mass production for an electronics product, the development schedules of Very Large Scale Integrated Circuit (VLSI) design and manufacturing become shorter and shorter. Design engineers must take care of the possible defects and debug them during the manufacturing process. Design for Testability (DFT) takes an important role of improving product yield.

Test coverage and test efficiency are the most important standards for design quality when we use DFT techniques. A good design with high test coverage should be observable and controllable. It is understandable that 100% test coverage is difficult to achieve. In order to save the testing costs, design engineers should use fewer test patterns with higher coverage. Test efficiency is also very important.

In addition, DFT engineers must guarantee the function remains unchanged during DFT design. In some designs, as some mission mode function logics are uncontrollable and unobservable, and these logics potentially cause many test problems. Test coverage for these designs could not be improved without using advanced test techniques or simply by increasing the number of test patterns.

Test coverage is defined as the percentage of detected faults out of total detectable faults. This coverage is a more meaningful evaluation for test pattern quality. Fault coverage is defined as the percentage of detected faults out of all faults, including the ATPG Undetected faults. By definition we can find that test coverage is always higher than fault coverage. The formula below shows the calculation for test coverage and fault coverage.

AU: ATPG Untestable;	UD: Undetectable;
ND: Not Detected;	PT: Possible Detected
Default Value: pt_credit = 50%; au_credit = 0%

IIn real design, usually there are two typical types of logic that impact test coverage. The first type resides in the input/output shadow parts between digital logic and black box. The second type is in the input/output pads of un-bonded pads in multi-die package.

Figure 1 indicates a multi-die package. In this application, the other pads except test_si and test_so are not bonded to outside; this unbonded input or output pads connect to ground or are floating. Therefore, the cone logic related to port_A,port_B and port_C are uncontrollable, while the logic related to port_Z1,port_Z2 and port_Z3 are unobservable. These in turn mean that test coverage is lowered because many of the logics in the design are not testable.

Figure 1: Uncontrollable or Unobservable Logic Caused by Packages

General speaking, the primary input and output pads are used for controllability and observability in DFT design. Usually it is impossible to reserve enough dedicated pads for every design because of the limitation of IO pads. We normally consider analog macros such as PLL, ADC and memory as a black box during ATPG test. Figure 2 shows digital black box interface. The RAM macro below is an example of a black box. Since the addr_bus, din_bus and net_1 go directly into the pins of memory, and the related logic cone “Com. Logic 1” sinks into the memory input pins, this logic could not be observed directly and therefore could not be tested. The test coverage of the design is low. Meantime, at the output pins of memory block, the nets dout_bus, net_2 and net_3 cannot be controlled directly because they are connected to memory’s output pins, these pins are considered as “X” state during Automatic Test Pattern Generation, therefore the “Com. Logic 2” could not be tested. Because of these test problems, the test coverage for this design is not high enough to meet the target of DFT.

Figure 2: Uncontrollable or Unobservable Logic Caused by Black-Box Interface

Clock gating may also affect the testability problem for Automatic Test Pattern Generation. To make the clock signal from clock gating cell controllable, we can use a control signal to bypass the clock gating cell or make it transparent during test or scan shift. We have two choices for the control signals: one is test mode and the other is test enable signal. It is recommended to use test enable signal as clock gating control signal, since the test mode keeps “1” in all test procedures while test enable only keeps in “1” in shift mode. Sometimes, we have to use test mode signal because of the impact from other modes. In this case, we can insert test points to increase the test coverage.

2. Solution

In order to fix the low global test coverage problem, we focus on making the related logic controllable and observable during RTL design or during scan chain insertion. This will help us to understand how to write good testable RTL code during function design and use DFT features of DFT Compiler for Test Point Insertion (TPI).

Figure 3 gives a solution to improve test coverage by adding TPI for un-bonded pads in Figure 1. One multiplex register is inserted at the output of the input pads as illustrated in the graph. When the control test enable signal TE is “0”, the circuit works in normal operation mode, its function logic receives the normal input data from primary inputs. When the control test enable signal TE is “1”, the circuit works in test mode: during shift process, the pre-load bits are shifted through the scan chain; during capture process, a pull-down or pull-up is applied to prevent the test logic from the global “X” propagation.

As for the output pads, some XOR cells and multiplex cells are inserted. When the control test enable signal TE is “0”, the circuit works in normal operation mode, the related pads output normal function response. When the control test enable signal TE is “1”, the circuit works in test mode: the XOR cells take the consideration with un-bonded pads, so these ports can be observed equivalently.

Figure 3: Test Point Insertion to Improve Test Coverage (for Un-bonded Pins)

As for the interface between the logic and the black box shown in Figure 2, the black box input signals come from the combinational logic and these signals go to the black box. The logic is not observable so the test coverage is low. For the black box’ s output signals, they control the next level combination logic directly. These signals are uncontrollable in test modes because they are from the black box. Therefore the logic is not controllable, which lowers the test coverage. Similar to the solution for un-bonded pads, Figure 4 shows the solution to improve testability. We insert some test points in the design and put the above mentioned signals into the scan chain in order to make them controllable and observable which finally improves the test coverage and efficiency.

In Figure 4, some XOR cells and multiplex cells are added at the input pins of the black box; these cells control the inputs of the black box and they are inserted into scan chain. When the control signal is “0”, the circuit works in normal operation mode, and the black box inputs receive signals from function input ports. When the control signal is “1”, the circuit works in test mode: the previously unobservable signals go through XOR cells and these signals can be observed transparently.

Also one multiplex register is added at each output pin of the black box to control the next-level combinational logic. When the control signal is “0”, the circuit works in normal operation mode, and the function logic receives the normal input data from the black box. When the control signal is “1”, the circuit works in test mode: Pre-loading data are shifted through the scan chain during the shift process. In capture process, a ground connection is used to prevent the test logic from the global “X” propagation.

Figure 4: TPI Solution for Test Coverage Improvement (Digital-Analog Interface)

For a design with black box modules, it is recommended to take them into account early during RTL design. Design engineers can balance a design’s functionality and its testability simultaneously. If testability is not considered during function design, TPI techniques can be used to solve the testability problem of the design. These techniques are flexible and easy to use as a common solution.

3. TPI Application

From the previous analysis of testability problems and solutions provided, some test points can be inserted to put the uncontrollable or unobservable logics into the scan chain. By using this technique, these logics can be tested, and test coverage and test efficiency can be improved greatly.

Test Point Insertion (TPI) is a useful technique for solving the potential testability problem and improving the test coverage of a design by making its uncontrollable logic controllable and unobservable logic observable. This technique also helps to improve the test efficiency since the higher coverage can be derived with few test vectors increasing. This technique is very easy to put into application since only a few commands are added in the existing scripts.

As for the multi-die package design, the “add net connections” command can be used to eliminate the unbonded pads before pattern generation. These unbonded pads can be defined as TIE0, TIE1 using embedded pull-up, pull-down cells. These pads can be defined as floating if they are not connected to any pin during packaging. The following example removes the primary input pads or inout pads; ATPG will exclude these pads during pattern generation.

Figure 5: Unbonded Pads Removal from Imported Design

Before the test point insertion, it is important to check the global test coverage and analyze where the bottle-neck for low test coverage is; otherwise the test point efficiency will not be good enough to meet the test target. TetraMAX is recommended to report the global test coverage of a netlist with scan chain insertion and then get the TPI design guidance. Figure 6 indicates test coverage and fault coverage from the design.

Figure 6: ATPG Test Coverage Report with Pre-TPI Netlist

According to the formulas for calculating test coverage and fault coverage, the UD (Undetectable) is excluded from the test coverage calculation; but the AU (ATPG Untestable) fault is included in coverage calculation. This is why we focus on AU faults for test point insertion to make them testable. With “report fault –class AU” command in depth option, the test coverage will be reported. This report gives the outline of test coverage for every module. We can find out which macros cause low test coverage mostly, then analyze the related logic carefully; TPI can be applied efficiently to receive the maximum return with little logic added. As an example, Figure 7 shows script command to report the AU Faults in the design.

Figure 7: AU Faults Report Command

Figure 8: AU Faults Report for Low Test Coverage

Figure 8 indicates the AU faults report with the related command for test coverage analysis. In this example, the main cause of low-test coverage is the untestable logic between memories and digital interface, also the untestable logic between analog and digital. Because the memories address and data in RAM are dedicated to special functionality and have nothing to do with other logic, this logic cone cannot be controlled by the primary ports in capture mode; they act just like sinking points, which need the test point insertion to make test coverage higher.

We recommend including TPI in traditional scan insertion flow when using a DFT Compiler. Some commands are added in script simply to define which instances are required for the test point insertion, then we insert scan chains using the original configuration. This flow is convenient for both design review and checks.

Figure 9 below indicates the script file for test point insertion. Many options can be used for control point and observe point insertion according to our requirement. According to our experience, both observe points and controllable points are sensitive for test ceoverage improvement, most of important thing is to choose the correct points for the higher test efficiency.

Also scan chains can be inserted with traditional configuration. Figure 10 and figure 11 show the post-TPI netlist adding the observation points and control points, the name of inserted DFF instances follows the name rule “udtp_sink***” by default, which means “user defined test point”. The instance named “EOLL” is the XOR gates according to the design request.

Figure 9: DFT Compiler Test Point Insertion Script File

Figure 10: Inserted Test Instances for Observation Purpose

Figure 11: Inserted Test Instances for Control Purpose

With the same options, Figure 12 indicates the test coverage and fault coverage of a post-TPI netlist in ATPG flow. With just a few test patterns increased, global test coverage is improved greatly which meets our test target. Figure 13 shows the test coverage increase for modules with TPI.

Figure 12: ATPG Test Coverage Report with Post-TPI Netlist

Figure 13: AU Faults Report with Post-TPI

The reports from DFT Compiler and TetraMAX reveal that the little additional logics can mean a lot of improvement for test coverage to satisfy the test target. Because only a few instances are added for coverage improvement, this TPI will not impact too much on Back-End design flow. Also there is no functionality difference between pre-TPI and post-TPI netlist; since the added test points only takes some multiplexers or XOR gates into account, it is clean from the design function. In functional mode, the design passes formal check successfully and smoothly by using formality; the TetraMAX guarantees the integration of scan chain and ATPG processing.

After we analyzed the post-TPI netlist, we concluded that the TPI technique and DFT Compiler are very useful to insert observe and control points in a test unfriendly design, and therefore improve the test coverage with little area overhead.

4. Conclusion

In our project mentioned above, there are more than ten thousand registers in the original design. With the TPI technique, we only added 12 registers and a few combinational logics. The test coverage increased from 95% to 98.3%. Obviously, this technique is very efficient and easy to use. More test points can be inserted if necessary for higher test coverage. The test coverage can reach nearly 100% in theory.

We strongly recommend design engineers use TPI technique in their design flow. By doing so, we can anticipate the different design structures required for function design and design for testability. On one hand, the function design is clear in operation mode. On the other hand, uncontrollable and unobservable problems are avoided mostly in the DFT design. However, if these issues exist after the RTL is frozen, we may use DFT tools to insert user-defined test-points. DFT Compiler and TetraMAX from Synopsys have the capability to accomplish this job.

It is also important to choose the right test points’ locations. If the location is chosen improperly, test coverage could not be improved. Test coverage could not be increased further even with more test patterns.

Based on analysis and implementation of this project, test coverage and efficiency have been improved greatly with just a few logic gates. This methodology is very easy to use, and we only needed to add a few commands in our existing scripts. It is useful for almost all DFT design, especially for those designs requesting higher test coverage. We strongly recommend this technique to improve test coverage for our designs.