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libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entitydivclk1is
Port(clk:instd_logic;
divclk:outstd_logic);
enddivclk1;
architectureBehavioralofdivclk1is
signalcounter:std_logic_vector(4downto0):="00000";
signaltempdivclk:std_logic:=''0'';
begin
process(clk)
begin
ifclk''eventandclk=''1''then
if(counter>="11000")then
counter<="00000";
tempdivclk<=nottempdivclk;
else
counter<=counter+''1'';
endif;
endif;
endprocess;
divclk<=tempdivclk;
endBehavioral;
7a?File->Savei|?3 g
File->Close
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libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entitydivclk1is
Port(clk:instd_logic:=''0'';
divclk:outstd_logic);
enddivclk1;
architectureBehavioralofdivclk1is
signalcounter:std_logic_vector(5downto0):="000000";
begin
process(clk)
begin
ifclk''eventandclk=''1''then
if(counter>="110001")then
counter<="000000";
else
counter<=counter+''1'';
endif;
endif;
endprocess;
divclk<=counter(5);
endBehavioral;
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->CompileAll;
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LIBRARYieee;
USEieee.std_logic_1164.ALL;
USEieee.numeric_std.ALL;
ENTITYdivclk1_tbIS
ENDdivclk1_tb;
ARCHITECTUREbehaviorOFdivclk1_tbIS
COMPONENTdivclk1
PORT(
clk:INstd_logic;
divclk:OUTstd_logic
);
ENDCOMPONENT;
SIGNALclk:std_logic:=''0'';
SIGNALdivclk:std_logic;
BEGIN
uut:divclk1PORTMAP(
clk=>clk,
divclk=>divclk
);
clk<=notclkafter10ns;
END;
/
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fileinput:TEXTopenread_modeis"STD_INPUT";
fileoutput:TEXTopenwrite_modeis"STD_OUTPUT";
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#include"iostream.h"
#include"fstream.h"
voidmain(void)
{
inti,j;
ofstreamfsIn("d:\\yuproj\\modelsim\\TextioTest\\TestData.dat");
ofstreamfsOut("d:\\yuproj\\modelsim\\TextioTest\\Result.dat");
for(i=-127;i<128;i++)
{
for(j=-127;j<128;j++)
{
fsIn<
fsOut<
}
}
fsIn.close();
fsOut.close();
}
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Result.dat
?ó''ì
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?
H-W[ bì? 7'' Vb
2.?yModelSimy?
u 7ModelSim?yy?Textioib"
c1d:\yuproj\modelsim\TextioTest
3.@F
!9÷óq
?y
!9óqNineBitsAdder?yóq￥ZE
^File->New->Source->VHDL÷}
?
?/
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_signed.all;
entityAdd2Inis
port(D1:instd_logic_vector(7downto0);
D2:instd_logic_vector(7downto0);
Q:outstd_logic_vector(8downto0);
Clk:instd_logic);
endAdd2In;
architectureA_Add2InofAdd2Inis
begin
process(Clk)
begin
ifClk=''1''andClk''eventthen
Q<=(D1(D1''left)&D1)+(D2(D2''left)&D2);
endif;
endprocess;
endA_Add2In;
é?FE-
n5é?ê￥ ?Z é?FE
?b
Hò￥
6??FE
?b
4.@F?
kóq
?yTestBenchóqTestBench.vhd?yóq￥ZE
^File->New->Source->VHDL
}
??/
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_signed.all;
useieee.std_logic_arith.all;
usestd.TEXTIO.all;
entitytbis
endtb;
architecturea_tboftbis
componentAdd2In
port(D1:instd_logic_vector(7downto0);
D2:instd_logic_vector(7downto0);
Q:outstd_logic_vector(8downto0);
Clk:instd_logic);
endcomponent;
signalD1:std_logic_vector(7downto0):=(others=>''0'');
signalD2:std_logic_vector(7downto0):=(others=>''0'');
signalQ:std_logic_vector(8downto0);
signalClk:std_logic:=''0'';
signalDlatch:boolean:=false;
signalSResult:integer;
begin
dut:Add2In
portmap(D1=>D1,
D2=>D2,
Q=>Q,
Clk=>Clk);
Clk<=notClkafter20ns;
process
fileInputD:textopenread_modeis"TestData.dat";
variableDLine:LINE;
variablegood:Boolean;
variableData1:integer;
variableData2:integer;
begin
waituntilClk=''1''andClk''event;
readline(InputD,DLine);
read(DLine,Data1,good);
read(DLine,Data2,good);
if(good)then
D1<=CONV_STD_LOGIC_VECTOR(Data1,8);
D2<=CONV_STD_LOGIC_VECTOR(Data2,8);
else
assertfalsereport"EndofReadingInputFile!"
severityerror;
endif;
endprocess;
process
fileInputR:textopenread_modeis"Result.dat";
variableRLine:LINE;
variableResult:integer;
begin
waituntilClk=''1''andClk''event;
Dlatch<=true;
ifDlatchthen
readline(InputR,RLine);
read(RLine,Result);
SResult<=Result;
ifSResult/=Qthen
assertfalsereport"Twovaluesaredifferent"
severitywarning;
endif;
endif;
endprocess;
enda_tb;
5.Ir
/
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^???Compile->CompileAll;
6.
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#Fatal:(vsim-3551)TEXTIO:Readpastendoffile"TestData.dat".
#Time:2601020nsIteration:0Process:/tb/line__34File:
D:/yuProj/modelsim/TextioTest/TestBench.vhd
#FatalerroratD:/yuProj/modelsim/TextioTest/TestBench.vhdline41
#
V
U ?TestData.datay bCpb?
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#Warning:Twovaluesaredifferent
#Time:4060nsIteration:0Instance:/tb
#Fatal:(vsim-3551)TEXTIO:Readpastendoffile"TestData.dat".
#Time:2601020nsIteration:0Process:/tb/line__34File:
D:/yuProj/modelsim/TextioTest/TestBench.vhd
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#
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Error:D:/yuProj/modelsim/TextioTest/TestBench.vhd(34):Unknown
identifier:read_mode
Error:D:/yuProj/modelsim/TextioTest/TestBench.vhd(34):FILE
declarationusing1076-1993syntax.Recompileusing-93switch.
Error:D:/yuProj/modelsim/TextioTest/TestBench.vhd(34):VHDLCompiler
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std=$MODEL_TECH/../std
ieee=$MODEL_TECH/../ieee
verilog=$MODEL_TECH/../verilog
vital2000=$MODEL_TECH/../vital2000
std_developerskit=$MODEL_TECH/../std_developerskit
synopsys=$MODEL_TECH/../synopsys
modelsim_lib=$MODEL_TECH/../modelsim_lib
;VHDLSection
unisim=$MODEL_TECH/../xilinx/vhdl/unisim
simprim=$MODEL_TECH/../xilinx/vhdl/simprim
xilinxcorelib=$MODEL_TECH/../xilinx/vhdl/xilinxcorelib
aim=$MODEL_TECH/../xilinx/vhdl/aim
pls=$MODEL_TECH/../xilinx/vhdl/pls
cpld=$MODEL_TECH/../xilinx/vhdl/cpld
;VerilogSection
unisims_ver=$MODEL_TECH/../xilinx/verilog/unisims_ver
uni9000_ver=$MODEL_TECH/../xilinx/verilog/uni9000_ver
simprims_ver=$MODEL_TECH/../xilinx/verilog/simprims_ver
xilinxcorelib_ver=$MODEL_TECH/../xilinx/verilog/xilinxcorelib_ver
aim_ver=$MODEL_TECH/../xilinx/verilog/aim_ver
cpld_ver=$MODEL_TECH/../xilinx/verilog/cpld_ver
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;Show_Warning1=0
;Turnoffprocess-without-a-wait-statementwarnings.Defaultison.
;Show_Warning2=0
;Turnoffnull-rangewarnings.Defaultison.
;Show_Warning3=0
;Turnoffno-space-in-time-literalwarnings.Defaultison.
;Show_Warning4=0
;Turnoffmultiple-drivers-on-unresolved-signalwarnings.Defaultison.
;Show_Warning5=0
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;Optimize_1164=0
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;NoVitalCheck=1
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;thenUserTimeUnitdefaultstops.
UserTimeUnit=default
;Defaultrunlength
RunLength=100
;Maximumiterationsthatcanberunwithoutadvancingsimulationtime
IterationLimit=5000
;Directivetolicensemanager:
;vhdlImmediatelyreserveaVHDLlicense
;vlogImmediatelyreserveaVeriloglicense
;plusImmediatelyreserveaVHDLandVeriloglicense
;nomgcDonotlookforMentorGraphicsLicenses
;nomtiDonotlookforModelTechnologyLicenses
;noqueueDonotwaitinthelicensequeuewhenalicenseisn''t
available
;License=plus
;Stopthesimulatorafteranassertionmessage
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BreakOnAssertion=3
;AssertionMessageFormat
;%S-SeverityLevel
;%R-ReportMessage
;%T-Timeofassertion
;%D-Delta
;%I-InstanceorRegionpathname(ifavailable)
;%%-print''%''character
;AssertionFormat="%S:%R\nTimf:%TIteration:%D%I\n"
;AssertionFile-alternatefileforstoringassertionmessages
;AssertFile=assert.log
;Defaultradixforallwindowsandcommands...
;Settosymbolic,ascii,binary,octal,decimal,hex,unsigned
DefaultRadix=symbolic
;VSIMStartupcommand
;Startup=dostartup.do
;Fileforsavingcommandtranscript
TranscriptFile=transcript
;Fileforsavingcommandhistory
;CommandHistory=cmdhist.log
;Specifywhetherpathsinsimulatorcommandsshouldbedescribed
;inVHDLorVerilogformat.ForVHDL,PathSeparator=/
;forVerilog,PathSeparator=.
PathSeparator=/
;Specifythedatasetseparatorforfullyrootedcontexts.
;Thedefaultis'':''.Forexample,sim:/top
;MustnotbethesamecharacterasPathSeparator.
DatasetSeparator=:
;Disableassertionmessages
;IgnoreNote=1
;IgnoreWarning=1
;IgnoreError=1
;IgnoreFailure=1
;Defaultforcekind.Maybefreeze,drive,ordeposit
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;DefaultForceKind=freeze
;Ifzero,openfileswhenelaborated
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;DelayFileOpen=0
;ControlVHDLfilesopenedforwrite
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UnbufferedOutput=0
;ControlnumberofVHDLfilesopenconcurrently
;Thisnumbershouldalwaysbelessthenthe
;currentulimitsettingformaxfiledescriptors
;0=unlimited
ConcurrentFileLimit=40
;Thiscontrolsthenumberofhierarchicalregionsdisplayedas
;partofasignalnameshowninthewaveformwindow.Thedefault
;valueoravalueofzerotellsVSIMtodisplaythefullname.
;WaveSignalNameWidth=0
;Turnoffwarningsfromthestd_logic_arith,std_logic_unsigned
;andstd_logic_signedpackages.
;StdArithNoWarnings=1
;TurnoffwarningsfromtheIEEEnumeric_stdandnumeric_bit
;packages.
;NumericStdNoWarnings=1
;Controltheformatofageneratestatementlabel.Don''tquoteit.
;GenerateFormat=%s__%d
;Specifywhethercheckpointfilesshouldbecompressed.
;Thedefaultistobecompressed.
;CheckpointCompressMode=0
;ListofdynamicallyloadedobjectsforVerilogPLIapplications
;Veriuser=veriuser.sl
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