Allegro
Memory
DocScope:CadenceAllegro15.x
DocNumber:SFTCA06009
Author:SOFER
CreateDate:2005-8-30
Rev:1.00
SOFERTECHNOLOGY
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SOFERTECHNICALFILE
1AB
2P
3P+A+B50Mil
XNet
ABCadence
XNetXeXtend
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1ABXNet
a)Analyze>SI/EMISim>Model…Yes.
b)DevTypeValue
PCBDevType
RN_8P_rn_8pRN
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c)CreateModel…CreateESpiceDevicemodelOK
d)ValuePinOK.
Pin
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SinglePin18273645
e)showelementNetNetnameXNet
XNet
2ConstraintManager
a)Setup>ElectricalConstraintSpreadsheetConstraintManager
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b)Net>Routing>RelativePropagationDelay
SigXplorer…Topology
Editor
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c)Set>Constraint
RuleName
FromPin
ToPin
Scope
Local
Global
DeltaTypeDeltaDeltaDelta
NoneDelta0
Delta
Delay
Length
Delta
TolType
Tolerance
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d)RuleFromToTopologyEditor
OK
e)File>UpdateConstraintManagerConstraintManager
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f)ConstraintManagerECsetYes
Close
g)MD0ReferencedElectricalCSet
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h)Change…
MD0OK
Close
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RelativePropagationDelayTopologyEditor
TopologyEditor
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i)
Slide
ConstraintManager
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OnlineDRC
Setup>Constraints…Electricalconstraintsets…
RelativepropagationDelayOn
File>Import>Pindelay
[]
EDAhttp://www.sofer.com.cn
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