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| HIP6020 |
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281
TM
HIP6020
SELECT
SS
FAULT/RT
DRIVE3
GND
VAUX
18
17
16
11
12
13
VSEN4DRIVE41514
CAUTION:Thesedevicesaresensitivetoelectrostaticdischarge;followproperICHandlingProcedures.
1-888-INTERSILor321-724-7143|Intersil(anddesign)isatrademarkofIntersilAmericasInc.
Copyright?IntersilAmericasInc.2002.AllRightsReserved
AdvancedDualPWMandDualLinear
PowerController
TheHIP6020providesthepowercontrolandprotectionfor
fouroutputvoltagesinhigh-performance,graphicsintensive
microprocessorandcomputerapplications.TheIC
integratestwoPWMcontrollersandtwolinearcontrollers,as
wellasthemonitoringandprotectionfunctionsintoa28-pin
SOICpackage.OnePWMcontrollerregulatesthe
microprocessorcorevoltagewithasynchronous-rectified
buckconverter.ThesecondPWMcontrollersuppliesthe
computersystem’sAGP1.5Vor3.3Vbuspowerwitha
standardbuckconverter.Thelinearcontrollersregulate
powerforthe1.5VGTLbusandthe1.8Vpowerforthe
North/SouthBridgecorevoltageand/orcachememory
circuits.
TheHIP6020includesanIntel-compatible,TTL5-input
digital-to-analogconverter(DAC)thatadjuststhecorePWM
outputvoltagefrom1.3V
DC
to2.05V
DC
in0.05Vstepsand
from2.1V
DC
to3.5V
DC
in0.1Vincrements.Theprecision
referenceandvoltage-modecontrolprovide±1%static
regulation.ThesecondPWMcontroller’soutputisuser-
selectable,throughaTTL-compatiblesignalappliedatthe
SELECTpin,forlevelsof1.5Vor3.3Vwith±3%accuracy.
ThelinearregulatorsuseexternalN-ChannelMOSFETsor
bipolarNPNpasstransistorstoprovidefixedoutputvoltages
of1.5V±3%(V
OUT3
)and1.8V±3%(V
OUT4
).
TheHIP6020monitorsalltheoutputvoltages.Asingle
PowerGoodsignalisissuedwhenthecoreiswithin±10%of
theDACsettingandallotheroutputsareabovetheirunder-
voltagelevels.Additionalbuilt-inover-voltageprotectionfor
thecoreoutputusesthelowerMOSFETtopreventoutput
voltagesabove115%oftheDACsetting.ThePWM
controllers’over-currentfunctionmonitorstheoutputcurrent
byusingthevoltagedropacrosstheupperMOSFET’s
r
DS(ON)
,eliminatingtheneedforacurrentsensingresistor.
Features
?Provides4RegulatedVoltages
-MicroprocessorCore,AGPBus,North/SouthBridge
and/orCacheMemory,andGTLBusPower
?DrivesN-ChannelMOSFETs
?LinearRegulatorDrivesCompatiblewithbothMOSFET
andBipolarSeriesPassTransistors
?SimpleSingle-LoopControlDesigns
-Voltage-ModePWMControl
?FastPWMConverterTransientResponse
-High-BandwidthErrorAmplifiers
-Full0%to100%DutyRatios
?ExcellentOutputVoltageRegulation
-CorePWMOutput:±1%OverTemperature
-AGPBusPWMOutput:±3%OverTemperature
-OtherOutputs:±3%OverTemperature
?TTL-Compatible5BitDACMicroprocessorCoreOutput
VoltageSelection
-WideRange...................1.3V
DC
to3.5V
DC
?Power-GoodOutputVoltageMonitor
?Over-VoltageandOver-CurrentFaultMonitors
-SwitchingRegulatorsDoNotRequireExtraCurrent
SensingElements,UseMOSFET’sr
DS(ON)
?SmallConverterSize
-ConstantFrequencyOperation
-200kHzFree-RunningOscillator;ProgrammableFrom
50kHztoOver1MHz
-SmallExternalComponentCount
Applications
?
MotherboardPowerRegulationforComputers
Pinout
HIP6020(SOIC)
TOPVIEW
OrderingInformation
PARTNUMBER
TEMP.
RANGE(
o
C)PACKAGE
PKG.
NO.
HIP6020CB0to7028LdSOICM28.3
HIP6020EVAL1EvaluationBoard
UGATE2
PHASE2
VID4
VID3
VSEN2
VCC
PGND
LGATE1
PHASE1
COMP1
UGATE1
28
27
26
25
24
23
22
21
20
19
1
2
3
4
5
6
7
8
9
10
PGOOD
VID2
OCSET2
VSEN1
VSEN3
VID1
VID0
OCSET1
FB1
DataSheetFebruary1999FN4683
HIP6020
BlockDiagram
SO
F
T
-
S
T
ART
INHIBIT
PWM
CO
M
P
1
E
RRO
R
AM
P
1
VC
C
PG
O
O
D
PW
M
1
GN
D
VS
EN
1
OC
S
E
T
1
VI
D
0
VI
D
1
VI
D
2
VI
D
3
FB
1
CO
M
P
1
DACO
UT
UG
AT
E
1
P
HAS
E
1
200
μ
A
28
μ
A
4.5
V
+-+-+-
+-
VI
D
4
LG
A
T
E
1
PG
N
D
DRIV
E
4
DRI
V
E
3
VSE
N
3
+-
INHIBIT
PW
M
2
UG
A
T
E
2
P
H
A
SE2
E
RRO
R
AM
P
2
PW
M
CO
M
P
2
20
0
μ
AOC
S
E
T
2
VS
EN
2
F
AUL
T
/
RT
+-+-
GA
T
E
C
O
NT
RO
L
+-
1.26V
+-
PO
WE
R
-
O
N
RE
S
E
T
(
P
O
R
)
TTLD
/
A
CO
NV
E
R
T
E
R
(
DAC)
O
S
C
I
LLA
TO
R
+-
+-
GA
T
E
CO
NT
RO
L
VC
C
VC
C
VC
C
VC
C
&F
AUL
T
LO
G
I
C
SS
1.
5
V
S
Y
NCH
DRIV
E
DRIV
E
1
DRIV
E
2
+-
+
+-
UNDE
R-
V
O
LTA
G
E
VS
EN
4
L
I
NE
AR
F
AUL
T
OV
LU
V
OC
2
OC
1
-
or
3.3V
+-
SEL
E
C
T
+
-
V
AUX
V
AUX
0.
7
5
x
0.
7
5
x
0.
9
0
x
1.
10
x
1.
1
5
x
282
HIP6020
SimplifiedPowerSystemDiagram
TypicalApplication
PWM1
+5V
IN
V
OUT1
Q1
Q2
Q3
V
OUT2
Q4
V
OUT3
V
OUT4
PWM2
LINEARLINEAR
HIP6020
CONTROLLER
CONTROLLER
CONTROLLERCONTROLLER
+3.3V
IN
Q5
VID1
VID2
VID3
VID4
SS
GND
VCC
+5V
IN
VID0
+12V
IN
V
OUT1
PGND
VSEN1
PGOOD
LGATE1
UGATE1
OCSET1
PHASE1
Q1
Q2
POWERGOOD
FB1
COMP1
1.3VTO3.5V
SELECT
UGATE2
PHASE2
Q3
CR2
VSEN2
DRIVE3
VSEN3
VSEN4
C
OUT4
1.5V
1.8V
C
OUT3
C
OUT2
C
IN
C
OUT1
Q4
L
OUT2
L
OUT1
HIP6020
V
OUT2
V
OUT3
V
OUT4
1.5VOR3.3V
FAULT/RT
C
SS
Q5
+3.3V
IN
TYPEDET
L
IN
DRIVE4
VAUX
OCSET2
2-283
HIP6020
AbsoluteMaximumRatingsThermalInformation
SupplyVoltage,V
CC
.................................+15V
PGOOD,RT/FAULT,DRIVE,PHASE,and
GATEVoltage..................GND-0.3VtoV
CC
+0.3V
Input,OutputorI/OVoltage..................GND-0.3Vto7V
ESDClassification................................Class1
OperatingConditions
SupplyVoltage,V
CC
...........................+12V±10%
AmbientTemperatureRange....................0
o
Cto70
o
C
JunctionTemperatureRange..................0
o
Cto125
o
C
ThermalResistance(Typical,Note1)θ
JA
(
o
C/W)
SOICPackage............................70
MaximumJunctionTemperature(PlasticPackage)........150
o
C
MaximumStorageTemperatureRange.........-65
o
Cto150
o
C
MaximumLeadTemperature(Soldering10s).............300
o
C
(SOIC-LeadTipsOnly)
CAUTION:Stressesabovethoselistedin“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.Thisisastressonlyratingandoperationofthe
deviceattheseoranyotherconditionsabovethoseindicatedintheoperationalsectionsofthisspecificationisnotimplied.
NOTE:
1.θ
JA
ismeasuredwiththecomponentmountedonanevaluationPCboardinfreeair.
ElectricalSpecificationsRecommendedOperatingConditions,UnlessOtherwiseNoted.RefertoFigures1,2and3
PARAMETERSYMBOLTESTCONDITIONSMINTYPMAXUNITS
VCCSUPPLYCURRENT
NominalSupplyCurrentI
CC
UGATE1,LGATE1,UGATE2,DRIVE3,and
DRIVE4Open
-9-mA
POWER-ONRESET
RisingVCCThresholdV
OCSET
=4.5V--10.4V
FallingVCCThresholdV
OCSET
=4.5V8.2--V
RisingVAUXThresholdV
OCSET
=4.5V-2.5-V
VAUXThresholdHysteresisV
OCSET
=4.5V-0.5-V
RisingV
OCSET1
Threshold-1.26-V
OSCILLATOR
FreeRunningFrequencyF
OSC
RT=OPEN185200215kHz
TotalVariation6k?
RampAmplitude?V
OSC
RT=Open-1.9-V
P-P
DACANDSTANDARDBUCKREGULATORREFERENCE
DAC(VID0-VID4)InputLowVoltage--0.8V
DAC(VID0-VID4)InputHighVoltage2.0-V
DACOUTVoltageAccuracy-1.0-+1.0%
PWM2ReferenceVoltageSELECT<0.8V-1.5-V
PWM2ReferenceVoltageSELECT>2.0V-3.3-V
PWM2ReferenceVoltageTolerance-3-%
1.5VAND1.8VLINEARREGULATORS(V
OUT3
ANDV
OUT4
)
Regulation-3-%
VSEN3RegulationVoltageVREG
3
-1.5-V
VSEN4RegulationVoltageVREG
4
-1.8-V
VSEN3,4Under-VoltageLevelVSEN3
UV
VSEN3Rising-75-%
VSEN3,4Under-VoltageHysteresisVSEN3Falling-7-%
OutputDriveCurrentVAUX-V
DRIVE
>0.6V2040-mA
SYNCHRONOUSPWMCONTROLLERERRORAMPLIFIER
DCGain-88-dB
Gain-BandwidthProductGBWP-15-MHz
SlewRateSRCOMP1=10pF-6-V/μs
284
HIP6020
FunctionalPinDescriptions
VCC(Pin28)
Providea12VbiassupplyfortheICtothispin.Thispinalso
providesthegatebiaschargeforalltheMOSFETs
controlledbytheIC.Thevoltageatthispinismonitoredfor
Power-OnReset(POR)purposes.
GND(Pin17)
SignalgroundfortheIC.Allvoltagelevelsaremeasured
withrespecttothispin.
PGND(Pin24)
Thisisthepowergroundconnection.Tiethesynchronous
PWMconverter’slowerMOSFETsourcetothispin.
VAUX(Pin16)
The+3.3Vinputvoltageatthispinismonitoredforpower-on
reset(POR)purposes.Connectedto+5Vinput,thispin
providesboostcurrentforthetwolinearregulatoroutput
drivesintheeventbipolarNPNtransistors(insteadof
N-channelMOSFETs)areemployedaspasselements.
PWMCONTROLLERSGATEDRIVERS
UGATE1,2SourceI
UGATE
VCC=12V,V
UGATE1
(orV
UGATE2
)=6V-1-A
UGATE1,2SinkR
UGATE
V
GATE-PHASE
=1V-1.73.5?
LGATESourceI
LGATE
VCC=12V,V
LGATE1
=1V-1-A
LGATESinkR
LGATE
V
LGATE
=1V-1.43.0?
PROTECTION
VSEN1Over-Voltage(VSEN1/DACOUT)VSEN1Rising-115120%
FAULTSourcingCurrentI
OVP
V
FAULT/RT
=2.0V-8.5-mA
OCSET1,2CurrentSourceI
OCSET
V
OCSET
=4.5V
DC
170200230μA
Soft-StartCurrentI
SS
-28-μA
POWERGOOD
VSEN1UpperThreshold
(VSEN1/DACOUT)
VSEN1Rising108-110%
VSEN1Under-Voltage
(VSEN1/DACOUT)
VSEN1Rising92-94%
VSEN1Hysteresis(VSEN1/DACOUT)Upper/LowerThreshold-2-%
PGOODVoltageLowV
PGOOD
I
PGOOD
=-4mA--0.8V
ElectricalSpecificationsRecommendedOperatingConditions,UnlessOtherwiseNoted.RefertoFigures1,2and3(Continued)
PARAMETERSYMBOLTESTCONDITIONSMINTYPMAXUNITS
TypicalPerformanceCurves
FIGURE1.R
T
RESISTANCEvsFREQUENCYFIGURE2.BIASSUPPLYCURRENTvsFREQUENCY
101001000
SWITCHINGFREQUENCY(kHz)
RE
S
I
S
T
ANCE
(
k
?
)
10
100
1000
R
T
PULLUP
TO+12V
R
T
PULLDOWNTOV
SS
1002003004005006007008009001000
I
CC
(m
A
)
SWITCHINGFREQUENCY(kHz)
140
120
100
80
60
40
20
0
C=660pF
C=1500pF
C=3600pF
C=4800pF
C
UGATE1
=C
UGATE2
=C
LGATE1
=C
V
IN
=5V
V
CC
=12V
2-285
HIP6020
SS(Pin12)
Connectacapacitorfromthispintoground.Thiscapacitor,
alongwithaninternal28μAcurrentsource,setsthe
soft-startintervaloftheconverter.
FAULT/RT(Pin13)
Thispinprovidesoscillatorswitchingfrequencyadjustment.
Byplacingaresistor(R
T
)fromthispintoGND,thenominal
200kHzswitchingfrequencyisincreasedaccordingtothe
followingequation:
Conversely,connectingapull-upresistor(R
T
)fromthispin
toVCCreducestheswitchingfrequencyaccordingtothe
followingequation:
Nominally,thevoltageatthispinis1.26V.Intheeventofan
over-voltageorover-currentcondition,thispinisinternally
pulledtoVCC.
PGOOD(Pin8)
PGOODisanopencollectoroutputusedtoindicatethe
statusoftheoutputvoltages.Thispinispulledlowwhenthe
synchronousregulatoroutputisnotwithin±10%ofthe
DACOUTreferencevoltageorwhenanyoftheotheroutputs
arebelowtheirunder-voltagethresholds.
ThePGOODoutputisopenfor‘11111’VIDcode.
VID0,VID1,VID2,VID3,VID4(Pins7,6,5,4and3)
VID0-4aretheTTL-compatibleinputpinstothe5-bitDAC.
Thelogicstatesofthesefivepinsprogramtheinternal
voltagereference(DACOUT).ThelevelofDACOUTsetsthe
microprocessorcoreconverteroutputvoltage,aswellasthe
corespondingPGOODandOVPthresholds.
OCSET1,OCSET2(Pins23and9)
Connectaresistor(R
OCSET
)fromthispintothedrainofthe
respectiveupperMOSFET.R
OCSET
,aninternal200μA
currentsource(I
OCSET
),andtheupperMOSFET’son-
resistance(r
DS(ON)
)settheconverterover-current(OC)trip
pointaccordingtothefollowingequation:
Anover-currenttripcyclesthesoft-startfunction.
ThevoltageatOCSET1pinismonitoredforpower-onreset
(POR)purposes.
PHASE1,PHASE2(Pins26and2)
ConnectthePHASEpinstotherespectivePWMconverter’s
upperMOSFETsource.Thesepinsrepresentthegatedrive
returncurrentpathandareusedtomonitorthevoltagedrop
acrosstheupperMOSFETsforover-currentprotection.
UGATE1,UGATE2(Pins27and1)
ConnectUGATEpinstotherespectivePWMconverter’s
upperMOSFETgate.Thesepinsprovidethegatedrivefor
theupperMOSFETs.
LGATE1(Pin25)
ConnectLGATE1tothesynchronousPWMconverter’s
lowerMOSFETgate.Thispinprovidesthegatedriveforthe
lowerMOSFET.
COMP1andFB1(Pins20,and21)
COMP1andFB1aretheavailableexternalpinsofthe
synchronousPWMregulatorerroramplifier.TheFB1pinis
theinvertinginputoftheerroramplifier.Similarly,the
COMP1pinistheerroramplifieroutput.Thesepinsareused
tocompensatethevoltage-modecontrolfeedbackloopof
thesynchronousPWMconverter.
VSEN1(Pin22)
ThispinisconnectedtothesynchronousPWMconverters’
outputvoltage.ThePGOODandOVPcomparatorcircuits
usethissignaltoreportoutputvoltagestatusandforover-
voltageprotection.
VSEN2(Pin10)
ConnectthispintotheoutputofthestandardbuckPWM
regulator.Thevoltageatthispinisregulatedtothelevel
predeterminedbythelogic-levelstatusoftheSELECTpin.
ThispinisalsomonitoredbythePGOODcomparatorcircuit.
SELECT(Pin11)
ThispindeterminestheoutputvoltageoftheAGPbus
switchingregulator.AlowTTLinputsetstheoutputvoltage
to1.5V,whileahighinputsetstheoutputvoltageto3.3V.
DRIVE3(Pin18)
ConnectthispintothegateofanexternalMOSFET.This
pinprovidesthedriveforthe1.5Vregulator’spass
transistor.
VSEN3(Pin19)
Connectthispintotheoutputofthe1.5Vlinearregulator.
Thispinismonitoredforundervoltageevents.
DRIVE4(Pin15)
ConnectthispintothegateofanexternalMOSFET.This
pinprovidesthedriveforthe1.8Vregulator’spass
transistor.
VSEN4(Pin14)
Connectthispintotheoutputofthelinear1.8Vregulator.
Thispinismonitoredforundervoltageevents.
Description
Operation
TheHIP6020monitorsandpreciselycontrols4outputvoltage
levels(RefertoFigures1,2,and3).Itisdesignedfor
Fs200KHz
510
6
×
R
T
k?()
--------------------+≈
(R
T
toGND)
Fs200KHz
410
7
×
R
T
k?()
---------------------–≈
(R
T
to12V)
I
PEAK
I
OCSET
R
OCSET
×
r
DSON()
---------------------------------------------------=
286
HIP6020
microprocessorcomputerapplicationswith3.3V,5V,and12V
biasinputfromanATXpowersupply.TheIChas2PWMand
twolinearcontrollers.ThefirstPWMcontroller(PWM1)is
designedtoregulatethemicroprocessorcorevoltage(V
OUT1
).
PWM1controllerdrives2MOSFETs(Q1andQ2)ina
synchronous-rectifiedbuckconverterandregulatesthecore
voltagetoalevelprogrammedbythe5-bitdigital-to-analog
converter(DAC).ThesecondPWMcontroller(PWM2)is
designedtoregulatetheadvancedgraphicsport(AGP)bus
voltage(V
OUT2
).PWM2controllerdrivesaMOSFET(Q3)ina
standardbuckconverterandregulatestheoutputvoltagetoa
digitally-programmablelevelof1.5Vor3.3V.Selectionofeither
outputvoltageisachievedbyapplyingtheproperlogiclevelat
theSELECTpin.Thetwolinearcontrollerssupplythe1.5V
GTLbuspower(V
OUT3
)andthe1.8Vmemorypower(V
OUT4
).
Initialization
TheHIP6020automaticallyinitializesuponreceiptofinput
power.Specialsequencingoftheinputsuppliesisnot
necessary.ThePower-OnReset(POR)functioncontinually
monitorstheinputsupplyvoltages.ThePORmonitorsthe
biasvoltage(+12V
IN
)attheVCCpin,the5Vinputvoltage
(+5V
IN
)ontheOCSET1pin,andthe3.3Vinputvoltage
(+3.3V
IN
)attheVAUXpin.ThenormallevelonOCSET1is
equalto+5V
IN
lessafixedvoltagedrop(seeover-current
protection).ThePORfunctioninitiatessoft-startoperation
afterallsupplyvoltagesexceedtheirPORthresholds.
Soft-Start
ThePORfunctioninitiatesthesoft-startsequence.Initially,the
voltageontheSSpinrapidlyincreasestoapproximately1V
(thisminimizesthesoft-startinterval).Thenaninternal28μA
currentsourcechargesanexternalcapacitor(C
SS
)ontheSS
pinto4.5V.ThePWMerroramplifiersreferenceinputs
(+terminal)andoutputs(COMP1pin)areclampedtoalevel
proportionaltotheSSpinvoltage.AstheSSpinvoltageslews
from1Vto4V,theoutputclampallowsgenerationofPHASE
pulsesofincreasingwidththatchargetheoutputcapacitor(s).
Aftertheoutputvoltageincreasestoapproximately70%ofthe
setvalue,thereferenceinputclampslowstheoutputvoltage
rate-of-riseandprovidesasmoothtransitiontothefinalset
voltage.Additionallybothlinearregulators’referenceinputsare
clampedtoavoltageproportionaltotheSSpinvoltage.This
methodprovidesarapidandcontrolledoutputvoltagerise.
Figure6showsthesoft-startsequenceforthetypical
application.AtT0theSSvoltagerapidlyincreasesto
approximately1V.AtT1,theSSpinanderroramplifier
outputvoltagereachthevalleyoftheoscillator’striangle
wave.Theoscillator’striangularwaveformiscomparedto
theclampederroramplifieroutputvoltage.AstheSSpin
voltageincreases,thepulse-widthonthePHASEpin
increases.Theintervalofincreasingpulse-widthcontinues
untileachPWMoutputreachessufficientvoltagetotransfer
controltotheerroramplifierinputreferenceclamp.Ifwe
considerthe3.3Voutput(V
OUT2
)inFigure6,thistime
occursatT2.DuringtheintervalbetweenT2andT3,the
erroramplifierreferencerampstothefinalvalueandthe
converterregulatestheoutputavoltageproportionaltothe
SSpinvoltage.AtT3theinputclampvoltageexceedsthe
referencevoltageandtheoutputvoltageisinregulation.
TheremainingoutputsarealsoprogrammedtofollowtheSS
pinvoltage.ThePGOODsignaltoggles‘high’whenalloutput
voltagelevelshaveexceededtheirunder-voltagelevels.See
theSoft-StartIntervalsectionunderApplicationsGuidelines
foraproceduretodeterminethesoft-startinterval.
FaultProtection
Allfouroutputsaremonitoredandprotectedagainstextreme
overload.Asustainedoverloadonanyoutputoranover-
voltageonV
OUT1
output(VSEN1)disablesalloutputsand
drivestheFAULT/RTpintoVCC.
FIGURE3.SOFT-STARTINTERVAL
0V
0V
0V
TIME
PGOOD
SOFT-START
(1V/DIV)
OUTPUT
(0.5V/DIV)
VOLTAGES
V
OUT1
(DAC=2.5V)
V
OUT2
(=3.3V)
V
OUT4
(=1.8V)
V
OUT3
(=1.5V)
T1T2T3T0T4
2-287
HIP6020
Figure7showsasimplifiedschematicofthefaultlogic.An
over-voltagedetectedonVSEN1immediatelysetsthefault
latch.Asequenceofthreeover-currentfaultsignalsalso
setsthefaultlatch.Theover-currentlatchissetdependent
uponthestatesoftheover-current(OC1andOC2),linear
under-voltage(LUV)andthesoft-startsignals.Awindow
comparatormonitorstheSSpinandindicateswhenC
SS
is
fullychargedto4.5V(UPsignal).Anunder-voltageoneither
linearoutput(VSEN3andVSEN4)isignoreduntilafterthe
soft-startinterval(T4inFigure6).ThisallowsV
OUT3
and
V
OUT4
toincreasewithoutfaultatstart-up.Cyclingthebias
inputvoltage(+12V
IN
ontheVCCpinoffthenon)resetsthe
counterandthefaultlatch.
Over-VoltageProtection
Duringoperation,ashortacrossthesynchronousPWM
upperMOSFET(Q1)causesV
OUT1
toincrease.Whenthe
outputexceedstheover-voltagethresholdof115%of
DACOUT,theover-voltagecomparatortripstosetthefault
latchandturnsthelowerMOSFET(Q2)on.Thisblowsthe
inputfuseandreducesV
OUT1
.Thefaultlatchraisesthe
FAULT/RTpintoVCC.
Aseparateover-voltagecircuitprovidesprotectionduring
theinitialapplicationofpower.ForvoltagesontheVCCpin
belowthepower-onreset(andabove~4V),theoutputlevel
ismonitoredforvoltagesabove1.3V.ShouldVSEN1
exceedthislevel,thelowerMOSFET,Q2isdrivenon.
Over-CurrentProtection
Alloutputsareprotectedagainstexcessiveover-currents.
BothPWMcontrollersusetheupperMOSFET’son-
resistance,r
DS(ON)
tomonitorthecurrentforprotection
againstshortedoutputs.Bothlinearregulatorsmonitortheir
respectiveVSENpinsforunder-voltagetoprotectagainst
excessivecurrents.
Figure8illustratestheover-currentprotectionwithan
overloadonOUT2.TheoverloadisappliedatT0andthe
currentincreasesthroughtheinductor(L
OUT2
).AttimeT1,
theOVER-CURRENT2comparatortripswhenthevoltage
acrossQ3(i
D
?r
DS(ON)
)exceedsthelevelprogrammedby
R
OCSET
.Thisinhibitsalloutputs,dischargesthesoft-start
capacitor(C
SS
)witha28μAcurrentsink,andincrementsthe
counter.C
SS
rechargesatT2andinitiatesasoft-startcycle
withtheerroramplifiersclampedbysoft-start.WithOUT2still
overloaded,theinductorcurrentincreasestotriptheover-
currentcomparator.Again,thisinhibitsalloutputs,butthe
soft-startvoltagecontinuesincreasingto4.5Vbefore
discharging.Thecounterincrementsto2.Thesoft-startcycle
repeatsatT3andtripstheover-currentcomparator.TheSS
pinvoltageincreasesto4.5VatT4andthecounter
incrementsto3.Thissetsthefaultlatchtodisablethe
converter.ThefaultisreportedontheFAULT/RTpin.
ThePWM1controlleroperatesinthesamewayasPWM2to
over-currentfaults.Additionally,thetwolinearcontrollers
monitortheVSENpinsforanunder-voltage.Should
excessivecurrentscauseVSEN3orVSEN4tofallbelowthe
linearunder-voltagethreshold,theLUVsignalsetstheover-
currentlatch,providingC
SS
is
fullycharged.BlankingtheLUV
signalduringtheC
SS
chargeintervalallowsthelinear
outputstobuildabovetheunder-voltagethresholdduring
normaloperation.Cyclingthebiasinputpoweroffthenon
resetsthecounterandthefaultlatch.
FAULT
LATCH
S
R
Q
POR
COUNTER
OC1
OV
OC2
LUV
+
-
+
-
0.15V
4V
SS
VCC
FAULT
R
FIGURE4.FAULTLOGIC-SIMPLIFIEDSCHEMATIC
UP
OVER-
CURRENT
LATCH
INHIBIT
S
R
Q
FIGURE5.OVER-CURRENTOPERATION
INDUCT
O
R
C
URRE
NT
S
O
F
T
-
S
T
ART
0A
0V
2V
4V
TIME
T1T2T3T0T4
F
AUL
T
/
RT
0V
10V
OVERLOAD
APPLIED
FAULT
REPORTED
COUNT
=1
COUNT
=2
COUNT
=3
288
HIP6020
Resistors(R
OCSET1
andR
OCSET2
)programtheover-current
triplevelsforeachPWMconverter.AsshowninFigure9,the
internal200μAcurrentsink(I
OCSET
)developsavoltageacross
R
OCSET
(V
SET
)thatisreferencedtoV
IN
.TheDRIVEsignal
enablestheover-currentcomparator(OVER-CURRENT1or
OVER-CURRENT2).Whenthevoltageacrosstheupper
MOSFET(V
DS(ON)
)exceedsV
SET
,theover-current
comparatortripstosettheover-currentlatch.BothV
SET
and
V
DS
arereferencedtoV
IN
andasmallcapacitoracross
R
OCSET
helpsV
OCSET
trackthevariationsofV
IN
dueto
MOSFETswitching.Theover-currentfunctionwilltripatapeak
inductorcurrent(I
PEAK)
determinedby:
TheOCtrippointvarieswithMOSFET’srDS(ON)
temperaturevariations.Toavoidover-currenttrippinginthe
normaloperatingloadrange,determinetheROCSET
resistorvaluefromtheequationabovewith:
1.Themaximumr
DS(ON)
atthehighestjunctiontemperature
2.TheminimumI
OCSET
fromthespecificationtable
3.DetermineI
PEAK
forI
PEAK
>I
OUT(MAX)
+(?I)/2,
where?Iistheoutputinductorripplecurrent.
Foranequationfortheripplecurrentseethesectionunder
componentguidelinestitled‘OutputInductorSelection’.
OUT1VoltageProgram
TheoutputvoltageofthePWM1converterisprogrammedto
discretelevelsbetween1.3V
DC
and3.5V
DC
.Thisoutput
(OUT1)isdesignedtosupplythecorevoltageofIntel’s
advancedmicroprocessors.Thevoltageidentification(VID)
pinsprogramaninternalvoltagereference(DACOUT)witha
TTL-compatible5-bitdigital-to-analogconverter(DAC).The
levelofDACOUTalsosetsthePGOODandOVPthresholds.
Table1specifiestheDACOUTvoltageforthedifferent
combinationsofconnectionsontheVIDpins.TheVIDpins
canbeleftopenforalogic1input,becausetheyareinternally
pulleduptoaninternalvoltageofabout5Vbya10μAcurrent
source.ChangingtheVIDinputsduringoperationisnot
recommendedandcouldtogglethePGOODsignaland
exercisetheover-voltageprotection.‘11111’VIDpin
combinationdisablestheICandopensthePGOODpin.
OUT2VoltageSelection
TheAGPregulatoroutputvoltageisinternallysettooneof
twodiscretelevels,basedonthestatusoftheSELECTpin.
SELECTpinisinternallypulled‘high’,suchthatleftopen,
theAGPoutputvoltageisbydefaultsetto3.3V.Theother
discretesettingavailableis1.5V,whichcanbeobtainedby
groundingtheSELECTpinusingajumperoranother
suitablemethodcapableofsinkingafewtensof
microamperes.ThestatusoftheSELECTpincannotbe
changedduringoperationoftheICwithoutimmediately
causingafaultcondition.
FIGURE6.OVER-CURRENTDETECTION
UGATE
OCSET
PHASE
OVER-
CURRENT
+
-
GATE
CONTROL
VCC
OC
200μA
V
DS
i
D
V
SET
R
OCSET
V
IN
=+5V
OVER-CURRENTTRIP:
I
OCSET
+
+
PWM
DRIVE
i
D
r
DSON()
×I
OCSET
R
OCSET
×>
V
DS
V
SET
>
V
PHASE
V
IN
V
DS
–=
V
OCSET
V
IN
V
SET
–=
I
PEAK
=
I
OCSET
R
OCSET
×
r
DSON()
---------------------------------------------------
2-289
HIP6020
ApplicationGuidelines
Soft-StartInterval
Initially,thesoft-startfunctionclampstheerroramplifier’soutput
ofthePWMconverters.ThisgeneratesPHASEpulsesof
increasingwidththatchargetheoutputcapacitor(s).Afterthe
outputvoltageincreasestoapproximately70%ofthesetvalue,
thereferenceinputoftheerroramplifierisclampedtoavoltage
proportionaltotheSSpinvoltage.Theresultingoutputvoltages
start-upasshowninFigure6.
Thesoft-startfunctioncontrolstheoutputvoltagerateofrise
tolimitthecurrentsurgeatstart-up.Thesoft-startinterval
andthesurgecurrentareprogrammedbythesoft-start
capacitor,C
SS
.Programmingafastersoft-startinterval
increasesthepeaksurgecurrent.Thepeaksurgecurrent
occursduringtheinitialoutputvoltageriseto70%oftheset
value.Usingtherecommended0.1μFsoftstartcapacitor
insuresalloutputvoltagesrampuptotheirsetvalueswithin
10msoftheinputvoltagesreachingPORlevels.
Shutdown
NeitherPWMoutputswitchesuntilthesoft-startvoltage
(V
SS
)exceedstheoscillator’svalleyvoltage.Additionally,
thereferenceoneachlinear’samplifierisclampedtothe
soft-startvoltage.HoldingtheSSpinlow(withanopendrain
oropencollectorsignal)turnsoffallfourregulators.
The‘11111’VIDcode,alsoshutsdowntheIC.
LayoutConsiderations
MOSFETsswitchveryfastandefficiently.Thespeedwith
whichthecurrenttransitionsfromonedevicetoanother
causesvoltagespikesacrosstheinterconnecting
impedancesandparasiticcircuitelements.Thevoltage
spikescandegradeefficiency,radiatenoiseintothecircuit,
andleadtodeviceover-voltagestress.Carefulcomponent
layoutandprintedcircuitdesignminimizesthevoltage
spikesintheconverter.Consider,asanexample,theturn-
offtransitionoftheupperMOSFET.Priortoturn-off,the
upperMOSFETwascarryingthefullloadcurrent.Duringthe
turn-off,currentstopsflowingintheupperMOSFETandis
pickedupbythelowerMOSFETorSchottkydiode.Any
inductanceintheswitchedcurrentpathgeneratesalarge
voltagespikeduringtheswitchinginterval.Careful
componentselection,tightlayoutofthecriticalcomponents,
andshort,widecircuittracesminimizethemagnitudeof
voltagespikes.
TherearetwosetsofcriticalcomponentsinaDC-DC
converterusingaHIP6020controller.Theswitchingpower
componentsarethemostcriticalbecausetheyswitchlarge
amountsofenergy,andassuch,theytendtogenerate
equallylargeamountsofnoise.Thecriticalsmallsignal
componentsarethoseconnectedtosensitivenodesor
thosesupplyingcriticalbypasscurrent.
ThepowercomponentsandthecontrollerICshouldbe
placedfirst.Locatetheinputcapacitors,especiallythehigh-
frequencyceramicde-couplingcapacitors,closetothe
powerswitches.Locatetheoutputinductorandoutput
capacitorsbetweentheMOSFETsandtheload.Locatethe
PWMcontrollerclosetotheMOSFETs.
Thecriticalsmallsignalcomponentsincludethebypass
capacitorforVCCandthesoft-startcapacitor,C
SS
.Locate
thesecomponentsclosetotheirconnectingpinsonthe
controlIC.MinimizeanyleakagecurrentpathsfromSS
node,sincetheinternalcurrentsourceisonly28μA.
Amulti-layerprintedcircuitboardisrecommended.Figure
10showstheconnectionsofthecriticalcomponentsinthe
converter.NotethatthecapacitorsC
IN
andC
OUT
each
couldrepresentnumerousphysicalcapacitors.Dedicateone
solidlayerforagroundplaneandmakeallcritical
componentgroundconnectionswithviastothislayer.
Dedicateanothersolidlayerasapowerplaneandbreakthis
TABLE1.OUT1VOLTAGEPROGRAM
PINNAMENOMINAL
DACOUT
VOLTAGEVID4VID3VID2VID1VID0
011111.30
011101.35
011011.40
011001.45
010111.50
010101.5
010011.60
010001.65
001111.70
001101.75
001011.80
001001.85
000111.90
000101.95
000012.0
000002.05
111110
111102.1
111012.
111002.3
110112.4
110102.5
110012.6
110002.7
101112.8
101102.9
101013.0
101003.1
100113.2
100103.
100013.4
100003.5
NOTE:0=connectedtoGND,1=openorconnectedto5Vthrough
pull-upresistors
290
HIP6020
planeintosmallerislandsofcommonvoltagelevels.The
powerplaneshouldsupporttheinputpowerandoutput
powernodes.Usecopperfilledpolygonsonthetopand
bottomcircuitlayersforthePHASEnodes,butdonot
unnecessarilyoversizetheseparticularislands.Sincethe
PHASEnodesaresubjectedtoveryhighdV/dtvoltages,the
straycapacitorformedbetweentheseislandsandthe
surroundingcircuitrywilltendtocoupleswitchingnoise.Use
theremainingprintedcircuitlayersforsmallsignalwiring.
ThewiringtracesfromthecontrolICtotheMOSFETgate
andsourceshouldbesizedtocarry2Apeakcurrents.
PWM1ControllerFeedbackCompensation
BothPWMcontrollersusevoltage-modecontrolforoutput
regulation.Thissectionhighlightsthedesignconsideration
foravoltage-modecontrollerrequiringexternal
compensation.Applythesemethodsandconsiderations
onlytothesynchronousPWMcontroller.Theconsiderations
forthestandardPWMcontrollerarepresentedseparately.
Figure11highlightsthevoltage-modecontrolloopfora
synchronous-rectifiedbuckconverter.Theoutputvoltage
(V
OUT
)isregulatedtotheReferencevoltagelevel.The
referencevoltagelevelistheDACoutputvoltage(DACOUT)
forPWM1.Theerroramplifieroutput(V
E/A
)iscomparedwith
theoscillator(OSC)triangularwavetoprovideapulse-width
modulatedwavewithanamplitudeofV
IN
atthePHASEnode.
ThePWMwaveissmoothedbytheoutputfilter(L
O
andC
O
).
Themodulatortransferfunctionisthesmall-signaltransfer
functionofV
OUT
/V
E/A
.ThisfunctionisdominatedbyaDC
Gain,givenbyV
IN
/V
OSC
,andshapedbytheoutputfilter,
withadoublepolebreakfrequencyatF
LC
andazeroat
F
ESR
.
ModulatorBreakFrequencyEquations
Thecompensationnetworkconsistsoftheerroramplifier
(internaltotheHIP6020)andtheimpedancenetworksZ
IN
and
Z
FB
.Thegoalofthecompensationnetworkistoprovidea
closedlooptransferfunctionwithhigh0dBcrossingfrequency
(f
0dB
)andadequatephasemargin.Phasemarginisthe
differencebetweentheclosedloopphaseatf
0dB
and180
degrees.Theequationsbelowrelatethecompensation
network’spoles,zerosandgaintothecomponents(R1,R2,
R3,C1,C2,andC3)inFigure11.Usetheseguidelinesfor
locatingthepolesandzerosofthecompensationnetwork:
1.PickGain(R2/R1)fordesiredconverterbandwidth
2.Place1
ST
ZeroBelowFilter’sDoublePole(~75%F
LC
)
3.Place2
ND
ZeroatFilter’sDoublePole
4.Place1
ST
PoleattheESRZero
5.Place2
ND
PoleatHalftheSwitchingFrequency
6.CheckGainagainstErrorAmplifier’sOpen-LoopGain
7.EstimatePhaseMargin-RepeatifNecessary
FIGURE7.PRINTEDCIRCUITBOARDPOWERPLANESAND
ISLANDS
V
OUT1
Q1
Q2
Q3
Q4
C
SS
+12V
C
VCC
VIACONNECTIONTOGROUNDPLANE
ISLANDONPOWERPLANELAYER
ISLANDONCIRCUITPLANELAYER
L
OUT1
C
OUT1
CR1
HIP6020
C
IN
C
OUT2
V
OUT2
V
OUT3
+5V
IN
SS
PGND
LGATE1
UGATE1
PHASE1
DRIVE3
PHASE2
KEY
L
OUT2
GNDVCC
UGATE2
OCSET1
OCSET2
R
OCSET1
R
OCSET2
C
OCSET1
C
OCSET2
LO
A
D
V
OUT4
DRIVE4
+3.3V
IN
L
IN
CR2
Q5
C
OUT3
C
OUT4
LO
A
D
LO
A
D
LO
A
D
FIGURE8.VOLTAGE-MODEBUCKCONVERTER
COMPENSATIONDESIGN
V
OUT
OSC
REFERENCE
L
O
C
O
ESR
V
IN
?V
OSC
ERROR
AMP
PWM
DRIVER
(PARASITIC)
Z
FB
+
-
DACOUT
R1
R3R2
C3
C2
C1
COMP
V
OUT
FB
Z
FB
HIP6020
Z
IN
COMP
DRIVER
DETAILEDCOMPENSATIONCOMPONENTS
PHASE
V
E/A
+
-
+
-
Z
IN
F
LC
1
2πL
O
C
O
××
---------------------------------------=F
ESR
1
2πESRC
O
××
-----------------------------------------=
2-291
HIP6020
CompensationBreakFrequencyEquations
Figure12showsanasymptoticplotoftheDC-DCconverter’s
gainvs.frequency.TheactualModulatorGainhasahighgain
peakdependentonthequalityfactor(Q)oftheoutputfilter,
whichisnotshowninFigure12.Usingtheaboveguidelines
shouldyieldaCompensationGainsimilartothecurveplotted.
Theopenlooperroramplifiergainboundsthecompensation
gain.CheckthecompensationgainatF
P2
withthecapabilities
oftheerroramplifier.TheClosedLoopGainisconstructedon
thelog-loggraphofFigure12byaddingtheModulatorGain(in
dB)totheCompensationGain(indB).Thisisequivalentto
multiplyingthemodulatortransferfunctiontothecompensation
transferfunctionandplottingthegain.
Thecompensationgainusesexternalimpedancenetworks
Z
FB
andZ
IN
toprovideastable,highbandwidth(BW)
overallloop.Astablecontrolloophasagaincrossingwith
-20dB/decadeslopeandaphasemargingreaterthan
45degrees.Includeworstcasecomponentvariationswhen
determiningphasemargin.
PWM2ControllerFeedbackCompensation
Toreducethenumberofexternalsmall-signalcomponents
requiredbyatypicalapplication,thestandardPWM
controllerisinternallystabilized.Theonlystabilitycriteria
thatneedstobemetrelatestheminimumvalueoftheoutput
inductortotheequivalentESRoftheoutputcapacitorbank,
asshowninthefollowingequation:
where
L
OUT(MIN)
-minimumoutputinductorvalueatfulloutput
current
ESR
OUT
-equivalentESRoftheoutputcapacitorbank
BW-desiredconverterbandwidth(nottoexceed0.25to
0.30oftheswitchingfrequency)
Thedesignprocedureforthisoutputshouldfollowthe
followingsteps:
1.Choosenumberandtypeofoutputcapacitorstomeetthe
outputtransientrequirementsbasedonthedynamic
loadingcharacteristicsoftheoutput.
2.DeterminetheequivalentESRoftheoutputcapacitor
bankandcalculateminimumoutputinductorvalue.
3.Verifythatchoseninductormeetsthisminimumvalue
criteria(atfulloutputload).Itisrecommendedthecho-
senoutputinductorbenomorethan30%saturatedat
fulloutputload.
OscillatorSynchronization
ThePWMcontrollersuseatrianglewaveforcomparison
withtheerroramplifieroutputtoprovideapulse-width
modulatedsignal.Shouldtheoutputvoltageofthetwo
convertersbeprogrammedclosetoeachother,thencross-
talkbetweentheconverterscouldcausenon-uniform
PHASEpulse-widthsandincreasedoutputvoltageripple.
TheHIP6020avoidsthisproblembysynchronizingthetwo
converters180degreesoutofphaseforoutputvoltage
settingswithinthesamerange.Therefore,forbothoutput
voltagesettingslessthan2.4Vorbothoutputvoltage
settingsgreaterorequalto2.4V,PWM1operatesoutof
phasewithPWM2.ForonePWMoutputvoltagesetting
below2.4VandtheotherPWMoutputvoltagesettingof
2.4Vandabove,PWM1operatesinphasewithPWM2.
ComponentSelectionGuidelines
OutputCapacitorSelection
Theoutputcapacitorsforeachoutputhaveunique
requirements.Ingeneraltheoutputcapacitorsshouldbe
selectedtomeetthedynamicregulationrequirements.
Additionally,thePWMconvertersrequireanoutput
capacitortofilterthecurrentripple.Theloadtransientforthe
microprocessorcorerequireshighqualitycapacitorsto
supplythehighslewrate(di/dt)currentdemands.
PWMOutputCapacitors
Modernmicroprocessorsproducetransientloadrates
above1A/ns.Highfrequencycapacitorsinitiallysupplythe
transientcurrentandslowtheloadrate-of-changeseenby
thebulkcapacitors.Thebulkfiltercapacitorvaluesare
generallydeterminedbytheESR(effectiveseries
resistance)andvoltageratingrequirementsratherthan
actualcapacitancerequirements.
F
Z1
1
2πR×2C1×
-----------------------------------=
F
Z2
1
2πR1R3+()C3××
-------------------------------------------------------=
F
P1
1
2πR
2
C1C2×
C1C2+
----------------------
??
??
××
-------------------------------------------------------=
F
P2
1
2πR×3C3×
-----------------------------------=
100
80
60
40
20
0
-20
-40
-60
F
P1
F
Z2
10M1M100K10K1K10010
OPENLOOP
ERRORAMPGAIN
F
Z1
F
P2
F
LC
F
ESR
COMPENSATION
GA
I
N
(d
B
)
FREQUENCY(Hz)
GAIN
MODULATOR
GAIN
FIGURE9.ASYMPTOTICBODEPLOTOFCONVERTERGAIN
CLOSEDLOOP
GAIN
20
V
IN
V
PP–
------------------
??
??
??
log
20
R2
R1
--------
??
??
log
L
OUTMIN()
ESR
OUT
10
1.75
×
2π×BW×
------------------------------------------------=
292
HIP6020
Highfrequencydecouplingcapacitorsshouldbeplacedas
closetothepowerpinsoftheloadasphysicallypossible.Be
carefulnottoaddinductanceinthecircuitboardwiringthat
couldcanceltheusefulnessoftheselowinductance
components.Consultwiththemanufactureroftheloadon
specificdecouplingrequirements.
Useonlyspecializedlow-ESRcapacitorsintendedfor
switching-regulatorapplicationsforthebulkcapacitors.The
bulkcapacitor’sESRdeterminestheoutputripplevoltageand
theinitialvoltagedropfollowingahighslew-ratetransient’s
edge.Analuminumelectrolyticcapacitor’sESRvalueis
relatedtothecasesizewithlowerESRavailableinlarger
casesizes.However,theequivalentseriesinductance(ESL)
ofthesecapacitorsincreaseswithcasesizeandcanreduce
theusefulnessofthecapacitortohighslew-ratetransient
loading.Unfortunately,ESLisnotaspecifiedparameter.
Workwithyourcapacitorsupplierandmeasurethe
capacitor’simpedancewithfrequencytoselectasuitable
component.Inmostcases,multipleelectrolyticcapacitorsof
smallcasesizeperformbetterthanasinglelargecase
capacitor.
LinearOutputCapacitors
Theoutputcapacitorsforthelinearregulatorsprovide
dynamicloadcurrent.ThuscapacitorsC
OUT3
andC
OUT4
shouldbeselectedfortransientloadregulation.
PWMOutputInductorSelection
EachPWMconverterrequiresanoutputinductor.The
outputinductorisselectedtomeettheoutputvoltageripple
requirementsandsetstheconverter’sresponsetimetoa
loadtransient.Additionally,PWM2outputinductorhasto
meettheminimumvaluecriteriaforloopstabilityas
describedinparagraph‘PWM2ControllerFeedback
Compensation’.Theinductorvaluedeterminesthe
converter’sripplecurrentandtheripplevoltageisafunction
oftheripplecurrent.Theripplevoltageandcurrentare
approximatedbythefollowingequations:
Increasingthevalueofinductancereducestheripplecurrent
andvoltage.However,thelargeinductancevaluesincrease
theconverter’sresponsetimetoaloadtransient.
Oneoftheparameterslimitingtheconverter’sresponsetoa
loadtransientisthetimerequiredtochangetheinductor
current.Givenasufficientlyfastcontrolloopdesign,the
HIP6020willprovideeither0%or100%dutycyclein
responsetoaloadtransient.Theresponsetimeisthetime
intervalrequiredtoslewtheinductorcurrentfromaninitial
currentvaluetothepost-transientcurrentlevel.Duringthis
intervalthedifferencebetweentheinductorcurrentandthe
transientcurrentlevelmustbesuppliedbytheoutput
capacitor(s).Minimizingtheresponsetimecanminimizethe
outputcapacitancerequired.
Theresponsetimetoatransientisdifferentforthe
applicationofloadandtheremovalofload.Thefollowing
equationsgivetheapproximateresponsetimeintervalfor
applicationandremovalofatransientload:
where:I
TRAN
isthetransientloadcurrentstep,t
RISE
isthe
responsetimetotheapplicationofload,andt
FALL
isthe
responsetimetotheremovalofload.Besuretocheckboth
oftheseequationsattheminimumandmaximumoutput
levelsfortheworstcaseresponsetime.
InputCapacitorSelection
Theimportantparametersforthebulkinputcapacitorarethe
voltageratingandtheRMScurrentrating.Forreliable
operation,selectbulkinputcapacitorswithvoltageand
currentratingsabovethemaximuminputvoltageandlargest
RMScurrentrequiredbythecircuit.Thecapacitorvoltage
ratingshouldbeatleast1.25timesgreaterthanthe
maximuminputvoltage.TheRMScurrentratingrequirement
fortheinputcapacitorsofabuckregulatorisapproximately
1/2ofthesummationoftheDCoutputloadcurrent.
Useamixofinputbypasscapacitorstocontrolthevoltage
overshootacrosstheMOSFETs.Useceramiccapacitance
forthehighfrequencydecouplingandbulkcapacitorsto
supplytheRMScurrent.Smallceramiccapacitorscanbe
placedveryclosetotheupperMOSFETtosuppressthe
voltageinducedintheparasiticcircuitimpedances.
Forathrough-holedesign,severalelectrolyticcapacitors
(PanasonicHFQseriesorNichiconPLseriesorSanyo
MV-GXorequivalent)maybeneeded.Forsurfacemount
designs,solidtantalumcapacitorscanbeused,butcaution
mustbeexercisedwithregardtothecapacitorsurgecurrent
rating.Thesecapacitorsmustbecapableofhandlingthe
surgecurrentatpower-up.TheTPSseriesavailablefrom
AVX,andthe593DseriesfromSpraguearebothsurge
currenttested.
MOSFETSelection/Considerations
TheHIP6020requires5externaltransistors.Three
N-channelMOSFETsareemployedbythePWMconverters.
TheGTLandmemorylinearcontrollerscaneachdrivea
MOSFEToraNPNbipolarasapasstransistor.Allthese
transistorsshouldbeselectedbaseduponr
DS(ON)
,current
gain,saturationvoltages,gatesupplyrequirements,and
thermalmanagementconsiderations.
PWM1MOSFETSelectionandConsiderations
Inhigh-currentPWMapplications,theMOSFETpower
dissipation,packageselectionandheatsinkarethedominant
designfactors.Thepowerdissipationincludestwoloss
components;conductionlossandswitchingloss.Theselosses
aredistributedbetweentheupperandlowerMOSFETs
accordingtothedutyfactor.Theconductionlossesarethe
?I
V
IN
V
OUT
–
F
S
L×
-------------------------------
V
OUT
V
IN
----------------×=
V
OUT
?I?ESR×=
t
RISE
L
O
I
TRAN
×
V
IN
V
OUT
–
-------------------------------=t
FALL
L
O
I
TRAN
×
V
OUT
------------------------------=
2-293
HIP6020
maincomponentofpowerdissipationforthelowerMOSFETs.
OnlytheupperMOSFEThassignificantswitchinglosses,since
thelowerdeviceturnsonandoffintonearzerovoltage.
Theequationspresentedassumelinearvoltage-current
transitionsanddonotmodelpowerlossduetothereverse
recoveryofthelowerMOSFET’sbodydiode.Thegate
chargelossesaredissipatedbytheHIP6020anddon''theat
theMOSFETs.However,largegate-chargeincreasesthe
switchingtime,t
SW
,whichincreasestheupperMOSFET
switchinglosses.EnsurethatbothMOSFETsarewithintheir
maximumjunctiontemperatureathighambienttemperature
bycalculatingthetemperatureriseaccordingtopackage
thermalresistancespecifications.Aseparateheatsinkmay
benecessarydependinguponMOSFETpower,package
type,ambienttemperatureandairflow.
Ther
DS(ON)
isdifferentforthetwoequationsaboveevenif
thesamedeviceisusedforboth.Thisisbecausethegate
driveappliedtotheupperMOSFETisdifferentthanthe
lowerMOSFET.Figure13showsthegatedrivewherethe
upperMOSFET’sgate-to-sourcevoltageisapproximately
V
CC
lesstheinputsupply.For+5Vmainpowerand+12VDC
forthebias,thegate-to-sourcevoltageofQ1is7V.Thelower
gatedrivevoltageis+12VDC.Alogic-levelMOSFETisa
goodchoiceforQ1andalogic-levelMOSFETcanbeusedfor
Q2ifitsabsolutegate-to-sourcevoltageratingexceedsthe
maximumvoltageappliedtoV
CC
.
RectifierCR1isaclampthatcatchesthenegativeinductor
swingduringthedeadtimebetweentheturnoffofthelower
MOSFETandtheturnonoftheupperMOSFET.Thediode
mustbeaSchottkytypetopreventthelossyparasitic
MOSFETbodydiodefromconducting.Itisacceptabletoomit
thediodeandletthebodydiodeofthelowerMOSFETclamp
thenegativeinductorswing,butefficiencycoulddrop,insome
cases,oneortwopercentasaresult.Thediode''srated
reversebreakdownvoltagemustbegreaterthanthe
maximuminputvoltage.
PWM2MOSFETandSchottkySelection
ThepowerdissipationinPWM2converterissimilarto
PWM1exceptthatthepowerlossesofthelowerdeviceisin
aSchottkyandnotaMOSFET.ThepowerlossesofPWM2
converteraredistributedbetweentheupperMOSFETand
theSchottky.Theequationsbelowdescribean
approximationofthisdistributionandassumealinear
voltage-currentswitchingtransitions.
LinearControllersTransistorSelection
TheHIP6020linearcontrollersarecompatiblewithboth
NPNbipolaraswellasN-ChannelMOSFETtransistors.The
maincriteriaforselectionofpasstransistorsforthelinear
regulatorsispackageselectionforefficientremovalofheat.
Thepowerdissipatedinalinearregulatoris
Selectapackageandheatsinkthatmaintainsthejunction
temperaturebelowthemaximumdesiredtemperaturewith
themaximumexpectedambienttemperature.
WhenselectingbipolarNPNtransistorsforusewiththe
linearcontrollers,insurethecurrentgainatthegiven
operatingV
CE
issufficientlylargetoprovidethedesired
outputloadcurrentwhenthebaseisfedwiththeminimum
driveroutputcurrent.
P
UPPER
I
O
2
r
DSON()
×V
OUT
×
V
IN
------------------------------------------------------------
I
O
V
IN
×t
SW
×F
S
×
2
----------------------------------------------------+=
P
LOWER
I
O
2
r
DSON()
×V
IN
V
OUT
–()×
V
IN
---------------------------------------------------------------------------------=
FIGURE10.UPPERGATEDRIVE-DIRECTV
CC
DRIVE
+12V
PGND
HIP6020
GND
LGATE
UGATE
PHASE
VCC
+5VORLESS
NOTE:
NOTE:
V
GS
≈V
CC
Q1
Q2
+
-
V
GS
≈V
CC
-5V
CR1
P
MOS
I
O
2
r
DSON()
×V
OUT
×
V
IN
------------------------------------------------------------
I
O
V
IN
×t
SW
×F
S
×
2
----------------------------------------------------+=
P
SCH
I
O
V
f
×V
IN
V
OUT
–()×
V
IN
-------------------------------------------------------------=
P
LINEAR
I
O
V
IN
V
OUT
–()×=
294
HIP6020
AllIntersilU.S.productsaremanufactured,assembledandtestedutilizingISO9000qualitysystems.
IntersilCorporation’squalitycertificationscanbeviewedatwww.intersil.com/design/quality
Intersilproductsaresoldbydescriptiononly.IntersilCorporationreservestherighttomakechangesincircuitdesign,softwareand/orspecificationsatanytimewithout
notice.Accordingly,thereaderiscautionedtoverifythatdatasheetsarecurrentbeforeplacingorders.InformationfurnishedbyIntersilisbelievedtobeaccurateand
reliable.However,noresponsibilityisassumedbyIntersiloritssubsidiariesforitsuse;norforanyinfringementsofpatentsorotherrightsofthirdpartieswhichmayresult
fromitsuse.NolicenseisgrantedbyimplicationorotherwiseunderanypatentorpatentrightsofIntersiloritssubsidiaries.
ForinformationregardingIntersilCorporationanditsproducts,seewww.intersil.com
HIP6020DC-DCConverterApplicationCircuit
Figure14showsanapplicationcircuitofapowersupplyfor
amicroprocessorcomputersystem.Thepowersupply
providesthemicroprocessorcorevoltage(V
OUT1
),theAGP
busvoltage(V
OUT2
),theGTLbusvoltage(V
OUT3
),andthe
memoryvoltage(V
OUT4
)from+3.3V,+5VDC,and+12VDC.
Fordetailedinformationonthecircuit,includingaBill-of-
Materialsandcircuitboarddescription,seeApplicationNote
AN9836.AlsoseeIntersil’webpage
(http://www.intersil.com)orIntersilAnswerFAX(321-724-
7800),documentnumber99836forthelatestinformation.
VID1
VID2
VID3
VID4
SS
GND
VCC
+5V
IN
VID0
+12V
IN
PGND
VSEN1
PGOOD
LGATE1
UGATE1
OCSET1
PHASE1
Q1,2
POWERGOOD
FB1
COMP1
V
OUT2
VSEN2
UGATE2
Q3
DRIVE3
VSEN3
DRIVE4
C28,29
V
OUT3
V
OUT4
C26,27
C15-22
HIP6020
Q4
L3
+
+
+
+
+
C8
L1
C1-7
C10
C9
R1
V
OUT1
R3
R4
C23
C24
C25
C30
2x1000μF
2x1000μF
C12-14
3x1000μF
1μH
7x1000μF
1μF
1μF
1000pF
8x1000μF
0.1μF
4.2μH
0.22μF
10pF
2.7nF
10.2K
1.62K
GND
(3.3V/1.5V)
(1.5V)
(1.8V)
VSEN4
TYPEDET
SELECT
+3.3V
IN
R6
499K
R5
150K
SD
PHASE2
1.0K
Q5
U1
1
2
3
4
5
6
7
8
9
10
11
12
13
16
15
14
17
18
19
20
21
22
23
24
25
26
27
28
FAULT/RT
VAUX
OCSET2
CR1
C11
1000pF
R2
L2
6.2μH
MBRD835L
2.7K
HUF76107D3S
HUF76107D3S
HUF76107D3S
HUF76143S3S
(1.3V-3.5V)
FIGURE11.POWERSUPPLYAPPLICATIONCIRCUITFORAMICROPROCESSORCOMPUTERSYSTEM
295
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