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GORESET
TheJKFlip-flop
FromtheprevioustutorialwenowknowthatthebasicgatedSRNANDflip-flopsuffersfromtwobasicproblems:
numberone,theS=0andR=0conditionorS=R=0mustalwaysbeavoided,andnumbertwo,ifSorRchangestate
whiletheenableinputishighthecorrectlatchingactionmaynotoccur.Thentoovercomethesetwofundamentaldesign
problemswiththeSRflip-flop,theJKflip-Flopwasdeveloped.
ThissimpleJKflip-Flopisthemostwidelyusedofalltheflip-flopdesignsandisconsideredtobeauniversalflip-flop
circuit.ThesequentialoperationoftheJKflip-flopisexactlythesameasforthepreviousSRflip-flopwiththesame"Set"
and"Reset"inputs.ThedifferencethistimeisthattheJKflip-flophasnoinvalidorforbiddeninputstatesoftheSRLatch
(whenSandRareboth1).
TheJKflip-flopisbasicallyagatedSRflip-flopwiththeadditionofaclockinputcircuitrythatpreventstheillegalorinvalid
outputconditionthatcanoccurwhenbothinputsSandRareequaltologiclevel"1".Duetothisadditionalclockedinput,
aJKflip-flophasfourpossibleinputcombinations,"logic1","logic0","nochange"and"toggle".ThesymbolforaJKflip-
flopissimilartothatofanSRBistableLatchasseenintheprevioustutorialexceptfortheadditionofaclockinput.
TheBasicJKFlip-flop
BoththeSandtheRinputsofthepreviousSRbistablehavenowbeenreplacedbytwoinputscalledtheJandKinputs,
respectivelyafteritsinventorJackKilby.Thenthisequatesto:J=SandK=R.
Thetwo2-inputANDgatesofthegatedSRbistablehavenowbeenreplacedbytwo3-inputNANDgateswiththethird
inputofeachgateconnectedtotheoutputsatQandQ.ThiscrosscouplingoftheSRflip-flopallowsthepreviously
invalidconditionofS="1"andR="1"statetobeusedtoproducea"toggleaction"asthetwoinputsarenowinterlocked.
Ifthecircuitisnow"SET"theJinputisinhibitedbythe"0"statusofQthroughthelowerNANDgate.Ifthecircuitis
"RESET"theKinputisinhibitedbythe"0"statusofQthroughtheupperNANDgate.AsQandQarealwaysdifferentwe
canusethemtocontroltheinput.WhenbothinputsJandKareequaltologic"1",theJKflip-floptogglesasshowninthe
followingtruthtable.
TheTruthTablefortheJKFunction
sameasforthe
SRLatch
InputOutputDescription
JKQQ
0000Memory
nochange0001
0110
ResetQ?00101
1001SetQ?1
1010
toggleaction1101Toggle
1110
ThentheJKflip-flopisbasicallyanSRflip-flopwithfeedbackwhichenablesonlyoneofitstwoinputterminals,either
SETorRESETtobeactiveatanyonetimetherebyeliminatingtheinvalidconditionseenpreviouslyintheSRflip-flop
circuit.AlsowhenboththeJandtheKinputsareatlogiclevel"1"atthesametime,andtheclockinputispulsedeither
"HIGH",thecircuitwill"toggle"fromitsSETstatetoaRESETstate,orvisa-versa.ThisresultsintheJKflip-flopacting
morelikeaT-typetoggleflip-flopwhenbothterminalsare"HIGH".
AlthoughthiscircuitisanimprovementontheclockedSRflip-flopitstillsuffersfromtimingproblemscalled"race"ifthe
outputQchangesstatebeforethetimingpulseoftheclockinputhastimetogo"OFF".Toavoidthisthetimingpulse
period(T)mustbekeptasshortaspossible(highfrequency).AsthisissometimesnotpossiblewithmodernTTLIC''s
themuchimprovedMaster-SlaveJKFlip-flopwasdeveloped.
Themaster-slaveflip-flopeliminatesallthetimingproblemsbyusingtwoSRflip-flopsconnectedtogetherinaseries
configuration.Oneflip-flopactsasthe"Master"circuit,whichtriggersontheleadingedgeoftheclockpulsewhilethe
otheractsasthe"Slave"circuit,whichtriggersonthefallingedgeoftheclockpulse.Thisresultsinthetwosections,the
mastersectionandtheslavesectionbeingenabledduringoppositehalf-cyclesoftheclocksignal.
The74LS73isaDualJKflip-flopIC,whichcontainstwoindividualJKtypebistable''swithinasinglechipenablingsingle
ormaster-slavetoggleflip-flopstobemade.OtherJKflip-flopIC''sincludethe74LS107DualJKflip-flopwithclear,the
74LS109Dualpositive-edgetriggeredJKflip-flopandthe74LS112Dualnegative-edgetriggeredflip-flopwithboth
presetandclearinputs.
DualJKFlip-flop74LS73
TheMaster-SlaveJKFlip-flop
TheMaster-SlaveFlip-FlopisbasicallytwogatedSRflip-flopsconnectedtogetherinaseriesconfigurationwiththe
slavehavinganinvertedclockpulse.TheoutputsfromQandQfromthe"Slave"flip-floparefedbacktotheinputsofthe
"Master"withtheoutputsofthe"Master"flip-flopbeingconnectedtothetwoinputsofthe"Slave"flip-flop.Thisfeedback
configurationfromtheslave''soutputtothemaster''sinputgivesthecharacteristictoggleoftheJKflip-flopasshown
below.
TheMaster-SlaveJKFlip-Flop
TheinputsignalsJandKareconnectedtothegated"master"SRflip-flopwhich"locks"theinputconditionwhilethe
clock(Clk)inputis"HIGH"atlogiclevel"1".Astheclockinputofthe"slave"flip-flopistheinverse(complement)ofthe
"master"clockinput,the"slave"SRflip-flopdoesnottoggle.Theoutputsfromthe"master"flip-flopareonly"seen"bythe
gated"slave"flip-flopwhentheclockinputgoes"LOW"tologiclevel"0".
Whentheclockis"LOW",theoutputsfromthe"master"flip-floparelatchedandanyadditionalchangestoitsinputsare
ignored.Thegated"slave"flip-flopnowrespondstothestateofitsinputspassedoverbythe"master"section.Thenon
the"Low-to-High"transitionoftheclockpulsetheinputsofthe"master"flip-floparefedthroughtothegatedinputsofthe
"slave"flip-flopandonthe"High-to-Low"transitionthesameinputsarereflectedontheoutputofthe"slave"makingthis
typeofflip-flopedgeorpulse-triggered.
Then,thecircuitacceptsinputdatawhentheclocksignalis"HIGH",andpassesthedatatotheoutputonthefalling-
edgeoftheclocksignal.Inotherwords,theMaster-SlaveJKFlip-flopisa"Synchronous"deviceasitonlypassesdata
withthetimingoftheclocksignal.
InthenexttutorialaboutSequentialLogicCircuits,wewilllookatMultivibratorsthatareusedaswaveform
generatorstoproducetheclocksignalstoswitchsequentialcircuits.
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