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2013-11-29 | 阅:  转:  |  分享 
  
TABLEOFCONTENTS:

1.SPI:WhatisSerialPeripheralInterfaceProtocol

2.WhyisSPImorepreferredmoreforPCB

3.Daisy-chainedslaveconfiguration

4.CommunicationinSPI

5.ClockpolarityandphaseinSPI

SPI:WhatisSerialPeripheralInterfaceProtocol

HowDoesCommunicationinSPIWork?

Thecommunicationisinitiatedbythemasterallthetime.The

masterfirstarrangestheclockbyusingafrequency,whichis

lessthanorequaltothemaximumfrequencythattheslave

devicesupports.Now,thisSPImastercontrolsthedata

transferbygeneratingtheclocksignal(SCLK).Themaster

thenselectthedesiredslaveforcommunicationbypullingthe

chipselect(SS)lineofthatparticularslave-peripheralto"low"

stateandactivatestheparticularslaveitwantsto

communicatewithbyusingslave-selectsignal(SS).Onceslaveisselectedthenreceivesortransmitsdatavia

thetwodatalines.Amaster,usuallythehostmicrocontroller,alwaysprovidesclocksignaltoalldevicesona

buswhetheritisselectedornot.Theslavesonthebusthathasnotbeenactivatedbythemasterusingitsslave

selectsignalwilldisregardtheinputclockandMOSIsignalsfromthemaster,andmustnotdriveMISO.That

meansthemasterselectsonlyoneslaveatatime.

Theusageoftheseeachfourpinsmaydependonthedevices.Forexample,SDIpinmaynotbepresentifa

devicedoesnotrequireaninput(ADCforexample),orSDOpinmaynotbepresentifadevicedoesnotrequirean

output(LCDcontrollersforexample).Ifamicrocontrolleronlyneedstotalkto1SPIPeripheraloroneslave,then

theCSpinonthatslavemaybegrounded.Withmultipleslavedevices,anindependentSSsignalisneededfrom

themasterforeachslavedevice.

WhatisthesignificanceofTri-stateoutputinSPI?

Indigitalelectronicsthree-state,tri-state,or3-statelogicallowsanoutputporttoassumeahighimpedancestate

inadditiontothe0and1logiclevels,effectivelyremovingtheoutputfromthecircuit.Thisallowsmultiplecircuits

tosharethesameoutputlineorlines(suchasabuswhichcannotlistentomorethanonedeviceatatime.Most

devices/peripheralshavetri-stateoutputs,whichgoestohighimpedancestate(disconnected)whenthedeviceis

notselected.Deviceswithoutthesetri-stateoutputscannotshareSPIbuswithotherdevices,becausesuch

slave''schip-selectmaynotgetactivated.

Now,ifawaitingperiodisrequired(suchasforanalog-to-digitalconversion)thenthemastermustwaitforatleast

thatperiodoftimebeforestartingtoissueclockcycles.InthemasterSPI,thebitsaresentoutoftheMOSIpin

andreceivedintheMISOpin.ThebitstobeshiftedoutarestoredintheSPIdataregister,SP0DR,andaresent

outmostsignificantbit(bit7)first.Whenbit7ofthemasterisshiftedoutthroughMOSIpin,abitfrombit7ofthe

slaveisbeingshiftedintobit0ofthemasterviatheMISOpin.After8clockpulsesorshifts,thisbitwilleventually

endupinbit7ofthemaster.TheleastsignificantbitcanbesentoutfirstbysettingtheLSBFbitto1intheSPI

ControlRegister.TheclockthatcontrolshowfastthebitsareshiftedoutandintoSP0DRisthesignalSCLK.The

frequencyofthisclockcanbecontrolledbytheSPIbaudrateregister,SP0BR.TheSSpinmustbelowtoselect

aslave.AcompleteSPIsystemisshownbelow.



Afullduplexmeansdatatransmissioncanoccurinbothdirectionsduringeachclockcycle.So,whenthemaster

sendsabitontheMOSIline;theslavereadsitfromthatsamelineandtheslavesendsabitontheMISOline;

themasterreadsitfromthatsameline.Now,tomakedatatransferorganizedshiftregistersareusedwithsome

givenwordsizesuchas8bit(canbemore)inbothmasterandslave.Theyareconnectedinaring.Whilemaster

shiftsregistervalueoutthroughMOSIline,theslaveshiftsdataintoitsshiftregister.

DataareusuallyshiftedoutwiththeMSB-mostsignificantbitfirst,whileshiftinganewLSB-leastsignificantbit

intothesameregister.Afterthatregisterhasbeenshiftedout,themasterandslavehaveexchangedtheirregister

values.Theneachdevicetakesthatvalueanddoesthenecessaryoperationwithit(forexample,writingitto

memory).Iftherearemoredatatobeexchanged,theshiftregistersareloadedwithnewdataandtheprocessis

repeated.Whentherearenomoredatatobetransmitted,themasterstopsitsclock.Normally,itthenrejectsthe

slave.



Thereisa"multiplebytestreammode"availablewithSPIbusinterface.Inthismodethemastercanshiftbytes

continuously.Inthiscase,theslaveselect(SS)iskeptlowuntilallstreamprocessgetsfinished.

SPIdevicessometimesuseanothersignallinetosendaninterruptsignaltoahostCPU.Someoftheexamples

forthesetypeofsignalsarepen-downinterruptsfromtouch-screensensors,thermallimitalertsfromtemperature

sensors,alarmsissuedbyrealtimeclockchips,andheadsetjackinsertionsfromthesoundcodecinacell

phone.

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