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03.12.24
TheFundamentalsofEfficientSynthesizableFiniteStateMachine
DesignusingNC-VerilogandBuildGates
CliffordE.Cummings
SunburstDesign,Inc.
503-641-8446
cliffc@sunburst-design.com
INTERNATIONALCADENCEUSERGROUPCONFERENCE
September16-18,2002
SanJose,California
ICU-2002
SanJose,CA
VotedBestPaper
2ndPlace
InternationalCadenceUsersGroup2002FundamentalsofEfficientSynthesizableFSM
Rev1.1DesignusingNC-VerilogandBuildGates
2
Abstract
ThispaperdetailsprovenRTLcodingstylesforefficientandsynthesizableFiniteStateMachine(FSM)
designusingIEEE-compliantVerilogsimulators.Importanttechniquesrelatedtooneandtwoalwaysblock
stylestocodeFSMswithcombinationaloutputsaregiventoshowwhyusingatwoalwaysblockstyleis
preferred.AnefficientVerilog-uniqueonehotFSMcodingstyleisalsoshown.Reasonsandtechniquesfor
registeringFSMoutputsarealsodetailed.Mythssurroundingerroneousstateencodings,full-caseand
parallel-caseusagearealsodiscussed.ComplianceandenhancementsrelatedtotheIEEE1364-2001
VerilogStandard,theproposedIEEE1364.1VerilogSynthesisInteroperabilityStandardandtheproposed
AccelleraSystemVerilogStandardarealsodiscussed.
1.Introduction
FSMisanabbreviationforFiniteStateMachine.
TherearemanywaystocodeFSMsincludingmanyverypoorwaystocodeFSMs.Thispaperwill
examinesomeofthemostcommonlyusedFSMcodingstyles,theiradvantagesanddisadvantages,and
offerguidelinesfordoingefficientcoding,simulationandsynthesisofFSMdesigns.
ThispaperwillalsodetailAccelleraSystemVerilogenhancementsthatwillfacilitateandenhancefuture
VerilogFSMdesigns.
Inthispaper,multiplereferencesaremadetocombinationalalwaysblocksandsequentialalwaysblocks.
Combinationalalwaysblocksarealwaysblocksthatareusedtocodecombinationallogicfunctionalityand
arestrictlycodedusingblockingassignments(seeCummings[4]).Acombinationalalwaysblockhasa
combinationalsensitivitylist,asensitivitylistwithout"posedge"or"negedge"Verilogkeywords.
Sequentialalwaysblocksarealwaysblocksthatareusedtocodeclockedorsequentiallogicandarealways
codedusingnonblockingassignments(seeCummings[4]).Asequentialalwaysblockhasanedge-based
sensitivylist.
2.MealyandMooreFSMs
AcommonclassificationusedtodescribethetypeofanFSMisMealyandMoorestatemachines[9][10].
Figure1-FiniteStateMachine(FSM)blockdiagram
InternationalCadenceUsersGroup2002FundamentalsofEfficientSynthesizableFSM
Rev1.1DesignusingNC-VerilogandBuildGates
3
AMooreFSMisastatemachinewheretheoutputsareonlyafunctionofthepresentstate.AMealyFSM
isastatemachinewhereoneormoreoftheoutputsisafunctionofthepresentstateandoneormoreofthe
inputs.AblockdiagramforMooreandMealyFSMsisshownFigure1.
3.BinaryEncodedorOnehotEncoded?
CommonclassificationsusedtodescribethestateencodingofanFSMareBinary(orhighlyencoded)and
Onehot.
Abinary-encodedFSMdesignonlyrequiresasmanyflip-flopsasareneededtouniquelyencodethe
numberofstatesinthestatemachine.Theactualnumberofflip-flopsrequiredisequaltotheceilingofthe
log-base-2ofthenumberofstatesintheFSM.
AonehotFSMdesignrequiresaflip-flopforeachstateinthedesignandonlyoneflip-flop(theflip-flop
representingthecurrentor"hot"state)issetatatimeinaonehotFSMdesign.Forastatemachinewith9-
16states,abinaryFSMonlyrequires4flip-flopswhileaonehotFSMrequiresaflip-flopforeachstatein
thedesign(9-16flip-flops).
FPGAvendorsfrequentlyrecommendusingaonehotstateencodingstylebecauseflip-flopsareplentifulin
anFPGAandthecombinationallogicrequiredtoimplementaonehotFSMdesignistypicallysmallerthan
mostbinaryencodingstyles.SinceFPGAperformanceistypicallyrelatedtothecombinationallogicsize
oftheFPGAdesign,onehotFSMstypicallyrunfasterthanabinaryencodedFSMwithlarger
combinationallogicblocks[8].
4.FSMCodingGoals
TodeterminewhatconstitutesanefficientFSMcodingstyle,wefirstneedtoidentifyHDLcodinggoals
andwhytheyareimportant.AftertheHDLcodinggoalshavebeenidentified,wecanthenquantifythe
capabilitiesofvariousFSMcodingstyles.
TheauthorhasidentifiedthefollowingHDLcodinggoalsasimportantwhendoingHDL-basedFSM
design:
?TheFSMcodingstyleshouldbeeasilymodifiedtochangestateencodingsandFSMstyles.
?Thecodingstyleshouldbecompact.
?Thecodingstyleshouldbeeasytocodeandunderstand.
InternationalCadenceUsersGroup2002FundamentalsofEfficientSynthesizableFSM
Rev1.1DesignusingNC-VerilogandBuildGates
4
?Thecodingstyleshouldfacilitatedebugging.
?Thecodingstyleshouldyieldefficientsynthesisresults.
ThreedifferentFSMdesignswillbeexaminedinthispaper.Thefirstisasimple4-stateFSMdesign
labeledfsm_cc4withoneoutput.Thesecondisa10-stateFSMdesignlabeledfsm_cc7withonlyafew
transitionarcsandoneoutput.Thethirdisanother10-stateFSMdesignlabeledfsm_cc8withmultiple
transitionarcsandthreeoutputs.Thecodingeffortstocreatethesethreedesignswillproveinteresting.
5.TwoAlwaysBlockFSMStyle(GoodStyle)
OneofthebestVerilogcodingstylesistocodetheFSMdesignusingtwoalwaysblocks,oneforthe
sequentialstateregisterandoneforthecombinationalnext-stateandcombinationaloutputlogic.
modulefsm_cc4_2
(outputreggnt,
inputdly,done,req,clk,rst_n);
parameter[1:0]IDLE=2''b00,
BBUSY=2''b01,
BWAIT=2''b10,
BFREE=2''b11;
reg[1:0]state,next;
always@(posedgeclkornegedgerst_n)
if(!rst_n)state<=IDLE;
elsestate<=next;
always@(stateordlyordoneorreq)begin
next=2''bx;
gnt=1''b0;
case(state)
IDLE:if(req)next=BBUSY;
elsenext=IDLE;
BBUSY:begin
gnt=1''b1;
if(!done)next=BBUSY;
elseif(dly)next=BWAIT;
elsenext=BFREE;
end
BWAIT:begin
gnt=1''b1;
if(!dly)next=BFREE;
elsenext=BWAIT;
end
BFREE:if(req)next=BBUSY;
elsenext=IDLE;
endcase
end
endmodule
Example1-fsm_cc4design-twoalwaysblockstyle-37linesofcode
5.1Importantcodingstylenotes:
?ParametersareusedtodefinestateencodingsinsteadoftheVerilog`definemacrodefinition
construct[3].Afterparameterdefinitionsarecreated,theparametersareusedthroughouttherestofthe
InternationalCadenceUsersGroup2002FundamentalsofEfficientSynthesizableFSM
Rev1.1DesignusingNC-VerilogandBuildGates
5
design,notthestateencodings.Thismeansthatifanengineerwantstoexperimentwithdifferentstate
encodings,onlytheparametervaluesneedtobemodifiedwhiletherestoftheVerilogcoderemains
unchanged.
?Declarationsaremadeforstateandnext(nextstate)aftertheparameterassignments.
?Thesequentialalwaysblockiscodedusingnonblockingassignments.
?Thecombinationalalwaysblocksensitivitylistissensitivetochangesonthestatevariableandallof
theinputsreferencedinthecombinationalalwaysblock.
?AssignmentswithinthecombinationalalwaysblockaremadeusingVerilogblockingassignments.
?Thecombinationalalwaysblockhasadefaultnextstateassignmentatthetopofthealwaysblock
(seesection5.3fordetailsaboutmakingdefault-Xassignments).
?Defaultoutputassignmentsaremadebeforecodingthecasestatement(thiseliminateslatchesand
reducestheamountofcoderequiredtocodetherestoftheoutputsinthecasestatementand
highlightsinthecasestatementexactlyinwhichstatestheindividualoutput(s)change).
?Inthestateswheretheoutputassignmentisnotthedefaultvalueassignedatthetopofthealways
block,theoutputassignmentisonlymadeonceforeachstate.
?Thereisanif-statement,anelse-if-statementoranelsestatementforeachtransitionarcinthe
FSMstatediagram.ThenumberoftransitionarcsbetweenstatesintheFSMstatediagramshould
equalthenumberofif-else-typestatementsinthecombinationalalwaysblock.
?Foreaseofscanninganddebug,allofthenextassignmentshavebeenplacedinasinglecolumn,as
opposedtofindingnextassignmentsfollowingthecontouroftheRTLcode.
5.2Theunfoundedfearoftransitionstoerroneousstates
Inengineeringschool,wewereallcautionedabout"whathappensifyouFSMgetsintoanerroneous
state?"Ingeneral,thisconcernisbothinvalidorpoorlydeveloped.
IdonotworryaboutmostofmyFSMdesignsgoingtoanerroneousstateanymorethanIworryaboutany
otherregisterinmydesignspontaneouslychangingvalue.Itjustdoesnotoccur!
Thereareexceptions,suchassatellites(subjecttoalphaparticlebombardment)ormedicalimplants
(subjecttoradiationandrequiringextrarobustdesign),plusotherexamples.Inthesesituations,onedoes
havetoworryaboutFSMsgoingtoanerroneousstate,butmostengineeringschoolsfailtonotethat
gettingbacktoaknownstateistypicallynotgoodenough!EventhoughtheFSMisnowinaknownstate,
therestofthehardwareisstillexpectingactivityrelatedtoanotherstate.Itispossibleforthedesignto
lockupwaitingforsignalsthatwillneverarrivebecausetheFSMchangedstateswithoutresettingtherest
ofthedesign.Attheveryleast,theFSMshouldtransitiontoanerrorstatethatcommunicatestotherestof
thedesignthatresettingwilloccuronthenextstatetransition,"getready!"
5.3MakingdefaultnextequalallX''sassignment
Placingadefaultnextstateassignmentonthelineimmediatelyfollowingthealwaysblocksensitivitylistis
averyefficientcodingstyle.Thisdefaultassignmentisupdatedbynext-stateassignmentsinsidethecase
statement.Therearethreetypesofdefaultnext-stateassignmentsthatarecommonlyused:(1)nextissetto
allX''s,(2)nextissettoapredeterminedrecoverystatesuchasIDLE,or(3)nextisjustsettothevalueof
thestateregister.
BymakingadefaultnextstateassignmentofX''s,pre-synthesissimulationmodelswillcausethestate
machineoutputstogounknownifnotallstatetransitionshavebeenexplicitlyassignedinthecase
statement.Thisisausefultechniquetodebugstatemachinedesigns,plustheX''swillbetreatedas"don''t
cares"bythesynthesistool.
SomedesignsrequireanassignmenttoaknownstateasopposedtoassigningX''s.Examplesinclude:
satelliteapplications,medicalapplications,designsthatusetheFSMflip-flopsaspartofadiagnosticscan
InternationalCadenceUsersGroup2002FundamentalsofEfficientSynthesizableFSM
Rev1.1DesignusingNC-VerilogandBuildGates
6
chainandsomedesignsthatareequivalencecheckedwithformalverificationtools.Makingadefaultnext
stateassignmentofeitherIDLEorall0''stypicallysatisfiesthesedesignrequirementsandmakingthe
initialdefaultassignmentmightbeeasierthancodingalloftheexplicitnext-statetransitionassignmentsin
thecasestatement.
5.410-statesimpleFSMdesign-twoalwaysblocks
Example2isthefsm_cc7designimplementedwithtwoalwaysblocks.Usingtwoalwaysblocks,the
fsm_cc7designrequires50linesofcode(codingrequirementsarecomparedinalatersection).
modulefsm_cc7_2
(outputregy1,
inputjmp,go,clk,rst_n);
parameterS0=4''b0000,
S1=4''b0001,
S2=4''b0010,
S3=4''b0011,
S4=4''b0100,
S5=4''b0101,
S6=4''b0110,
S7=4''b0111,
S8=4''b1000,
S9=4''b1001;
reg[3:0]state,next;
always@(posedgeclkornegedgerst_n)
if(!rst_n)state<=S0;
elsestate<=next;
always@(stateorgoorjmp)begin
next=4''bx;
y1=1''b0;
case(state)
S0:if(!go)next=S0;
elseif(jmp)next=S3;
elsenext=S1;
S1:if(jmp)next=S3;
elsenext=S2;
S2:next=S3;
S3:beginy1=1''b1;
if(jmp)next=S3;
elsenext=S4;
end
S4:if(jmp)next=S3;
elsenext=S5;
S5:if(jmp)next=S3;
elsenext=S6;
S6:if(jmp)next=S3;
elsenext=S7;
S7:if(jmp)next=S3;
elsenext=S8;
S8:if(jmp)next=S3;
elsenext=S9;
S9:if(jmp)next=S3;
elsenext=S0;
endcase
end
endmodule
Example2-fsm_cc7design-twoalwaysblockstyle-50linesofcode
InternationalCadenceUsersGroup2002FundamentalsofEfficientSynthesizableFSM
Rev1.1DesignusingNC-VerilogandBuildGates
7
5.510-statemoderatelycomplexFSMdesign-twoalwaysblocks
Example3isthefsm_cc8designimplementedwithtwoalwaysblocks.Usingtwoalwaysblocks,the
fsm_cc8designrequires80linesofcode(codingrequirementsarecomparedinalatersection).
modulefsm_cc8_2
(outputregy1,y2,y3,
inputjmp,go,sk0,sk1,clk,rst_n);
parameterS0=4''b0000,
S1=4''b0001,
S2=4''b0010,
S3=4''b0011,
S4=4''b0100,
S5=4''b0101,
S6=4''b0110,
S7=4''b0111,
S8=4''b1000,
S9=4''b1001;
reg[3:0]state,next;
always@(posedgeclkornegedgerst_n)
if(!rst_n)state<=S0;
elsestate<=next;
always@(stateorjmporgoorsk0orsk1)begin
next=4''bx;
y1=1''b0;
y2=1''b0;
y3=1''b0;
case(state)
S0:if(!go)next=S0;
elseif(jmp)next=S3;
InternationalCadenceUsersGroup2002FundamentalsofEfficientSynthesizableFSM
Rev1.1DesignusingNC-VerilogandBuildGates
8
elsenext=S1;
S1:begin
y2=1''b1;
if(jmp)next=S3;
elsenext=S2;
end
S2:if(jmp)next=S3;
elsenext=S9;
S3:begin
y1=1''b1;
y2=1''b1;
if(jmp)next=S3;
elsenext=S4;
end
S4:if(jmp)next=S3;
elseif(sk0&&!jmp)next=S6;
elsenext=S5;
S5:if(jmp)next=S3;
elseif(!sk1&&!sk0&&!jmp)next=S6;
elseif(!sk1&&sk0&&!jmp)next=S7;
elseif(sk1&&!sk0&&!jmp)next=S8;
elsenext=S9;
S6:begin
y1=1''b1;
y2=1''b1;
y3=1''b1;
if(jmp)next=S3;
elseif(go&&!jmp)next=S7;
elsenext=S6;
end
S7:begin
y3=1''b1;
if(jmp)next=S3;
elsenext=S8;
end
S8:begin
y2=1''b1;
y3=1''b1;
if(jmp)next=S3;
elsenext=S9;
end
S9:begin
y1=1''b1;
y2=1''b1;
y3=1''b1;
if(jmp)next=S3;
elsenext=S0;
end
endcase
end
endmodule
Example3-fsm_cc8design-twoalwaysblockstyle-80linesofcode
InternationalCadenceUsersGroup2002FundamentalsofEfficientSynthesizableFSM
Rev1.1DesignusingNC-VerilogandBuildGates
9
6.OneAlwaysBlockFSMStyle(AvoidThisStyle!)
OneofthemostcommonFSMcodingstylesinusetodayistheonesequentialalwaysblockFSMcoding
style.ThiscodingstyleisverysimilartocodingstylesthatwerepopularizedbyPLDprogramming
languagesofthemid-1980s,suchasABLE.FormostFSMdesigns,theonealwaysblockFSMcoding
styleismoreverbose,moreconfusingandmoreerrorpronethanacomparabletwoalwaysblockcoding
style.
Reconsiderthefsm_cc4designshowninsection5.
modulefsm_cc4_1
(outputreggnt,
inputdly,done,req,clk,rst_n);
parameter[1:0]IDLE=2''d0,
BBUSY=2''d1,
BWAIT=2''d2,
BFREE=2''d3;
reg[1:0]state;
always@(posedgeclkornegedgerst_n)
if(!rst_n)begin
state<=IDLE;
gnt<=1''b0;
end
elsebegin
state<=2''bx;
gnt<=1''b0;
case(state)
IDLE:if(req)begin
state<=BBUSY;
gnt<=1''b1;
end
elsestate<=IDLE;
BBUSY:if(!done)begin
state<=BBUSY;
gnt<=1''b1;
end
elseif(dly)begin
state<=BWAIT;
gnt<=1''b1;
end
elsestate<=BFREE;
BWAIT:if(dly)begin
state<=BWAIT;
gnt<=1''b1;
end
elsestate<=BFREE;
BFREE:if(req)begin
state<=BBUSY;
gnt<=1''b1;
end
elsestate<=IDLE;
endcase
end
endmodule
Example4-fsm_cc4design-onealwaysblockstyle-47linesofcode
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6.1Importantcodingstylenotes:
?Parametersareusedtodefinestateencodings,thesameasthetwoalwaysblockcodingstyle.
?Adeclarationismadeforstate.Notfornext.
?Thereisjustonesequentialalwaysblock,codedusingnonblockingassignments.
?Thethereisstilladefaultstateassignmentbeforethecasestatement,thenthecasestatementtests
thestatevariable.Willthisbeaproblem?No,becausethedefaultstateassignmentismadewitha
nonblockingassignment,sotheupdatetothestatevariablewillhappenattheendofthesimulation
timestep.
?Defaultoutputassignmentsaremadebeforecodingthecasestatement(thisreducestheamountof
coderequiredtocodetherestoftheoutputsinthecasestatement).
?Astateassignmentmustbemadeforeachtransitionarcthattransitionstoastatewheretheoutput
willbedifferentthanthedefaultassignedvalue.Formultipleoutputsandformultipletransitionarcs
intoastatewheretheoutputschange,multiplestateassignmentswillberequired.
?Thestateassignmentsdonotcorrespondtothecurrentstateofthecasestatement,butthestate
thatcasestatementistransitioningto.Thisiserrorprone(butitdoesworkifcodedcorrectly).
?Again,foreaseofscanninganddebug,theallofthestateassignmentshavebeenplacedinasingle
column,asopposedtofindingstateassignmentsfollowingthecontouroftheRTLcode.
?Alloutputswillberegistered(unlesstheoutputsareplacedintoaseparatecombinationalalwaysblock
orassignedusingcontinuousassignments).NoasynchronousMealyoutputscanbegeneratedfroma
singlesynchronousalwaysblock.
?Note:somemisinformedengineersfearthatmakingmultipleassignmentstothesamevariable,inthe
samealwaysblock,usingnonblockingassignments,isundefinedandcancauseraceconditions.Thisis
nottrue.Makingmultiplenonblockingassignmentstothesamevariableinthesamealwaysblockis
definedbytheVerilogStandard.Thelastnonblockingassignmenttothesamevariablewins!(See
reference[5]fordetails).
6.210-statesimpleFSMdesign-onealwaysblocks
Example5isthefsm_cc7designimplementedwithonealwaysblocks.Usingonealwaysblocks,the
fsm_cc7designrequires79linesofcode(codingrequirementsarecomparedinalatersection).
modulefsm_cc7_1
(outputregy1,
inputjmp,go,clk,rst_n);
parameterS0=4''b0000,
S1=4''b0001,
S2=4''b0010,
S3=4''b0011,
S4=4''b0100,
S5=4''b0101,
S6=4''b0110,
S7=4''b0111,
S8=4''b1000,
S9=4''b1001;
reg[3:0]state;
always@(posedgeclkornegedgerst_n)
if(!rst_n)begin
state<=S0;
y1<=1''b0;
end
elsebegin
y1<=1''b0;
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state<=4''bx;
case(state)
S0:if(!go)state<=S0;
elseif(jmp)begin
y1<=1''b1;
state<=S3;
end
elsestate<=S1;
S1:if(jmp)begin
y1<=1''b1;
state<=S3;
end
elsestate<=S2;
S2:begin
y1<=1''b1;
state<=S3;
end
S3:if(jmp)begin
y1<=1''b1;
state<=S3;
end
elsestate<=S4;
S4:if(jmp)begin
y1<=1''b1;
state<=S3;
end
elsestate<=S5;
S5:if(jmp)begin
y1<=1''b1;
state<=S3;
end
elsestate<=S6;
S6:if(jmp)begin
y1<=1''b1;
state<=S3;
end
elsestate<=S7;
S7:if(jmp)begin
y1<=1''b1;
state<=S3;
end
elsestate<=S8;
S8:if(jmp)begin
y1<=1''b1;
state<=S3;
end
elsestate<=S9;
S9:if(jmp)begin
y1<=1''b1;
state<=S3;
end
elsestate<=S0;
endcase
end
endmodule
Example5-fsm_cc7design-onealwaysblockstyle-79linesofcode
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6.310-statemoderatelycomplexFSMdesign-onealwaysblocks
Example6isthefsm_cc8designimplementedwithonealwaysblocks.Usingonealwaysblocks,the
fsm_cc8designrequires146linesofcode(codingrequirementsarecomparedinalatersection).
modulefsm_cc8_1
(outputregy1,y2,y3,
inputjmp,go,sk0,sk1,clk,rst_n);
parameterS0=4''b0000,
S1=4''b0001,
S2=4''b0010,
S3=4''b0011,
S4=4''b0100,
S5=4''b0101,
S6=4''b0110,
S7=4''b0111,
S8=4''b1000,
S9=4''b1001;
reg[3:0]state;
always@(posedgeclkornegedgerst_n)
if(!rst_n)begin
state<=S0;
y1<=1''b0;
y2<=1''b0;
y3<=1''b0;
end
elsebegin
state<=4''bx;
y1<=1''b0;
y2<=1''b0;
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y3<=1''b0;
case(state)
S0:if(!go)state<=S0;
elseif(jmp)begin
state<=S3;
y1<=1''b1;
y2<=1''b1;
end
elsebegin
state<=S1;
y2<=1''b1;
end
S1:if(jmp)begin
state<=S3;
y1<=1''b1;
y2<=1''b1;
end
elsestate<=S2;
S2:if(jmp)begin
state<=S3;
y1<=1''b1;
y2<=1''b1;
end
elsebegin
state<=S9;
y1<=1''b1;
y2<=1''b1;
y3<=1''b1;
end
S3:if(jmp)begin
state<=S3;
y1<=1''b1;
y2<=1''b1;
end
elsestate<=S4;
S4:if(jmp)begin
state<=S3;
y1<=1''b1;
y2<=1''b1;
end
elseif(sk0&&!jmp)begin
state<=S6;
y1<=1''b1;
y2<=1''b1;
y3<=1''b1;
end
elsestate<=S5;
S5:if(jmp)begin
state<=S3;
y1<=1''b1;
y2<=1''b1;
end
elseif(!sk1&&!sk0&&!jmp)begin
state<=S6;
y1<=1''b1;
y2<=1''b1;
y3<=1''b1;
end
elseif(!sk1&&sk0&&!jmp)begin
state<=S7;
y3<=1''b1;
end
elseif(sk1&&!sk0&&!jmp)begin
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state<=S8;
y2<=1''b1;
y3<=1''b1;
end
elsebegin
state<=S9;
y1<=1''b1;
y2<=1''b1;
y3<=1''b1;
end
S6:if(jmp)begin
state<=S3;
y1<=1''b1;
y2<=1''b1;
end
elseif(go&&!jmp)begin
state<=S7;
y3<=1''b1;
end
elsebegin
state<=S6;
y1<=1''b1;
y2<=1''b1;
y3<=1''b1;
end
S7:if(jmp)begin
state<=S3;
y1<=1''b1;
y2<=1''b1;
end
elsebegin
state<=S8;
y2<=1''b1;
y3<=1''b1;
end
S8:if(jmp)begin
state<=S3;
y1<=1''b1;
y2<=1''b1;
end
elsebegin
state<=S9;
y1<=1''b1;
y2<=1''b1;
y3<=1''b1;
end
S9:if(jmp)begin
state<=S3;
y1<=1''b1;
y2<=1''b1;
end
elsestate<=S0;
endcase
end
endmodule
Example6-fsm_cc8design-onealwaysblockstyle-146linesofcode
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7.OnehotFSMCodingStyle(GoodStyle)
Efficient(smallandfast)onehotstatemachinescanbecodedusinganinversecasestatement;acase
statementwhereeachcaseitemisanexpressionthatevaluatestotrueorfalse.
Reconsiderthefsm_cc4designshowninsection5.Eightcodingmodificationsmustbemadetothetwo
alwaysblockcodingstyleofsection5toimplementtheefficientonehotFSMcodingstyle.
Thekeytounderstandingthechangesistorealizethattheparametersnolongerrepresentstate
encodings,theynowrepresentanindexintothestatevector,andcomparisonsandassignmentsarenow
beingmadetosinglebitsineitherthestateornext-statevectors.Noticehowthecasestatementisnow
doinga1-bitcomparisonagainsttheonehotstatebit.
modulefsm_cc4_fp
(outputreggnt,
inputdly,done,req,clk,rst_n);
parameter[3:0]IDLE=0,
BBUSY=1,
BWAIT=2,
BFREE=3;
reg[3:0]state,next;
always@(posedgeclkornegedgerst_n)
if(!rst_n)begin
state<=4''b0;
state[IDLE]<=1''b1;
end
elsestate<=next;
always@(stateordlyordoneorreq)begin
next=4''b0;
gnt=1''b0;
case(1''b1)//ambitfull_caseparallel_case
state[IDLE]:if(req)next[BBUSY]=1''b1;
elsenext[IDLE]=1''b1;
state[BBUSY]:begin
gnt=1''b1;
if(!done)next[BBUSY]=1''b1;
elseif(dly)next[BWAIT]=1''b1;
elsenext[BFREE]=1''b1;
end
state[BWAIT]:begin
gnt=1''b1;
if(!dly)next[BFREE]=1''b1;
elsenext[BWAIT]=1''b1;
end
state[BFREE]:begin
if(req)next[BBUSY]=1''b1;
elsenext[IDLE]=1''b1;
end
endcase
end
endmodule
Example7-fsm_cc4design-case(1''b1)onehotstyle-42linesofcode
Indexintothestateregister,
notstateencodings
Onehotrequireslarger
declarations
Resetmodification
Mustmakeall-0''sassignment
Add"full"&"parallel"case
case(1''b1)
state[current_state]
caseitems
Onlyupdatethe
next[next_state]bit
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7.110-statesimpleFSMdesign-case(1''b1)onehotcodingstyle
Example8isthefsm_cc7designimplementedwiththecase(1''b1)onehotcodingstyle.Usingthisstyle,
thefsm_cc7designrequires53linesofcode(codingrequirementsarecomparedinalatersection).
modulefsm_cc7_onehot_fp
(outputregy1,
inputjmp,go,clk,rst_n);
parameterS0=0,
S1=1,
S2=2,
S3=3,
S4=4,
S5=5,
S6=6,
S7=7,
S8=8,
S9=9;
reg[9:0]state,next;
always@(posedgeclkornegedgerst_n)
if(!rst_n)begin
state<=0;
state[S0]<=1''b1;
end
elsestate<=next;
always@(stateorgoorjmp)begin
next=10''b0;
y1=1''b0;
case(1''b1)//ambitfull_caseparallel_case
state[S0]:if(!go)next[S0]=1''b1;
elseif(jmp)next[S3]=1''b1;
elsenext[S1]=1''b1;
state[S1]:if(jmp)next[S3]=1''b1;
elsenext[S2]=1''b1;
state[S2]:next[S3]=1''b1;
state[S3]:beginy1=1''b1;
if(jmp)next[S3]=1''b1;
elsenext[S4]=1''b1;
end
state[S4]:if(jmp)next[S3]=1''b1;
elsenext[S5]=1''b1;
state[S5]:if(jmp)next[S3]=1''b1;
elsenext[S6]=1''b1;
state[S6]:if(jmp)next[S3]=1''b1;
elsenext[S7]=1''b1;
state[S7]:if(jmp)next[S3]=1''b1;
elsenext[S8]=1''b1;
state[S8]:if(jmp)next[S3]=1''b1;
elsenext[S9]=1''b1;
state[S9]:if(jmp)next[S3]=1''b1;
elsenext[S0]=1''b1;
endcase
end
endmodule
Example8-fsm_cc7design-case(1''b1)onehotstyle-53linesofcode
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7.210-statemoderatelycomplexFSMdesign-case(1''b1)onehotcodingstyle
Example9isthefsm_cc8designimplementedwiththecase(1''b1)onehotcodingstyle.Usingthisstyle,
thefsm_cc8designrequires86linesofcode(codingrequirementsarecomparedinalatersection).
modulefsm_cc8_onehot_fp
(outputregy1,y2,y3,
inputjmp,go,sk0,sk1,clk,rst_n);
parameterS0=0,
S1=1,
S2=2,
S3=3,
S4=4,
S5=5,
S6=6,
S7=7,
S8=8,
S9=9;
reg[9:0]state,next;
always@(posedgeclkornegedgerst_n)
if(!rst_n)begin
state<=0;
state[S0]<=1''b1;
end
elsestate<=next;
always@(stateorjmporgoorsk0orsk1)begin
next=0;
case(1''b1)//ambitfull_caseparallel_case
state[S0]:if(!go)next[S0]=1''b1;
elseif(jmp)next[S3]=1''b1;
elsenext[S1]=1''b1;
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state[S1]:if(jmp)next[S3]=1''b1;
elsenext[S2]=1''b1;
state[S2]:if(jmp)next[S3]=1''b1;
elsenext[S9]=1''b1;
state[S3]:if(jmp)next[S3]=1''b1;
elsenext[S4]=1''b1;
state[S4]:if(jmp)next[S3]=1''b1;
elseif(sk0&&!jmp)next[S6]=1''b1;
elsenext[S5]=1''b1;
state[S5]:if(jmp)next[S3]=1''b1;
elseif(!sk1&&!sk0&&!jmp)next[S6]=1''b1;
elseif(!sk1&&sk0&&!jmp)next[S7]=1''b1;
elseif(sk1&&!sk0&&!jmp)next[S8]=1''b1;
elsenext[S9]=1''b1;
state[S6]:if(jmp)next[S3]=1''b1;
elseif(go&&!jmp)next[S7]=1''b1;
elsenext[S6]=1''b1;
state[S7]:if(jmp)next[S3]=1''b1;
elsenext[S8]=1''b1;
state[S8]:if(jmp)next[S3]=1''b1;
elsenext[S9]=1''b1;
state[S9]:if(jmp)next[S3]=1''b1;
elsenext[S0]=1''b1;
endcase
end
always@(posedgeclkornegedgerst_n)
if(!rst_n)begin
y1<=1''b0;
y2<=1''b0;
y3<=1''b0;
end
elsebegin
y1<=1''b0;
y2<=1''b0;
y3<=1''b0;
case(1''b1)
next[S0],next[S2],next[S4],next[S5]:;//defaultoutputs
next[S7]:y3<=1''b1;
next[S1]:y2<=1''b1;
next[S3]:begin
y1<=1''b1;
y2<=1''b1;
end
next[S8]:begin
y2<=1''b1;
y3<=1''b1;
end
next[S6],next[S9]:begin
y1<=1''b1;
y2<=1''b1;
y3<=1''b1;
end
endcase
end
endmodule
Example9-fsm_cc8design-case(1''b1)onehotstyle-86linesofcode
ThisistheonlycodingstylewhereIrecommendusingfull_caseandparallel_casestatements.Theparallel
casestatementtellsthesynthesistooltonotbuildapriorityencodereventhoughintheory,morethanone
ofthestatebitscouldbeset(asengineers,weknowthatthisisaonehotFSMandthatonlyonebitcanbe
setsonopriorityencoderisrequired).Thevalueofthefull_casestatementisstillinquestion.
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8.RegisteredFSMOutputs(GoodStyle)
RegisteringtheoutputsofanFSMdesigninsuresthattheoutputsareglitch-freeandfrequentlyimproves
synthesisresultsbystandardizingtheoutputandinputdelayconstraintsofsynthesizedmodules(see
reference[1]formoreinformation).
FSMoutputsareeasilyregisteredbyaddingathirdalwayssequentialblocktoanFSMmodulewhere
outputassignmentsaregeneratedinacasestatementwithcaseitemscorrespondingtothenextstatethat
willbeactivewhentheoutputisclocked.
modulefsm_cc4_2r
(outputreggnt,
inputdly,done,req,clk,rst_n);
parameter[1:0]IDLE=2''b00,
BBUSY=2''b01,
BWAIT=2''b10,
BFREE=2''b11;
reg[1:0]state,next;
always@(posedgeclkornegedgerst_n)
if(!rst_n)state<=IDLE;
elsestate<=next;
always@(stateordlyordoneorreq)begin
next=2''bx;
case(state)
IDLE:if(req)next=BBUSY;
elsenext=IDLE;
BBUSY:if(!done)next=BBUSY;
elseif(dly)next=BWAIT;
elsenext=BFREE;
BWAIT:if(!dly)next=BFREE;
elsenext=BWAIT;
BFREE:if(req)next=BBUSY;
elsenext=IDLE;
endcase
end
always@(posedgeclkornegedgerst_n)
if(!rst_n)gnt<=1''b0;
elsebegin
gnt<=1''b0;
case(next)
IDLE,BFREE:;//defaultoutputs
BBUSY,BWAIT:gnt<=1''b1;
endcase
end
endmodule
Example10-fsm_cc4design-threealwaysblocksw/registeredoutputs-40linesofcode
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8.110-statesimpleFSMdesign-threealwaysblocks-registeredoutputs
Example11isthefsm_cc7designwithregisteredoutputsimplementedwiththreealwaysblocks.Using
threealwaysblocks,thefsm_cc7designrequires60linesofcode(codingrequirementsarecomparedina
latersection).
modulefsm_cc7_3r
(outputregy1,
inputjmp,go,clk,rst_n);
parameterS0=4''b0000,
S1=4''b0001,
S2=4''b0010,
S3=4''b0011,
S4=4''b0100,
S5=4''b0101,
S6=4''b0110,
S7=4''b0111,
S8=4''b1000,
S9=4''b1001;
reg[3:0]state,next;
always@(posedgeclkornegedgerst_n)
if(!rst_n)state<=S0;
elsestate<=next;
always@(stateorgoorjmp)begin
next=4''bx;
y1=1''b0;
case(state)
S0:if(!go)next=S0;
elseif(jmp)next=S3;
elsenext=S1;
S1:if(jmp)next=S3;
elsenext=S2;
S2:next=S3;
S3:beginy1=1''b1;
if(jmp)next=S3;
elsenext=S4;
end
S4:if(jmp)next=S3;
elsenext=S5;
S5:if(jmp)next=S3;
elsenext=S6;
S6:if(jmp)next=S3;
elsenext=S7;
S7:if(jmp)next=S3;
elsenext=S8;
S8:if(jmp)next=S3;
elsenext=S9;
S9:if(jmp)next=S3;
elsenext=S0;
endcase
end
always@(posedgeclkornegedgerst_n)
if(!rst_n)y1<=1''b0;
elsebegin
y1<=1''b0;
case(state)
S0,S1,S2,S4,S5,S6,S7,S8,S9:;//default
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S3:y1<=1''b1;
endcase
end
endmodule
Example11-fsm_cc7design-threealwaysblocksw/registeredoutputs-60linesofcode
8.210-statemoderatelycomplexFSMdesign-threealwaysblocks-registered
outputs
Example12isthefsm_cc8designwithregisteredoutputsimplementedwiththreealwaysblocks.Using
threealwaysblocks,thefsm_cc8designrequires83linesofcode(codingrequirementsarecomparedina
latersection).
modulefsm_cc8_3r
(outputregy1,y2,y3,
inputjmp,go,sk0,sk1,clk,rst_n);
parameterS0=4''b0000,
S1=4''b0001,
S2=4''b0010,
S3=4''b0011,
S4=4''b0100,
S5=4''b0101,
S6=4''b0110,
S7=4''b0111,
S8=4''b1000,
S9=4''b1001;
reg[3:0]state,next;
always@(posedgeclkornegedgerst_n)
if(!rst_n)state<=S0;
elsestate<=next;
always@(stateorjmporgoorsk0orsk1)begin
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next=4''bx;
case(state)
S0:if(!go)next=S0;
elseif(jmp)next=S3;
elsenext=S1;
S1:if(jmp)next=S3;
elsenext=S2;
S2:if(jmp)next=S3;
elsenext=S9;
S3:if(jmp)next=S3;
elsenext=S4;
S4:if(jmp)next=S3;
elseif(sk0&&!jmp)next=S6;
elsenext=S5;
S5:if(jmp)next=S3;
elseif(!sk1&&!sk0&&!jmp)next=S6;
elseif(!sk1&&sk0&&!jmp)next=S7;
elseif(sk1&&!sk0&&!jmp)next=S8;
elsenext=S9;
S6:if(jmp)next=S3;
elseif(go&&!jmp)next=S7;
elsenext=S6;
S7:if(jmp)next=S3;
elsenext=S8;
S8:if(jmp)next=S3;
elsenext=S9;
S9:if(jmp)next=S3;
elsenext=S0;
endcase
end
always@(posedgeclkornegedgerst_n)
if(!rst_n)begin
y1<=1''b0;
y2<=1''b0;
y3<=1''b0;
end
elsebegin
y1<=1''b0;
y2<=1''b0;
y3<=1''b0;
case(next)
S0,S2,S4,S5:;//defaultoutputs
S7:y3<=1''b1;
S1:y2<=1''b1;
S3:begin
y1<=1''b1;
y2<=1''b1;
end
S8:begin
y2<=1''b1;
y3<=1''b1;
end
S6,S9:begin
y1<=1''b1;
y2<=1''b1;
y3<=1''b1;
end
endcase
end
endmodule
Example12-fsm_cc8design-threealwaysblocksw/registeredoutputs-83linesofcode
InternationalCadenceUsersGroup2002FundamentalsofEfficientSynthesizableFSM
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9.ComparingRTLCodingEfforts
Intheprecedingsections,threedifferentFSMdesignswerecodedfourdifferentways:(1)twoalways
blockcodingstyle,(2)onealwaysblockcodingstyle,(3)onehot,twoalwaysblockcodingstyle,and(4)
threealwaysblockcodingstylewithregisteredoutputs.
Twoalwaysblock
codingstyle
Onealwaysblock
codingstyle
(12%-83%larger)
Onehot,two
alwaysblock
codingstyle
Threealways
blockcodingstyle
w/registered
outputs
fsm_cc4
(4states,simple)37linesofcode
47linesofcode
(12%-27%larger)42linesofcode40linesofcode
fsm_cc7
(10states,simple)50linesofcode
79linesofcode
(32%-58%larger)53linesofcode60linesofcode
fsm_cc8
(10states,moderate
complexity)
80linesofcode146linesofcode(70%-83%larger)86linesofcode83linesofcode
Table1-LinesofRTLcoderequiredfordifferentFSMcodingstyles
FromTable1,weseethattheonealwaysblockFSMcodingstyleistheleastefficientcodingstylewith
respecttotheamountofRTLcoderequiredtorenderanequivalentdesign.Infact,themoreoutputsthatan
FSMdesignhasandthemoretransitionarcsintheFSMstatediagram,thefastertheonealwaysblock
codingstyleincreasesinsizeovercomparableFSMcodingstyles.
Ifyouareacontractororarepaidbytheline-of-code,clearly,theonealwaysblockFSMcodingstyle
shouldbeyourpreferredstyle.Ifyouaretryingtocompleteaprojectontimeandcodethedesignina
concisemanner,theonealwaysblockcodingstyleshouldbeavoided.
10.SynthesisResults
Synthesisresultswerenotcompletebythetimethepaperwassubmittedforpublication.
11.RunningCadenceBuildGates
ac_shell(forcommand-linemode)
ac_shell-gui&(forGUImodewithprocessrunninginbackground)
12.Verilog-2001Enhancements
Asofthiswriting,theCadenceVerilogsimulatorsdonotsupportmany(ifany)ofthenewVerilog-2001
enhancements.AlloftheprecedingexampleswerecodedwithVerilog-2001enhancedandconciseANSI-
stylemoduleheaders.Inreality,tomakethedesignsworkwiththeCadenceVerilogsimulators,Ihadto
alsocodeVerilog-1995stylemoduleheadersandselecttheappropriateheaderusingmacrodefinitions.To
easethetask,Ihavecreatedtwoaliasesfor1995-styleVerilogsimulations.
aliasncverilog95"ncverilog+define+V95"
aliasverilog95"verilog+define+V95"
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12.1ANSI-Styleportdeclarations
ANSI-styleportdeclarationsareaniceenhancementtoVerilog-2001buttheyarenotyetsupportedby
version3.4ofNC-VerilogorVerilog-XL,buttheyarereportedtoworkwithBuildGates.This
enhancementpermitsmoduleheaderstobedeclaredinamuchmoreconcisemannerovertraditional
Verilog-1995codingrequirements.
Verilog-1995requiredeachmoduleportbedeclaredtwoorthreetimes.Verilog-1995requiredthat(1)the
moduleportsbelistedinthemoduleheader,(2)themoduleportdirectionsbedeclared,and(3)forreg-
variableoutputports,theportdatatypewasalsorequired.
Verilog-2001combinedallofthisinformationintosinglemoduleportdeclarations,significantlyreducing
theverbosityandredundancyofVerilogmoduleheaders.OfthemajorVerilogvendors,onlytheCadence
VerilogsimulatorsdonotsupportthisVerilog-2001feature.Thismeansthatuserswhowanttotake
advantageofthisfeatureandwhousesimulatorsfrommultiplevendors,includingCadence,mustcode
bothstylesofmoduleheadersusing`ifdefstatementstoselecttheappropriatemoduleheaderstyle.
Ipreferthefollowingcodingstyletosupportretro-styleVerilogsimulators:
`ifdefV95
//Verilog-1995old-style,verbosemoduleheaders
`else
//Verilog-2001new-style,efficientmoduleheaders
`endif
Thefollowingexampleisfromtheactualfsm_cc4_1.vfileusedtotestonealwaysblockFSMcoding
stylesinthispaper.
`ifdefV95
modulefsm_cc4_1(gnt,dly,done,req,clk,rst_n);
outputgnt;
inputdly,done,req;
inputclk,rst_n;
reggnt;
`else
modulefsm_cc4_1
(outputreggnt,
inputdly,done,req,clk,rst_n);
`endif
Itshouldbenotedthatthisisaneasyenhancementtoimplement,significantlyimprovesthecoding
efficiencyofmoduleheadersandthatsomemajorVerilogvendorshavesupportedthisenhancedcoding
styleformorethanayearatthetimethispaperwaswritten.TheauthorstronglyencouragesCadence
simulatordeveloperstoquicklyadoptthisVerilog-2001enhancementtoeasetheVerilogcodingburdenfor
Cadencetoolusers.
12.2@Combinationalsensitivitylist
Verilog-2001addedthemuch-heralded@combinationalsensitivitylisttoken.Althoughthe
combinationalsensitivylistcouldbewrittenusinganyofthefollowingstyles:
always@
always@()
always@()
always@()
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oranyothercombinationofthecharacters@()withorwithoutwhitespace,theauthorprefersthefirst
andmostabbreviatedstyle.Totheauthor,"always@"clearlydenotesthatacombinationalblockoflogic
follows.
TheVerilog-2001"always@"codingstylehasanumberofimportantadvantagesoverthemore
cumbersomeVerilog-1995combinationalsensitivitylistcodingstyle:
?Reducescodingerrors-thecodeinformsthesimulatorthattheintendedimplementationis
combinationallogic,sothesimulatorwillautomaticallyaddandremovesignalsfromthesensitivity
listasRTLcodeisaddedordeletedfromthecombinationalalwaysblock.TheRTLcoderisnolonger
burdenedwithmanuallyinsuringthatallofthenecessarysignalsarepresentinthesensitivitylist.This
willreducecodingerrorsthatdonotshowupuntilasynthesistoolorlintingtoolreportserrorsinthe
sensitivitylist.Thebasicintentofthisenhancementistoinformthesimulator,"ifthesynthesistool
wantsthesignals,sodowe!"
?Abbreviatedsyntax-largecombinationalblocksoftenmeantmultiplelinesofredundantsignal
naminginasensitivitylist.Theredundancyservednoappreciablepurposeanduserswillgladlyadopt
themoreconciseandabbreviated@syntax.
?Clearintent-analways@proceduralblockinformsthecode-reviewerthatthisblockisintendedto
behavelike,andsynthesizeto,combinationallogic.
13.SystemVerilogEnhancements
InJuneof2002,AccellerareleasedtheSystemVerilog3.0languagespecification,asupersetofVerilog-
2001withmanyniceenhancementsformodeling,synthesisandverification.Thebasisforthe
SystemVeriloglanguagecomesfromadonationbyCoDesignAutomationofsignificantportionsoftheir
Superloglanguage.
KeyfunctionalitythathasbeenaddedtotheAccelleraSystemVerilog3.0SpecificationtosupportFSM
designincludes:
Enumeratedtypes-Whydoengineerswanttouseenumeratedtypes?(1)Enumeratedtypespermit
abstractstatedeclarationwithoutdefiningthestateencodings,and(2)enumeratedtypescantypicallybe
easilydisplayedinawaveformviewerpermittingfasterdesigndebug.Enumeratedtypesallowabstract
statedefinitionswithoutrequiredstateencodingassignments.Usersalsowantedtheabilitytoassignstate
encodingstocontrolimplementationdetailssuchasoutputencodedFSMdesignswithsimpleregistered
outputs.
OneshortcomingoftraditionalenumeratedtypeswastheinabilitytomakeX-stateassignments.As
discussedearlierinthispaper,X-stateassignmentsareimportanttosimulationdebugandsynthesis
optimization.SystemVerilogenumeratedtypeswillpermitdatatypedeclaration,makingitpossibleto
declareenumeratedtypeswithanall-X''sdefinitions.
OtherSystemVerilogproposalsunderconsiderationforFSMenhancementinclude:
Differentenumeratedstyles-theabilitytodeclaredifferentenumeratedstyles,suchasenum_onehot,to
makeexperimentationwithdifferentencodingstyleseasiertodo.Currently,whenchangingfromabinary
encodingtoanefficientonehotencodingstyle,8differentcodechangesmustbemadeintheFSMmodule.
Wouldn''titbeniceifthesyntaxpermittedeasierhandlingofFSMstyleswithoutmanualintervention.
Transitionstatementand->>nextstatetransitionoperator-
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TheseenhancementswereremovedfromtheSystemVerilog3.0Standardonlybecausetheirdefinitionwas
notfullyelaboratedandunderstood.Somepeopleliketheideaofanext-statetransitionoperatorthat
closelycorrespondstothetransitionarcsthatareshownonanFSMstatediagram.
Theinfinitelyabusable"goto"statement-Concernabouta"goto"statementthatcould"causespaghetti-
code"couldbeavoidedbylimitingagoto-transitiontoalabelwithinthesameproceduralblock.Implicit
FSMcodingstylesaremuchcleanerwithagotostatement.Agotostatementcombinedwithacarefully
crafteddisablestatementmakesresethandlingeasiertodo.Agotostatementalleviatestheproblemof
multipletransitionarcswithinatraditionalimplicitFSMdesign.Gotoisjustaproposalandmaynotpass.
14.Conclusions
TherearemanywaystocodeFSMdesigns.TherearemanyinefficientwaystocodeFSMdesigns!
Useparameterstodefinestateencodings.Parametersareconstantsthatarelocaltoamodule.After
definingthestateencodingsatthetopoftheFSMmodule,neverusethestateencodingsagainintheRTL
code.Thismakesitpossibletoeasilychangethestateencodingsinjustoneplace,theparameter
definitions,withouthavingtotouchtherestoftheFSMRTLcode.Thismakesstate-encoding-
experimentationeasytodo.
UseatwoalwaysblockcodingstyletocodeFSMdesignswithcombinationaloutputs.Thisstyleis
efficientandeasytocodeandcanalsoeasilyhandleMealyFSMdesigns.
UseathreealwaysblockcodingstyletocodeFSMdesignswithregisteredoutputs.Thisstyleisefficient
andeasytocode.Note,anotherrecommendedcodingstyleforFSMdesignswithregisteredoutputsisthe
"outputencoded"FSMcodingstyle(seereference[1]formoreinformationonthiscodingstyle).
AvoidtheonealwaysblockFSMcodingstyle.Itisgenerallymoreverbosethananequivalenttwoalways
blockcodingstyle,outputassignmentsaremoreerrorpronetocodingmistakesandonecannotcode
asynchronousMealyoutputswithoutmakingtheoutputassignmentswithseparatecontinuousassign
statements.
15.Acknowledgements
IwouldliketoespeciallythankbothRichOwenandNasirJunejoofCadencefortheirassistanceandtips
enablingtheuseoftheBuildGatessynthesistool.Theirinputhelpedmetoachieveveryfavorableresultsin
ashortperiodoftime.
16.References
[1]CliffordE.Cummings,"CodingAndScriptingTechniquesForFSMDesignsWithSynthesis-Optimized,Glitch-
FreeOutputs,"SNUG''2000Boston(SynopsysUsersGroupBoston,MA,2000)Proceedings,September2000.
(Alsoavailableonlineatwww.sunburst-design.com/papers)
[2]CliffordE.Cummings,''"full_caseparallel_case",theEvilTwinsofVerilogSynthesis,''SNUG''99Boston
(SynopsysUsersGroupBoston,MA,1999)Proceedings,October1999.(Alsoavailableonlineatwww.sunburst-
design.com/papers)
[3]CliffordE.Cummings,"NewVerilog-2001TechniquesforCreatingParameterizedModels(orDownWith
`defineandDeathofadefparam!),"InternationalHDLConference2002Proceedings,pp.17-24,March2002.
(Alsoavailableonlineatwww.sunburst-design.com/papers)
[4]CliffordE.Cummings,"NonblockingAssignmentsinVerilogSynthesis,CodingStylesThatKill!,"SNUG''2000
Boston(SynopsysUsersGroupSanJose,CA,2000)Proceedings,March2000.(Alsoavailableonlineat
www.sunburst-design.com/papers)
InternationalCadenceUsersGroup2002FundamentalsofEfficientSynthesizableFSM
Rev1.1DesignusingNC-VerilogandBuildGates
27
[5]IEEEStandardHardwareDescriptionLanguageBasedontheVerilogHardwareDescriptionLanguage,IEEE
ComputerSociety,IEEEStd1364-1995,pg.47,section5.4.1-Determinism.
[6]NasirJunejo,personalcommunication
[7]RichOwen,personalcommunication
[8]TheProgrammableLogicDataBook,Xilinx,1994,pg.8-171
[9]WilliamI.Fletcher,AnEngineeringApproachToDigitalDesign,NewJersey,Prentice-Hall,1980
[10]ZviKohavi,SwitchingAndFiniteAutomotaTheory,SecondEdition,NewYork,McGraw-HillBookCompany,
1978
Author&ContactInformation
CliffCummings,PresidentofSunburstDesign,Inc.,isanindependentEDAconsultantandtrainerwith20
yearsofASIC,FPGAandsystemdesignexperienceandtenyearsofVerilog,synthesisandmethodology
trainingexperience.
Mr.Cummings,amemberoftheIEEE1364VerilogStandardsGroup(VSG)since1994,chairedtheVSG
BehavioralTaskForce,whichwaschargedwithproposingenhancementstotheVeriloglanguage.Mr.
CummingsisalsoamemberoftheIEEEVerilogSynthesisInteroperabilityWorkingGroupandthe
AccelleraSystemVerilogStandardizationGroup.
Mr.CummingsholdsaBSEEfromBrighamYoungUniversityandanMSEEfromOregonState
University.
E-mailAddress:cliffc@sunburst-design.com
Anupdatedversionofthispapercanbedownloadedfromthewebsite:www.sunburst-design.com/papers
(DataaccurateasofJuly22nd,2002)
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