1 MATLAB设计与仿真设计一个7抽头FIR低通滤波器。代码如下，仿真结果如图1和图2所示。 close all; clc,clear; b = fir1(6,0.1,'low'); [h,w] = freqz(b,1,'whole',512); %plot(w/pi,20*log10(abs(h))) plot(w/pi,abs(h)) ax = gca; ax.YLim = [-0.2 1.2]; ax.XTick = 0:.5:2; xlabel('Normalized Frequency (\times\pi rad/sample)') ylabel('Magnitude')
f1 = 40; f2 = 400; fs=1000; t=0:(1/fs):(1/fs)*100;
x = sin(2*pi*f1*t)+sin(2*pi*f2*t); b = b*2; y = filter(b,1,x); figure; subplot(2,1,1); plot(t,x); title('Original Signal') subplot(2,1,2); plot(t,y); title('Lowpass Filtered Signal') %y=conv(b,x); %figure %plot(t,y(1:101));
图 1 滤波器幅频特性
图 2 滤波器MATLAB仿真 2. Verilog HDL设计与仿真本文中滤波器采用输入广播、结果移动、权重保持的方式[1]。图3以3抽头滤波器为例说明了其原理。图4为该3抽头滤波器的电路实现原理图。
图 3 滤波器基本原理
图 4 滤波器的电路实现 本文中的滤波器由7个处理单元构成，由Vivado综合出的RLT级视图如图5和图6所示。
图 5 滤波器RTL级视图
图 6 处理单元RTL级视图 滤波器代码如下。 `module filter ( input clk,rst, input signed [31:0] original, output signed [31:0] filtered
); localparam w0=4,w1=18,w2=47,w3=62,w4=47,w5=18,w6=4; wire signed [31:0] right[7:0]; wire signed [31:0] y_out[7:0]; wire signed [31:0] w[6:0];
assign w[00] = w0; assign w[01] = w1; assign w[02] = w2; assign w[03] = w3; assign w[04] = w4; assign w[05] = w5; assign w[06] = w6;
assign right[0]=original; assign filtered=y_out[0]; assign y_out[7]=0;
genvar i; generate for (i=0; i<=6; i=i+1) begin: pe process_element pe ( .clk(clk), .rst(reset), .w(w[i]), .x(right[i]), .d(y_out[i+1]), .y(y_out[i]), .r(right[i+1]) ); end endgenerate
endmodule
module process_element ( input clk,rst, input signed [31:0] w,x,d, output signed [31:0] y,r
); wire signed [31:0] w_1,w_2; multiplier u_mult ( .a(w), .b(x), .result(w_1) );
addr u_add ( .a(w_1), .b(w_2), .result(y) );
DFF u_dff ( .clk(clk), .rst(rst), .d(d), .q(w_2) );
assign r=x;
endmodule
module DFF ( input clk,rst, input signed[31:0] d, output reg signed [31:0] q );
always@ (posedge clk, posedge rst) if(rst) q<=0; else q<=d; endmodule
module addr ( input signed [31:0]a,b, output signed[31:0]result ); assign result = a+b;
endmodule
module multiplier ( input signed [31:0]a,b, output signed[31:0]result ); assign result = a*b;
endmodule 滤波器仿真代码如下。 `timescale 1ns/10ps module filter_tb; localparam T=10;//100MHz reg clk,reset; reg [31:0] rom [100:0]; reg [31:0] original; reg [15:0] i;
//generate 100MHz clock initial begin clk=0; forever clk=#(T/2)~clk; end //reset for the first half cycle initial begin reset=1;#(T*1.6) reset=0; end
filter u_filter ( .clk(clk), .rst(reset), .original(original), .filtered() );
always@(posedge clk) i=i+1;
always@* begin original=rom[i]; end
initial begin i=0; $readmemh ("data.txt", rom); #(T*100) $stop;
end
endmodule
滤波器仿真代码代码中的“data.txt”文件由MATLAB脚本生成，代码如下 temp=(x*1000); temp(find(temp<0))=temp(find(temp<0))+2^32; temp=uint32(temp); temp=dec2hex(temp); fid=fopen('data.txt','wt'); fprintf(fid,'%s\n','@00'); for i=1:length(temp) fprintf(fid,'%s\n',temp(i,:) ); end fclose(fid);
仿真结果如图7所示。其中original为原始输入信号，filtered为滤波器输出信号
图 7 滤波器Verilog HDL仿真 参考文献[1]帕里, 弘毅, 国强, 等. VLSI 数字信号处理系统: 设计与实现[M]. 机械工业出版社, 2004. |
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