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IC攻城狮求职宝典 07 2018年IC设计企业 Cadence

 芯文苑eecourse 2018-12-24

IC设计

Cadence 2018设计笔试题

Choice Questions

1. What is the minimum number of flip flops to implement a state machines to detect the bit sequence 11011001?                                               (  C  )

A. 8     B. 3     C. 4     D. 5

解析:

2. What types list below could be used in packed array?                 (  A  )

A. Bit    B. int    C. logic  D. reg

解析:合并数组,既可以当作数组,也可以当作单独的数据。例如,有一个32比特的寄存器,有时候希望把它看成48比特的数据,有时候则希望把它看成单个的无符号数据。

如:bit [3:0] [7:0] barray [3];

3. Divide (1110111)2 by (1001)2                                                                             (  A  )

A. Quotient (1101)2 remainder (10)2

B. Quotient (1101)2 remainder (0)2

C. Quotient (10)2 remainder (0)2

D. Quotient (1101)2 remainder (101)2

解析:小学的时候十进制的除法我们是怎么做的,现在就怎么做。

4. What is the duration of task t?                                    (  C  )

       

A. 10 times units

B. 16 times units

C. 5 times units

D. 7 times units

解析:

5. According to the following truth table with input A,B,C and D, what is an equation for output F ?                                                        (  D  )

  

A

B

C

D

F

0

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

1

1

1

0

1

0

0

1

0

1

0

1

1

0

1

1

0

0

0

1

1

1

0

1

0

0

0

x

1

0

0

1

x

1

0

1

0

x

1

0

1

1

x

1

1

0

0

1

1

1

0

1

1

1

1

1

0

0

1

1

1

1

0

A. BC+B’C’

B. AB’

C. AB’+B’C

D. BC’+B’C

解析:卡诺图化简

6. What input can detect sluck at-1 fault at E ?                          (  B  )

 

 

 

 

 

 

 


A. A=0, B=X, C=0, D=1

B. A=X, B=1, C=0, D=1

C. A=X, B=0, C=0, D=0

D. A=0, B=1, C=1, D=1

 

7. Given the following designWhat are the effective setup and hold times for the following circuit ?                                                          (  C  )

 

A. Tsetup=4ns, Thold = 1ns

B. Tsetup=3ns, Thold = 0ns

C. Tsetup=3ns, Thold = 1ns

D. Tsetup=2ns, Thold = 0ns 

解析:有效建立时间分析:

有效保持时间分析:

 

8. What is the maximum operating frequency of the above circuit ?      (  C  )

A. 250MHz    B. 80MHz    C. 125 MHz    D. 166.7MHz

9. Which equation best describes the maximum clock frequency in a synchronous system ?

                                                               (  D  )

A. Max Freq = 1/( Tprop_delay + Tsu + Thold )

B. Max Freq = 1/( Tprop_delay + Tsu + Tco + Thold)

C. Max Freq = 1/( Tsu + Tco + Thold + Tclock_skew)

D. Max Freq = 1/( Tprop_delay + Tsu + Tco + Tclock_skew)

E. Max Freq = 1/( Tprop_delay + Tsu + Tco + Thold + Tclock_skew)

 

10. Given the following design, What is the setup margin for flop2 ?    (  A  )

 

A. 8.95ns    B. 9.55ns    C. 0.85    D. 7.75ns

解析:Tcycle - Tprop_delay_max - Tsu - Tco_max - Thold + Tclock_skew>0

11. What is the hold margin for flop2 ?                             (  C  )

A. 0.5ns     B. 0.1ns     C. -0.10ns   D. 9.9ns  

  解析:Tprop_delay_min + Tco_min - Tclock_skew - Thold > 0

Write Questions

1. Design a module in Verilog to satisfy the following requirements.

  (1) a clock with the frequency of 100MHz

(2) a 4-bit width signal that sensitive at the clock posedge, constrain this signal to be randomize 16 times in the range from 8 to 15.

 

2. What is logic synthesis ?

解析:

Translate + mapping + optimization

 

3. What is function verification?

功能验证主要目的是验证DUT的逻辑上的功能是否正确。

          模块级功能验证:侧重于单个模块功能的正确性验证。

          block级验证:侧重于模块间的信号交互级联验证

          系统级验证:需要验证如中断,时钟门控,切频,复位

       等等系统级的功能。

目前流行基于UVM的验证方法学搭建验证平台。

 

4. What is formal verification ?

形式验证(等价性验证)用于验证AB是否等价,这里的B是由A转换得到的。这里的AB可以是RTL代码,也可以是门级网表。在进行等价性验证时,A是参考,B称为实现。可以用形式验证来检查综合结果是否正确(将RTL级的设计与门级网表比较)、插扫描链前后的网表是否一致、布局前后网表是否一致、插时钟树前后的网表是否一致、布线前后的网表是否一致。

 

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