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性能、低功耗的多位delta-sigma音频dac ·110分贝信噪比，-80分贝 THD+N ·24位，8至96 kHz采样频率 ·内置耳机驱动程序 无盖期权 ·高信噪比和 共模抑制比 ·i2s/pcm主或从串行数据端口 ·256/384fs、USB 12/24 MHz和其他 非标准音频系统时钟 ·I2C接口 ·7波段全可调均衡器 ·动态范围压缩 ·回放信号反馈 弹出和点击噪声抑制 ·1.8V至3.3V操作 技术支持 151 1247 6010 莫R
The device works either in hardware mode (HW mode) or software mode (I2C mode). The
default is hardware mode. Software mode is enabled by setting bit 2 of configuration register
0x02.
In HW mode, LRCK and SCLK are supplied externally. LRCK and SCLK must be synchronously
derived from the system clock with some specific rates. The device can auto detect MCLK/LRCK
ratio according to Table 1. The device only supports the MCLK/LRCK ratios listed in Table 1. The
SCLK/LRCK ratio is normally 64. 
CLOCK MODES AND SAMPLING FREQUENCIES
In software mode, the device supports standard audio clocks (32Fs, 64F, 128Fs, 256Fs, 384Fs,
512Fs, etc), USB clocks (12/24 MHz), and some common non standard audio clocks (16 MHz, 25
MHz, 26 MHz, etc).
According to the serial audio data sampling frequency (Fs), the device can work in two speed
modes: single speed mode or double speed mode. In single speed mode, Fs normally ranges
from 8 kHz to 48 kHz, and in double speed mode, Fs normally range from 64 kHz to 96 kHz.
The device can work either in master clock mode or slave clock mode. In slave mode, LRCK and
SCLK are supplied externally, and LRCK and SCLK must be synchronously derived from the
system clock with specific rates. In master mode, LRCK and SCLK are derived internally from
device master clock.
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