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Intel公司的Cyclone® 10 LP FPGA是高容量成本敏感型功能的理想的低功耗FPGA器件,针对广泛的通用逻辑应用而设计,与前代相比,其功耗和成本各降低一半.Cyclone® 10 LP FPGA基于功耗优化的 60 nm 工艺制造,所有Cyclone® 10 LP FPGA 工作时仅需要两个内核电源(1.0V和1.2V),简化了配电网络并可节省电路板成本,电路板空间和设计时间.利用Intel® Cyclone® 10 LP FPGA 的灵活性,您可以设计体积更小,成本更低的设备,从而降低系统总成本.器件嵌入的乘法器支持一个单独18x18乘法器或两个独立的9x9乘法器,也可以级联乘法器区块以形成更宽或更深逻辑结构.器件嵌入的存储器区块包括M9K存储器区块列,每个M9K存储器区块提供9Kb存储器,也可以级联存储器区块以形成更宽或更深逻辑结构,同时可配置M9K成RAM,FIFO缓冲器或ROM.主要用在汽车电字,消费电子,测试与测量,医疗电子与计算机和存储以及其智能电能.本文介绍了Cyclone® 10 LP FPGA主要特性,逻辑单元(LE)框图,Intel® Cyclone® 10 LP FPGA评估板主要特性,框图,电路图,材料清单和PCB设计图. The Intel® Cyclone® 10 LP FPGAs are optimized for low cost and low static power,making them ideal for high-volume and cost-sensitive applications. Cyclone 10 LP devices provide a high density sea of programmable gates, on-board resources, and general purpose I/Os. These resources satisfies the requirements ofI/O expansion and chip-to-chip interfacing. The Cyclone 10 LP architecture suits smartand connected end applications across many market segments: · Industrial and automotive · Broadcast, wireline, and wireless · Compute and storage · Government, military, and aerospace · Medical, consumer, and smart energy The free but powerful Quartus® Prime Lite Edition software suite of design tools meetsthe requirements of several classes of users: · Existing FPGA designers · Embedded designers using the FPGA with Nios® II processor · Students and hobbyists who are new to FPGA Advanced users who require access to the full IP Base Suite can subscribe to the Quartus Prime Standard Edition or purchase the license separately. Cyclone® 10 LP FPGA主要特性:   图1. Cyclone® 10 LP FPGA器件LE框图 Embedded Multipliers Each embedded multiplier block in Cyclone 10 LP devices supports one individual 18 × 18-bit multiplier or two individual 9 × 9-bit multipliers. You can cascade the multiplier blocks to form wider or deeper logic structures. You can control the operation of the embedded multiplier blocks using the following options: · Parameterize the relevant IP cores with the Quartus Prime parameter editor · Infer the multipliers directly with VHDL or Verilog HDL Intel and partners offer popular DSP IPs for Cyclone 10 LP devices, including: · Finite impulse response (FIR) · Fast Fourier transform (FFT) · Numerically controlled oscillator (NCO) functions For a streamlined DSP design flow, the DSP Builder tool integrates the Quartus Prime software with MathWorks Simulink and MATLAB design environments. Embedded Memory Blocks The embedded memory structure consists of M9K memory blocks columns. Each M9K memory block of a Cyclone 10 LP device provides 9 Kb of on-chip memory. You can cascade the memory blocks to form wider or deeper logic structures. You can configure the M9K memory blocks as RAM, FIFO buffers, or ROM. Clocking and PLL Cyclone 10 LP devices feature global clock (GCLK) networks, dedicated clock pins, and general purpose PLLs. · Up to 20 GCLK networks that drive throughout the device · Up to 15 dedicated clock pins · Up to four general purpose PLLs with five outputs per PLL The PLLs provide robust clock management and synthesis for the Cyclone 10 LPdevice. You can dynamically reconfigure the PLLs in user mode to change the clockphase or frequency. FPGA General Purpose I/O Cyclone 10 LP devices offer highly configurable GPIOs with these features: · Support for over 20 popular single-ended and differential I/O standards. · Programmable bus hold, pull-up resistors, delay, and drive strength. · Programmable slew-rate control to optimize signal integrity. · Calibrated on-chip series termination (RS OCT) or driver impedance matching (RS)for single-endd I/O standards. · True and emulated LVDS buffers with LVDS SERDES implemented using logicelements in the device core. · Hot socketing support. Configuration Cyclone 10 LP devices use SRAM cells to store configuration data. Configuration datais downloaded to the Cyclone 10 LP device each time the device powers up. You can use EPCS or EPCQ (AS x1) flash configuration devices to store configuration data and configure the Cyclone 10 LP FPGAs. · Cyclone 10 LP devices support 1.5 V, 1.8 V, 2.5 V, 3.0 V, and 3.3 V programming voltages and several configuration schemes. · The single-event upset (SEU) mitigation feature detects cyclic redundancy check (CRC) errors automatically during configuration and optionally during user mode Power Management Cyclone 10 LP devices are built on optimized low-power process: · Available in two core voltage options: 1.2 V and 1.0 V · Hot socketing compliant without needing external components or special designrequirements To accelerate your design schedule, combine Intel Cyclone 10 LP FPGAs with Enpirion® Power Solutions. Intel’s ultra-compact and efficient EnpirionPowerSoCs are ideal formeeting Cyclone 10 LP power requirements. EnpirionPowerSoCs integrate most of the required components to provide you fully-validated and straightforward solutions withup to 96% efficiency. These advantages reduce your power supply design time andallow you to focus on your IP and FPGA designs. Intel® Cyclone® 10 LP FPGA Evaluation Kit The Intel Cyclone 10 LP FPGA Evaluation Kit includes the following components: · The Intel Cyclone 10 LP FPGA evaluation board · USB Y-cable (USB Type-A to mini Type-B) for both on-board Intel FPGA Download Cable II and 5 V power supply from USB port · Intel Cyclone 10 LP FPGA Evaluation Kit collateral, available from the Intel Cyclone 10 LP FPGA pageEvaluation Board with the following components. Intel® Cyclone® 10 LP FPGA评估板主要特性: · Intel Cyclone 10 LP FPGA (10CL025, U256 package) · Enpirion® EN5329QI/EN5339QI - 2A/3A PowerSoC Low Profile Synchronous Buck DC-DC Converter with Integrated Inductor · Enpirion EP5358xUI 600 mA PowerSoC DC-DC Step-Down Converters with Integrated Inductor · Intel XWAY PHY11G Gigabit Ethernet PHY PEF7071 · Intel MAX® 10 FPGA 10M08SAU169C8G (Embedded Intel FPGA Download Cable IIand System Management)Programming and Configuration · Embedded Intel FPGA Download Cable II (JTAG) · Optional JTAG direct through 10-pin header · Active Serial x1 configuration from EPCQ or EPCQ-A flash Memory Devices · 128 megabit (Mb) 8-bit HyperRAM with HBMC (Hyperbus Memory Controller) IP provided by Synaptic Labs · Flash memory: — Rev A1 board: 64 Mb EPCQ — Rev A2 board: 128 Mb EPCQ-A Communication Ports · One Gigabit Ethernet (GbE) RJ-45 port · One 2x20 GPIO Expansion Header · One Arduino UNO R3 type connectors · One 12-pin DigilentPmod compatible connector Clock Circuits · Silicon Labs Si510 50 MHz crystal oscillator · Silicon Labs Si5351 clock generator with programmable frequency GUI Power Supply · USB Y-cable (USB Type-A to mini Type-B) for both on-board Intel FPGA Download Cable II and 5 V power supply from USB port · Supplemental 5 V DC power adapter option (5 V power adapter and cord are not included in the kit)  图2.Intel® Cyclone® 10 LP FPGA评估板外形图  图3.Intel® Cyclone® 10 LP FPGA评估板框图  图4.Intel® Cyclone® 10 LP FPGA评估板电路图(1)  图5.Intel® Cyclone® 10 LP FPGA评估板电路图(2)  图6.Intel® Cyclone® 10 LP FPGA评估板电路图(3)  图7.Intel® Cyclone® 10 LP FPGA评估板电路图(4)  图8.Intel® Cyclone® 10 LP FPGA评估板电路图(5)  图9.Intel® Cyclone® 10 LP FPGA评估板电路图(6)  图10.Intel® Cyclone® 10 LP FPGA评估板电路图(7) 图11.Intel® Cyclone® 10 LP FPGA评估板电路图(8) 图12.Intel® Cyclone® 10 LP FPGA评估板电路图(9) 图13.Intel® Cyclone® 10 LP FPGA评估板电路图(10) 图14.Intel® Cyclone® 10 LP FPGA评估板电路图(11) 图15.Intel® Cyclone® 10 LP FPGA评估板电路图(12) 图16.Intel® Cyclone® 10 LP FPGA评估板电路图(13) 图17.Intel® Cyclone® 10 LP FPGA评估板电路图(14) 图18.Intel® Cyclone® 10 LP FPGA评估板电路图(15) 图19.Intel® Cyclone® 10 LP FPGA评估板电路图(16) 图20.Intel® Cyclone® 10 LP FPGA评估板电路图(17) 图21.Intel® Cyclone® 10 LP FPGA评估板PCB设计图(1) 图22. Intel® Cyclone® 10 LP FPGA评估板PCB设计图(2) Intel® Cyclone® 10 LP FPGA评估板材料清单见: 6XX-44504R-0C 详情请见: https://www./content/dam/altera-www/global/zh_CN/pdfs/literature/hb/cyclone-10/c10lp-51002-ch.pdf 和https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10lp-51001.pdf 以及https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-c10-lp-eval-kit.pdf 与https://www.intel.com/content/dam/altera-www/global/en_US/support/boards-kits/cyclone10/c10lp-eval-a1-sch.PDF |
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