imx6q 默认的设置LVDS分出大于38M的时钟没有问题,但是如果我们使用一些小分辨率的屏,时钟远小于38M时,无论怎么设置,输出的时钟都是38M。 下面是解决的办法; 1 修改imx6qdl-sabresd.dtsi 将 &clks { fsl,ldb-di0-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; fsl,ldb-di1-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; }; 改为 &clks { /* fsl,ldb-di0-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; fsl,ldb-di1-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; */ fsl,ldb-di0-parent = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; fsl,ldb-di1-parent = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; }; 2 修改arch/arm/mach-imx/clk-imx6q.c 在文件开头增加 static int g_ldb_di0_sel,g_ldb_di1_sel; 修改函数 of_assigned_ldb_sels 在函数的结尾添加 g_ldb_di0_sel = *ldb_di0_sel; g_ldb_di1_sel = *ldb_di1_sel; 修改函数imx6q_clocks_init 将 if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) { imx_clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]); imx_clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]); } 修改为 if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) { if(g_ldb_di0_sel==IMX6QDL_CLK_PLL5_VIDEO_DIV) { imx_clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); } else { imx_clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]); } if(g_ldb_di1_sel==IMX6QDL_CLK_PLL5_VIDEO_DIV) { imx_clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); } else { imx_clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]); } } 最后修改DTS文件,设置为自己需要的频率重新编译就可以了。 |
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