Preface本文中英文结合（学习一些专有名词），主要介绍ICC II软件进行后端设计的主要流程，在阅读之前需要对数字IC设计流程有一定的了解。 逻辑综合相关知识请查看：Synopsys逻辑综合及DesignCompiler的使用（想了解逻辑综合的可以看看这个，但内容较多） 数字IC设计整体流程请查看：关于数字IC后端设计的一些基础概念与常识（基础不太扎实的建议先看一遍这个） 有关ICC中用到的一些名词解释请查看：干货满满–数字后端设计及ICC教程整理（建议关注公众号，不是打广告，我也是写这篇blog的时候发现的，真的非常全面）（建议先看我这个博客了解大体流程，然后再看他这个，加深了解；或者看我的博客时还有一些专有名词不太理解啥意思，就可以去他那里找一找解释，效果更佳） 本文类似于笔记形式，整合了网上一些相关资料，参考资料都在最后Reference中列出，尊重知识产权。 ContentBlocks and Design Libraries
read_verilog
open_block save_block
create_lib open_lib save_lib
Objects
get_* help_attributes Attributes of Objects每个objects都有属性，属性有值
report_attributes -application [get_selection]Application Options(App Options)
Finding/Applying Application Options
report_app_options get_app_options
report_app_options time.* (报道Timing相关的app_options)
report_app_options -non_default (一般都是默认值，该命令可知道哪些进行了修改)
set_app_options -name time.remove_clock_reconvergence_pessimism -value true (设定app_options)IC Compiler II GUI
Built-In Script Editor
Design Setup
Overview
NDM
block library
IC Compiler II Library Manager
Library Manager(icc2_lm_shell) Flow
Library Prep-icc2_lm_shell
create_workspace 需要指定一个名字以及需要的tech file read_db read_lef check_workspace commit_workspace 保存ndm APR Flow - Design & Timing Setup
create a design library
load the netlist and power intent(UPF)
apply the floorplan
load the scan chain definitions(scan-DEF)
perform MCMM setup
apply timing and optimization controls
Create a “Container”: The Design Library
lappend search_path /x/y/libs
create_libs ORCA.dlib -use_technology_lib abc14_9m_tech.ndm -ref_libs {
abc14_9m_tech.ndm
abc14_hvt_std.ndm abc14_svt_std.ndm abc14_lvt_std.ndm
abc14_srams.ndm abc14_ip.ndm
}Read the Netlist and Create a Design
lappend search_path ./netlist
read_verilog -top ORCA ORCA.v
link_blockMultiple Modes and Multiple Corners
Concurrent MCMM Optimization
Mode, Corner and Scenario Setup
create_mode M1 create_mode M2 create_corner C1; // Common corner to both modes create_scenario -mode M1 -corner C1 -name M1_C1 create_scenario -mode M2 -corner C1 -name M2_C1 Loading Constraints
current_scenario M1_C1 current_scenario M2_C1
read_sdc C1_corner.sdc read_sdc M2_mode.sdc
read_sdc M1_mode.sdc read_sdc M2_C1_scenario.sdc
read_sdc M1_C1_scenario.sdc
read_sdc global_constraints.sdcDefining PVT Directly - Recommended
Specify TLUplus Parasitic RC Models
#if the TLUplus models have not been loaded into a technology library, they can #be loaded into the design library: #read_parasitic_tech -tlup $TLUPLUS_MAX_FILE -name maxLTU #read_parasitic_tech -tlup $TLUPLUS_MIN_FILE -name minTLU set_parasitic_parameters -corner c_slow -library $(techlib) -early_spec maxTLU -late_spec maxTLU set_parasitic_parameters -corner c_fast -library $(techlib) -early_spec minTLU -late_spec minTLU
Controlling Scenario Analysis / Optimization
create_scenario
set_scenario_statusAPR Flow - Floorplan Definition
Floorplanning Overview
Create the Initial Floorplan
initialize_floorplan -shape U Place Macros and Standard Cells
create_placement -floorplan [-congestion]
set_fixed_objects [get_flat_cells -filter 'is_hard_macro']在place_opt之前要把hard_macro fix住Place I/O Pins
set_block_pin_constraints -self -allowed_layers 'M3 M4' -sides '1 2 3' | -exclude_sides '4 5 6' set_individual_pin_constraints -ports ... place_pins -self Power Planning Challenges
Pattern_Based Power Network Synthesis
Write out the Floorplan for ICC II/DC-G
write_floorplan -output ORCA_TOP.fp
write_floorplan -format icc -output ORCA_TOP.fp.dc -net_types {power ground} -include_physical_status {fixed locked}APR Flow - Placement & Optimization
Key Steps of the Placement Phase
Design and Flow Requirement Setup Steps
Congestion-Focused Setup Steps
The Five Stages of place_opt
Placement and Logic Optimization: place_opt
Recommended place_opt Exploration Flow
Example Script
open_lib design.dlib
open_block floorplan
#Place setup
remove_ideal_network -all
set_lib_cell_purpose -include none [get_lib_cells '*/*BUF_X64* */*REG_ulvt*']
set_app_options -list [opt.power.mode none | leakage | dynamic | total]
#Apply Place configuration steps, as needed
set_scenario_set_scenario_status * -active false
set_scenario_status <list_of_placement_scenarios> -active true
set_scenario_status *corner_FAST -setup false
set_scenario_status mode_TEST* -leakage_power false
#Enable SPG, if applicable:
set_app_options -list {place_opt.flow.do_spg true}
place_optAPR Flow - CTS & Optimization
The definition of CTS
Clock Tree Synthesis Goal and Flows
Comparing Classic CTS versus CCD
Clock Tree Balancing Setup
# 设定clock tree balance
set_clock_balance_points
# 指定期望的延时以及相互之间的偏差
set_clock_tree_options
# 控制CTS选择哪种cell
set_lib_cell_purpose -include cts $cts_cells
set_dont_touch $cts_cells false
create_clock_balance_group
derive_clock_balance_constraints -slack_less_than -0.3Non-Default Rules
Defining/Applying NDR
create_routing_rule 2xs_2xW_CLK_RULE -width {M1 0.11 M2 0.11 M3 0.14 M4 0.14 M5 0.14} -spacings {M1 0.4 M2 0.4 M3 0.48 M4 0.48 M5 1.1}
-cuts {
{VIA3 {Vrect 1}} ... {VIA5 {Vrect 1}} }
set_clock_routing_rules -rule 2xs_2xW_CLK_RULE -min_routing_layer M4 -max_routing_layer M5Defining CTS-Specific DRC Values
set_max_transition <value> -clock_path [all_clocks] (default: 0.5ns)
set_max_capacitance <value> -clock_path [all_clocks] (default: 0.6pF)
set_max_transition 0.2 -clock_path -scenarios 'S1 S4' [get_clocks SYS_CLK]CTS Execution
clock_opt #CCD enabled clock_opt.flow.enable_ccd #four stages of clock_opt bulid_clock -> route_clock -> final_optp -> global_route_opt(optional) Analyzing CTS Results: Clock QoR Report
report_clock_qor [-type area | balance_groups | drc_violators | latency | local_skew | power | robustness | structure | summary] [-histogram_type latency | transition | level |...]
[-modes ...] [-corners ...]...Analyzing CTS Results: Clock Timing Report
report_clock_timing -type summary | transition | latency | ...
-modes {m1 m2}
-corners {c1 c2}...Example Script
open_lib design.dlib
open_block place
#CTS setup
source clock_tree_balance.tcl
source clock_routing_tules.tcl
source clock_constraints.tcl
#Apply CTS configuration steps, as needed
set_scenario_status -active true [all_scenarios]
set_scenario_status {s2 s4} -hold true
set_app_options -name clock_opt.hold.effort -value high
set_app_options -name cts.compile.enable_global_route -value true
set_app_options -name opt.common.allow_physical_feedthrough -value true
#Enable CCD, if applicable:
set_app_options -name clock_opt.flow.enbale_ccd -value true
clock_optAPR Flow - Routing & Optimization
Routing Phase Goal
Recommended Routing Flow
route_auto #Routing performs Global Routing -> Track Assignment -> Detail Routing route_opt
Check Zroute DRC Violations
check_routesExample Script
open_lib design.dlib
open_block cts
#route setup
source antenna_rules.tcl
set_app_options -list {
route.global.timing_driven true
route.track.timing_driven true
route.detail.timing_driven true
}
set_app_options -name time.si_enable_analysis -value true
#Apply route configuration steps, as needed
set_scenario_status -active true [all_scenarios]
set_scenario_status {s2 s4} -hold true
#Enable CCD, if applicable:
set_app_options -name route_opt.flow.enable_ccd -value true
route_auto
route_optAPR Flow - Signoff
Signoff
Prime Time Signoff-driven Physically Aware ECO Flow
Function ECO Flow
#Perform ECO comparison
eco_netlist -by_verilog_file ECO_netlist.v -write_changes ECO_changes.tcl
#Apply ECO changes and place
source ECO_changes.tcl
connect_pg_net
place_eco_cells -cel_changed_cells
#ECO routing and post-route optimization
route_eco -max_detail_wires true -utilize_dangling_wires true -open_net_driven true \
-reroute modified_nets_first_then_others
route_optStandard Cell Fillers and Metal Fill
Filler Insertion & Removal
#Insert filler cells. First cells with metal, then without #Should be sorted from largest to smallest set FILLER_CELL_METAL 'saed32/FILL128 saed32/FILL64 ... saed32/FILL2 saed32/FILL1' create_stdcell_fillers -lib_cells $FILLER_CELL_METAL connect_pg_net remove_stdcell_fillers_with_violation create_stdcell_fillers -lib_cells $FILLER_CELL_NO_METAL connect_pg_net
remove_cells [get_cells -hierarchical -filter design_type==filler]In-Design Signoff DRC Checking and Fixing
Signoff DRC using IC Validator
Metal Fill Insertion
Customer Support
Solvnet
Regerence Flow
ICC II介绍
ICC命令集请查看：ICC 命令集 ==注：==该文只是总结了ICC的一些命令，但是没有对应的解释，各命令具体含义，请在ICC命令行man一下进行查阅。 多级物理层次
可扩展Timer
并行优化
preroute optimization
主要特点
Fusion with redhawk
Fusion with StarRC & PT/PX
Fusion with ICV
other fusion
PT StarRC直接读取ICCII Database
ICC使用步骤Reference极术干货|Mount-新一代布局总线系统IC Compiler II 初识（PPT下载+视频回放） process corner工艺角什么是itf文件？什么是TLUplus文件？ AppendixSignoff (electronic design automation) Signoff (electronic design automation)In the automated design of integrated circuits, signoff (also written as sign-off) checks is the collective name given to a series of verification steps that the design must pass before it can be taped out. This implies an iterative process involving incremental fixes across the board using one or more check types, and then retesting the design. There are two types of sign-off’s: front-end sign-off and back-end sign-off. After back-end sign-off the chip goes to fabrication. After listing out all the features in the specification, the verification engineer will write coverage for those features to identify bugs, and send back the RTL design to the designer. Bugs, or defects, can include issues like missing features (comparing the layout to the specification), errors in design (typo and functional errors), etc. When the coverage reaches a maximum% then the verification team will sign it off. By using a methodology like UVM, OVM, or VMM, the verification team develops a reusable environment. Nowadays, UVM is more popular than others. Check typesSignoff checks have become more complex as VLSI designs approach 22nm and below process nodes, because of the increased impact of previously ignored (or more crudely approximated) second-order effects. There are several categories of signoff checks.
ToolsA small subset of tools are classified as “golden” or signoff-quality. Categorizing a tool as signoff-quality without vendor-bias is a matter of trial and error, since the accuracy of the tool can only be determined after the design has been fabricated. So, one of the metrics that is in use (and often touted by the tool manufacturer/vendor) is the number of successful tapeouts enabled by the tool in question. It has been argued that this metric is insufficient, ill-defined, and irrelevant for certain tools, especially tools that play only a part in the full flow.[1] While vendors often embellish the ease of end-to-end (typically RTL to GDS for ASICs, and RTL to timing closure for FPGAs) execution through their respective tool suite, most semiconductor design companies use a combination of tools from various vendors (often called “best of breed” tools) in order to minimize correlation errors pre- and post-silicon.[2] Since independent tool evaluation is expensive (single licenses for design tools from major vendors like Synopsys and Cadence may cost tens or hundreds of thousands of dollars) and a risky proposition (if the failed evaluation is done on a production design, resulting in a time to market delay), it is feasible only for the largest design companies (like Intel, IBM, Freescale, and TI). As a value add, several semiconductor foundries now provide pre-evaluated reference/recommended methodologies (sometimes referred to as “RM” flows) which includes a list of recommended tools, versions, and scripts to move data from one tool to another and automate the entire process.[3] This list of vendors and tools is meant to be representative and is not exhaustive:
References
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