本公众号【读芯树:duxinshu_PD】主要介绍数字集成电路物理设计相关知识,才疏学浅,如有错误,欢迎指正交流学习。 这是集成电路物理设计的第六个系列【Physical Verification】的第十一篇文章,本篇文章主要介绍PERC相关内容: 01 — 什么是PERC?
02 — Why PERC?
03 — Calibre PERC Catalog
04 — PERC in the Design Flow
05 — Calibre PERC cmd calibre -perc -hier -auto rules #run PERC hier on a netlist and have hcells recognized automatically calibre -per -hier -hcell cell_list rules #run PERC hier on a netlist and have recognized from a user-specified hcell list calibre -perc rules #run PERC flat on a netlist calibre -spice lay.net -perc -hier -auto rules #run PERC hier on a layout and have hcells recoginezed auto calibre -spice lay.net -perc rules #run PERC flat on a layout
TVF FUNCTION esd [/* package require CalibreLVS_PERCproc esd_init {} { perc::define_net_type 'Power' {lvsPower} perc::define_net_type 'Ground' {lvsGround} perc::define_net_type 'Pad' {in_pad? out_pad?} perc::create_net_path -type 'r'}proc rule_1 {} { perc::check_net -netType {!Power && !Ground} -pathType {Pad} -condition cond_1 -comment 'PAD with incorrect ESD protection'}proc cond_1 {net} { set selected 0 set logic_gate_count [perc::count -net $net -type {lvsGate} -pinAtNet {lvsIn}] if {$logic_gate_count ==0} { return $selected } set result [perc::count -net $net -type {r} -pinAtNet {p n} -pinNetType {{p n} {Pad}} -list] set res_count [lindex $result 0] if {$res_count == 0} { perc::report_base_result -title 'Missing Resistor' set selected 1 } if {$res_count > 0} { set res_itr [lindex $res_list 0] set res_val [perc::property $res_itr r] if {$res_val < 100} { perc::report_base_result -value 'Resistor exists but with value less than 100 ohm: $res_val' -list [list $res_itr] set selected 1 } } set nest_count [perc::count -net $net -type {MN} -subtype {nch_esd} -pinAtNet {D} -pinNetType {{g} {Ground} {s} {Ground} {b} {Ground}}] if {$nesd_count == 0} { perc::report_base_result -title 'Missing ESD nmos device' set selected 1 } return $selected }*/] PERC cmd: lvsGate: device type referring to all logic gates lvsInjection: device type referring to all logic injection device lvsIn: pin name referring to all input pins of logic gates and gate-based injection devices lvsOut: pin name referring to all output pins of logic gates and gate-based injection devices lvsPower: list of power nets defined by 'LVS POWER NAME' statement lvsGround: list of ground nets defined by 'LVS GROUND NAME' statement lvsTopPorts: list of nets connected to ports in the top cell lvsTop: generic cell name referring to the top level cell 06 — 参考文献 https://www./glossary/what-is-programmable-electrical-rules-checking.htmlCalibre PER User GuideCalibre PERC Catalog test-case and common examples |
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