第3章 VHDL基础
3-1 如图所示
程序：
IF_THEN语句
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY mux21 S
PORT ( s1,s0 : IN STD_LOGIC_VECTOR ;
a,b,c,d : IN STD_LOGIC ;
y : OUT STD_LOGIC ) ;
END ENTITY mux21 ;
ARCHITECTURE one OF mux21 IS
BEGIN
PROCESS ( s0,s1,a,b,c,d )
BEGIN
IF s1=’0’ AND s0=’0’ THEN y<=a ;
ELSIF s1=’0’ AND s0=’1’ THEN y<=b ;
ELSIF s1=’1’ AND s0=’0’ THEN y<=c ;
ELSIF s1=’1’ AND s0=’1’ THEN y<=d ;
ELSE y<=NULL ;
END IF ;
END PROCESS ;
END ARCHITECTURE one ;
CASE 语句
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY mux21 IS
PORT ( s1,s0 : IN STD_LOGIC_VECTOR ;
a,b,c,d : IN STD_LOGIC ;
y : OUT STD_LOGIC ) ;
END ENTITY mux21 ;
ARCHITECTURE two OF mux21 IS
SIGNAL s : STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ;
BEGIN
s<=s1 & s0 ;
PROCESS ( s )
BEGIN
CASE s IS
WHEN “00” => y<=a ;
WHEN “01” => y<=b ;
WHEN “10” => y<=c ;
WHEN “11” => y<=d ;
WHEN OTHERS => NULL ;
END CASE ;
END PROCESS ;
END ARCHITECTURE two ;
3-3 程序：
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY MUXK IS
PORT ( s0,s1 : IN STD_LOGIC ;
a1,a2,a3 : IN STD_LOGIC ;
outy : OUT STD_LOGIC ) ;
END ENTITY MUXK ;
ARCHITECTURE double OF MUXK IS
SIGNAL tmp : STD_LOGIC ; --内部连接线
SIGNAL u1_s, u1_a, u1_b, u1_y : STD_LOGIC ;
SIGNAL u2_s, u2_a, u2_b, u2_y : STD_LOGIC ;
BEGIN
p_MUX21A_u1 : PROCESS ( u1_s, u1_a, u1_b, u1_y )
BEGIN
CASE u1_s IS
WHEN ‘0’ => u1_y<= u1_a ;
WHEN ‘1’ => u1_y<= u1_b ;
WHEN OTHERS => NULL ;
END CASE ;
END PROCESS p_ MUX21A_u1 ;
p_ MUX21A_u2 : PROCESS ( u2_s, u2_a, u2_b, u2_y )
BEGIN
CASE u2_s IS
WHEN ‘0’ => u2_y<= u2_a ;
WHEN ‘1’ => u2_y<= u2_b ;
WHEN OTHERS => NULL ;
END CASE ;
END PROCESS p_ MUX21A_u2 ;
u1_s<= s0 ; u1_a<= a2 ; u1_b<= a3 ;
tmp<= u1_y ;
u2_s<=s1 ; u2_a<= a1 ; u2_b<= tmp;
outy <= u2_y ;
END ARCHITECTURE double ;
3-4 程序：
（1）1位半减器
1位半减器的设计选用（2）图，两种表达方式：
一、 LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY h_suber IS
PORT ( x,y : IN STD_LOGIC ;
s_out ,diff : OUT STD_LOGIC ) ;
END ENTITY h_suber ;
ARCHITECTURE fhd1 OF h_suber IS
BEGIN
diff<=x XOR y ; s_out<= ( NOT a ) AND b ;
END ARCHITECTURE fhd1 ;
二、 LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY h_suber IS
PORT ( x,y : IN STD_LOGIC ;
s_out ,diff : OUT STD_LOGIC ) ;
END ENTITY h_suber ;
ARCHITECTURE fhd1 OF h_suber IS
SIGNAL s : STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ;
BEGIN
s<= x & y ;
PROCESS ( s )
BEGIN
CASE s IS
WHEN “00” => s_out <=’0’ ; diff<=’0’ ;
WHEN “01” => s_out <=’1’ ; diff<=’1’ ;
WHEN “10” => s_out <=’0’ ; diff<=’1’ ;
WHEN “11” => s_out <=’0’ ; diff<=’0’ ;
WHEN OTHERS => NULL ;
END CASE ;
END PROCESS ;
END ARCHITECTURE fhd1 ;
或门逻辑描述：
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY or IS
PORT ( a,b : IN STD_LOGIC ;
c : OUT STD_LOGIC ) ;
END ENTITY or ;
ARCHITECTURE one OF or IS
BEGIN
c<= a OR b ;
END ARCHITECTURE one ;
1位全减器：
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY f_suber IS
PORT ( x,y,sub_in : IN STD_LOGIC ;
sub_out ,diffr : OUT STD_LOGIC ) ;
END ENTITY f_suber ;
ARCHITECTURE fhd1 OF f_suber IS
COMPONENT h_suber IS
PORT ( x,y : IN STD_LOGIC ;
s_out ,diff : OUT STD_LOGIC ) ;
END COMPONENT h_suber ;
COMPONENT or IS
PORT ( a,b : IN STD_LOGIC ;
c : OUT STD_LOGIC ) ;
END COMPONENT or ;
SIGNAL d,e,f : STD_LOGIC ;
BEGIN
u1 : h_suber PORT MAP ( x=>x, y=>y, diff=>d, s_out=>e ) ;
u2 : h_suber PORT MAP ( x=>d, y=>sub_in, diff=>diffr, s_out=>f ) ;
u3 : or PORT MAP ( a=>f, b=>e, c=>sub_out ) ;
END ARCHITECTURE fhd1 ;
（2）8位减法器：
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY 8f_suber IS
PORT ( x0,x1,x2,x3,x4,x5,x6,x7 : IN STD_LOGIC ;
y0,y1,y2,y3,y4,y5,y6,y7 : IN STD_LOGIC ;
sub_in : IN STD_LOGIC ;
sub_out : OUT STD_LOGIC ;
diffr0,diffr1,diffr2,diffr3 : OUT STD_LOGIC ;
diffr4,diffr5,diffr6,diffr7 : OUT STD_LOGIC ) ;
END ENTITY 8f_suber ;
ARCHITECTURE 8fhd1 OF 8f_suber IS
COMPONENT f_suber IS
PORT ( x,y,sub_in : IN STD_LOGIC ;
sub_out ,diffr : OUT STD_LOGIC ) ;
END COMPONENT f_suber ;
SIGNAL a,b,c,d,e,f,g : STD_LOGIC ;
BEGIN
u0 : f_suber PORT MAP ( x=>x0, y=>y0, sub_in=>, sub_out=>a, diff=>diff0 ) ;
u1 : f_suber PORT MAP ( x=>x1, y=>y1, sub_in=>a, sub_out=>b, diff=>diff1 ) ;
u2 : f_suber PORT MAP (x=>x2, y=>y2, sub_in=>b, sub_out=>c, diff=>diff2 ) ;
u3 : f_suber PORT MAP (x=>x3, y=>y3, sub_in=>c, sub_out=>d, diff=>diff3 ) ;
u4 : f_suber PORT MAP (x=>x4, y=>y4, sub_in=>d, sub_out=>e, diff=>diff4 ) ;
u5 : f_suber PORT MAP (x=>x5, y=>y5, sub_in=>e, sub_out=>f, diff=>diff5 ) ;
u6 : f_suber PORT MAP (x=>x6, y=>y6, sub_in=>f, sub_out=>g, diff=>diff6 ) ;
u7 : f_suber PORT MAP (x=>x7, y=>y7, sub_in=>g, sub_out=> sub_out, diff=>diff7 ) ;
END ARCHITECTURE 8fhd1 ;
3-5 程序：
或非门逻辑描述：
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY nor IS
PORT ( d, e : IN STD_LOGIC ;
f : OUT STD_LOGIC ) ;
END ENTITY nor ;
ARCHITECTURE one OF nor IS
BEGIN
f <= NOT ( d OR e ) ;
END ARCHITECTURE one ;
时序电路描述：
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY circuit IS
PORT ( CL, CLK0 : IN STD_LOGIC ;
OUT1 : OUT STD_LOGIC ) ;
END ENTITY circuit ;
ARCHITECTURE one OF circuit IS
COMPONENT DFF1 IS
PORT ( CLK : IN STD_LOGIC ;
D : IN STD_LOGIC ;
Q : OUT STD_LOGIC ) ;
END COMPONENT DFF1 ;
COMPONENT nor IS
PORT ( d, e : IN STD_LOGIC ;
f : OUT STD_LOGIC ) ;
END COMPONENT nor ;
COMPONENT not IS
PORT ( g : IN STD_LOGIC ;
h : OUT STD_LOGIC ) ;
END COMPONENT not ;
SIGNAL a, b : STD_LOGIC ;
BEGIN
u0 : nor PORT MAP ( d=>b, e=>CL, f=>a ) ;
u1 : DFF1 PORT MAP ( CLK=>CLK0, D=>a, Q=>b ) ;
u2 : not PORT MAP ( g=>b, h=>OUT1 ) ;
END ARCHITECTURE one ;
3-6 LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY MX3256 IS
PORT( INA,INB,INCK,INC: IN STD_LOGIC ;
E,OUT1: OUT STD_LOGIC) ;
END ENTITY MX3256;
ARCHITECTURE one OF MX3256 IS
COMPONENT LK35 IS
PORT ( A1,A2,CLK: IN STD_LOGIC ;
O1,O2: OUT STD_LOGIC) ;
END COMPONENT LK35;
BEGIN
3-7
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_unsigned.ALL ;
ENTITY CNT IS
PORT( CLK,EN,RST,opcode: IN STD_LOGIC ;
CQ: OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ;
COUT: OUT STD_LOGIC) ;
END ENTITY CNT;
ARCHITECTURE behav1 OF CNT IS
BEGIN
PROCESS( RST,EN,CLK,opcode )
VARIABLE CQI: STD_LOGIC_VECTOR( 15 DOWNTO 0) ;
begin
IF RST=’1’ THEN CQI:=( OTHERS=>’0’) ;
ELSIF EN=’1’ THEN
IF CLK’EVENT AND CLK=’1’ THEN
CASE opcode IS
WHEN ‘0’ =>CQI:=CQI+1;
WHEN ‘1’ =>CQI:=CQI-1;
WHEN OTHERS =>NULL;
END CASE;
END IF;
END IF;
CASE opcode IS
WHEN ‘0’ => IF CQI=65535 THEN COUT<=’1’;
ELSE COUT<=’0’;
END IF;
WHEN ‘1’ => IF CQI=0 THEN COUT<=’1’;
ELSE COUT<=’0’;
END IF;
WHEN OTHERS =>NULL;
END CASE;
CQ<=CQI;
END PROCESS;
END behav1;
3-8
3-9
3-10
3-11
3-12
3-13
3-14
程序1：
SIGNAL A,EN : STD_LOGIC ;
PROCESS ( A, EN )
VARIABLE B : STD_LOGIC ;
BEGIN
IF EN = ‘1’ THEN B := A ;
END IF ;
END PROCESS ;
程序2：
ARCHITECTURE one OF sample IS
BEGIN
PROCESS ( )
VARIABLE a,b,c : integer range…;
BEGIN
c := a+b ;
END PROCESS;
END ARCHITECTURE one ;
程序3：
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY mux21 IS
PORT ( a,b : IN STD_LOGIC ;
sel : IN STD_LOGIC ;
c : OUT STD_LOGIC ) ;
END ENTITY mux21 ;
ARCHITECTURE one OF mux21 IS
BEGIN
PROCESS ( )
BEGIN
IF sel = ‘0’ THEN c<=a ;
ELSE c<=b ;
END IF ;
END PROCESS;
END ARCHITECTURE one ;
第4章 Quartus II使用方法
习题
4-1
第5章 VHDL状态机
习题
5-1 例5-4（两个进程）：
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY MOORE1 IS
PORT ( DATAIN : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ;
CLK,RST : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ) ;
END ENTITY MOORE1 ;
ARCHITECTURE behav OF MOORE1 IS
TYPE ST_TYPE IS ( ST0,ST1,ST2,ST3,ST4 ) ;
SIGNAL C_ST ,N_ST : ST_TYPE ;
BEGIN
REG : PROCESS ( RST ,CLK )
BEGIN
IF RST=’1’ THEN C_ST<=ST0; Q<=”0000”;
ELSIF CLK ’EVENT AND CLK=’1’ THEN
C_ST<=N_ST ;
END IF ;
END PROCESS ;
COM : PROCESS (C_ST , DATAIN)
BEGIN
CASE C_ST IS
WHEN ST0 =>
IF DATAIN = “10” THEN N_ST <= ST1 ;
ELSE N_ST <= ST0 ;
END IF ;
Q <=”1001” ;
WHEN ST1 =>
IF DATAIN = “11” THEN N_ST <= ST2 ;
ELSE N_ST <= ST1 ;
END IF ;
Q <=” 0101” ;
WHEN ST2 =>
IF DATAIN = “01” THEN N_ST <= ST3 ;
ELSE N_ST <= ST0 ;
END IF ;
Q <=” 1100” ;
WHEN ST3 =>
IF DATAIN = “00” THEN N_ST <= ST4 ;
ELSE N_ST <= ST2 ;
END IF ;
Q <=” 0010” ;
WHEN ST4 =>
IF DATAIN = “11” THEN N_ST <= ST0 ;
ELSE N_ST <= ST3 ;
END IF ;
Q <=” 1001” ;
WHEN OTHERS => N_ST <= ST0 ;
END CASE ;
END PROCESS ;
END ARCHITECTURE behav ;
5-2 例5-5（单进程）：
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY MEALY1 IS
PORT ( CLK, DATAIN ,RESET : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR ( 4 DOWNTO 0 ) ) ;
END ENTITY MEALY1 ;
ARCHITECTURE behav OF MEALY1 IS
TYPE states IS ( st0,st1,st2,st3,st4 ) ;
SIGNAL STX : states ;
BEGIN
PROCESS ( CLK, RESET )
BEGIN
IF RESET = ‘1’ THEN STX<= st0 ;
ELSIF CLK’ EVENT AND CLK = ‘1’ THEN
CASE STX IS
WHEN st0 =>
IF DATAIN = ‘1’ THEN STX<= st1; Q<=”10000” ;
ELSE Q<=”01010” ;
END IF ;
WHEN st1 =>
IF DATAIN = ‘0’ THEN STX<= st2; Q<=”10111” ;
ELSE Q<=” 10100” ;
END IF ;
WHEN st2 =>
IF DATAIN = ‘1’ THEN STX<= st3; Q<=”10101” ;
ELSE Q<=” 10011” ;
END IF ;
WHEN st3 =>
IF DATAIN = ‘0’ THEN STX<= st4; Q<=”11011” ;
ELSE Q<=” 01001” ;
END IF ;
WHEN st4 =>
IF DATAIN = ‘1’ THEN STX<= st0; Q<=”11101” ;
ELSE Q<=” 01101” ;
END IF ;
WHEN OTHERS => STX<=st0; Q<=”00000” ;
END CASE ;
END PROCESS ;
END ARCHITECTURE behav ;
5-3 序列检测器：
要求1：
要求2：
要求3：
5-4
5-5
第6章 16位CISC CPU设计
习题
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
第7章 VHDL语句
习题
7-1
7-2
7-3
7-4 因为每条并行赋值语句在结构体中是同时执行的，所以每条并行赋值语句都相当于一条缩写的进程语句，这条语句的所有输入信号都被隐性地列入此缩写进程的敏感信号表中。
7-5
7-6 CASE语句、WITH_SELECT语句 ：
共同点：执行依赖敏感信号的变化，子句条件选择值同时测试，因此不允许条件重叠，也不允许条件涵盖不全；
异同点：CASE语句是顺序语句，仅在进程中使用；
WITH_SELECT语句是并行语句；
7-7 程序：
ENTITY ---- IS
PORT ( a, b : IN STD_LOGIC ;
c, d : IN STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ;
next1 : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ) ;
ENTITY ---- ;
ARCHITECTURE behav OF ---- IS
BEGIN
Next1 <= “1101” WHEN a=’0’ AND b=’1’ ELSE
d WHEN a=’0’ ELSE
c WHEN b=’1’ ELSE
“1011” ;
END ARCHITECTURE behav ;
7-8 程序1：x是信号；程序2：x是变量；
第8章 VHDL结构
习题
8-1 设计实体：独立的电路功能结构；
实体：设计实体的表层设计单元，是对设计实体与外部电路进行接口描述，是设计实体对外的一个通信界面。
8-2 【例7-18】
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY andn IS
GENERIC ( n : INTEGER ); --定义类属参量及其数据类型
PORT(a : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);--用类属参量限制矢量长度
c : OUT STD_LOGIC);
END;
ARCHITECTURE behav OF andn IS
BEGIN
PROCESS (a)
VARIABLE int : STD_LOGIC;
BEGIN
int := ''1'';
FOR i IN a''LENGTH - 1 DOWNTO 0 LOOP --循环语句
IF a(i)=''0'' THEN int := ''0'';
END IF;
END LOOP;
c <=int ;
END PROCESS;
END;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY exn IS
PORT(d1,d2,d3,d4,d5,d6,d7 : IN STD_LOGIC;
q1,q2 : OUT STD_LOGIC);
END;
ARCHITECTURE exn_behav OF exn IS
COMPONENT andn --调用例10-1的元件调用声明
GENERIC ( n : INTEGER);
PORT(a : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);
C : OUT STD_LOGIC);
END COMPONENT ;
BEGIN
u1: andn GENERIC MAP (n =>2)
--参数传递映射语句，定义类属变量，n赋值为2
PORT MAP (a(0)=>d1,a(1)=>d2,c=>q1);
u2: andn GENERIC MAP (n =>5) --定义类属变量，n赋值为5
PORT MAP (a(0)=>d3,a(1)=>d4,a(2)=>d5,
a(3)=>d6,a(4)=>d7, c=>q2);
END;
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
ENTITY decoder3t08 IS
port ( input: IN STD_LOGIC_VECTOR ( 2 DOWNTO 0 ) ;
output: OUT BIT_VECTOR ( 7 DOWNTO 0 ) ) ;
END ENTITY decoder3t08 ;
ARCHITECTURE behave OF decoder3t08 IS
BEGIN
output <= “00000001” SLL CONV_INTEGER ( input ) ;
input output
000 00000001
001 00000010
010 00000100
011 00001000
100 00010000
101 00100000
110 01000000
111 10000000
END behave ;
8-7 不能，因为求和操作符“+”的操作数的数据类型必须是整数；解决方法：设计一个函数FUNCTION“+”(A,B：STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTORconv_integer( )将A、B转换成整数，A+B=>C,然后再用conv_std_logic_vector( )将C转换成std_logic_vector类型。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
PACKAGE STD_LOGIC_UNSIGNED IS
FUNCTION “+”( L,R: STD_LOGIC_VECTOR )
RETURN STD_LOGIC_VECTOR;
END STD_LOGIC_UNSIGNED;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
PACKAGE BODY STD_LOGIC_UNSIGNED IS
FUNCTION “+”(L,R: STD_LOGIC_VECTOR; )
RETURN STD_LOGIC_VECTOR IS
VARIABLE result: INTEGER RANGE –255 TO +255;
BEGIN
result:=CONV_INTEGER( L ) + CONV_INTEGER( R );
RETURN CONV_STD_LOGIC_VECTOR( result, L’length);
END;
END STD_LOGIC_UNSIGNED;
……
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE. STD_LOGIC_UNSIGNED.ALL;
ENTITY ADDER IS
PORT( A,B: IN STD_LOGIC_VECTOR;
C: OUT STD_LOGIC_VECTOR);
END ENTITY ADDER;
ARCHITECTURE behav OF ADDER IS
BEGIN
C<=A+B;
END behav;
8-8 数据对象3类：
1）常量（CONSTANT）
CONSTANT 常数名：数据类型：=表达式
2）变量（VARIABLE）
VARIABLE 变量名：数据类型：=初始值
3）信号（SIGNAL）
SIGNAL 信号名：数据类型：=初始值
例如：
SIGNAL a: STD_LOGIC_VECTOR;
8-9 能。
FUNCTION DECIMAL
( X: std_logic_vector;CARDINAL_Num:integer ) RETURN integer IS
BEGIN
VARIABLE temp: integer:=0;
FOR I in X’ length-1 DOWNTO 1 LOOP
temp:=( temp+X( I ) )CARDINAL_Num;
END LOOP;
temp:=temp+X(0);
RETURN temp;
END FUNCTION DECIMAL;
8-10 16#0FA# -- 起始为非英文字母；
符号“#”不能成为标识符的构成；
10#12F# -- 同上
8#789# -- 同上
8#356# -- 同上
2#0101010# -- 同上
74HC245 -- 起始为非英文字母；
\74HC574\ -- 符号“\”不能成为标识符的构成；
CLR/RESET -- 符号“\”不能成为标识符的构成；
\IN 4/SCLK\ -- 符号“\、/”和空格不能成为标识符的构成；
D100% -- 符号“%”不能成为标识符的构成；
8-11 BIT、INTEGER、BOOLEAN：STD库；
IEEE：STD_LOGIC_1164、NUMERIC_BIT、NUMERIC_STD、MATH_REAL、MATH_COMPLEX —>显式表达；
STD ：STANDARD、TEXTIO —>无须显式表达；
WORK ：无须显式表达，总是可见；
8-12
8-13 （1）BIT ：枚举型，值 ：0/1，数据对象 ：变量、信号，
参与逻辑运算，参与关系运算（=，=/）；
BOOLEAN ：枚举型，值 ：FALSE/TRUE，关系运算符、逻辑运算符获得；
（2）都可以，逻辑操作的基本数据类型 ：BIT、BOOLEAN、STD_LOGIC及BIT、STD_LOGIC所对应的等长的一维矢量；
（3）BOOLEAN类型；
（4）BOOLEAN类型；
8-14 程序 ：
LIBRARY IEEE ;
USE ---- ;
USE IEEE.STD_LOGIC_ARITH.ALL ;
PACKAGE STD_LOGIC_UNSIGNED IS
FUNCTION “ + ” ( L : AGE ; R : INTEGER )
RETURN AGE ;
END STD_LOGIC_UNSIGNED ;
LIBRARY IEEE ;
USE ---- ;
USE IEEE.STD_LOGIC_ARITH.ALL ;
PACKAGE BODY STD_LOGIC_UNSIGNED IS
FUNCTION “ + ” ( L : AGE ; R : INTEGER ; )
RETURN AGE IS
VARIABLE RESULT : INTEGER ;
BEGIN
RESULT := CONV_INTEGER(L)+R ;
RETURN CONV_AGE(RESULT) ;
END FUNCTION “ + ” ;
----
END STD_LOGIC_UNSIGNED ;
LIBRARY IEEE ;
USE ---- ;
USE IEEE.STD_LOGIC_ARITH.ALL ;
USE IEEE. STD_LOGIC_UNSIGNED.ALL
ENTITY ---- IS
PORT ( ---- ) ;
END ENTITY ---- ;
ARCHITECTURE ---- OF ---- IS
SIGNAL a, c : AGE ;
----
BEGIN
c <= a + 20 ;
END ARCHITECTURE ---- OF ---- ;
8-15
第一种设计方案:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity comp8 is
port (a,b: in integer range -127 to 127;
d,e,f: out std_logic );
end comp8;
architecture behav1 of comp8 is
begin
process (a,b)
begin
d<=’0’;e<=’0’;f<=’0’;
if (a=b) then d<=’1’;
elsif (a>b) then e<=’1’;
else f<=’1’;
end if;
end process;
end architecture behav1;
第二种设计方案：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity comp8 is
port (a,b: in signed(8 downto 0);
d,e,f: out integer range 0 to 1);
end comp8;
architecture behav2 of comp8 is
begin
process (a,b)
variable c: signed(8 downto 0);
begin
d<=0;e<=0;f<=0;
c:=a-b;
if (c=0)then d<=1;
elsif (c(8)=''0'') then e<=1;
else f<=1;
end if;
end process;
end architecture behav2;
问题：
1．任意一个二进制数都有符号位？
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