4-Channel, 500 MSPS DDS with 10-Bit DACs Data Sheet AD9959 FEATURES Software-/hardware-controlled power-down Dual supply operation (1.8 V DDS core/3.3 V serial I/O) 4 synchronized DDS channels @ 500 MSPS Multiple device synchronization Independent frequency/phase/amplitude control between Selectable 4× to 20× REFCLK multiplier (PLL) channels Selectable REFCLK crystal oscillator Matched latencies for frequency/phase/amplitude changes 56-lead LFCSP package Excellent channel-to-channel isolation (>65 dB) Linear frequency/phase/amplitude sweeping capability APPLICATIONS Up to 16 levels of frequency/phase/amplitude modulation Agile local oscillators (pin-selectable) Phased array radars/sonars 4 integrated 10-bit digital-to-analog converters (DACs) Instrumentation Individually programmable DAC full-scale currents Synchronized clocking 0.12 Hz or better frequency tuning resolution RF source for AOTF 14-bit phase offset resolution 10-bit output amplitude scaling resolution Serial I/O port interface (SPI) with enhanced data throughput FUNCTIONAL BLOCK DIAGRAM RECONSTRUCTED 10-BIT DAC SINE WAVE (4) RECONSTRUCTED 500MSPS 10-BIT DAC SINE WAVE DDS CORES RECONSTRUCTED 10-BIT DAC SINE WAVE MODULATION CONTROL RECONSTRUCTED 10-BIT DAC SYSTEM TIMING AND SINE WAVE REF CLOCK CLOCK CONTROL INPUT CIRCUITRY SOURCE USER INTERFACE Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 ?2005–2016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 05246-101AD9959 Data Sheet TABLE OF CONTENTS Linear Sweep Mode .................................................................... 25? Features .............................................................................................. 1? Linear Sweep No-Dwell Mode ................................................. 26? Applications ....................................................................................... 1? Sweep and Phase Accumulator Clearing Functions .............. 27? Functional Block Diagram .............................................................. 1? Output Amplitude Control Mode ............................................ 28? General Description ......................................................................... 3? Synchronizing Multiple AD9959 Devices ................................... 29? Specif ica t ions ..................................................................................... 4? Automatic Mode Synchronization ........................................... 29? Absolute Maximum Ratings ............................................................ 8? Manual Software Mode Synchronization ................................ 29? ESD Caution .................................................................................. 8? Manual Hardware Mode Synchronization .............................. 29? Pin Configuration and Function Descriptions ............................. 9? I/O_UPDATE, SYNC_CLK, and System Clock Typical Performance Characteristics ........................................... 11? Relationships ............................................................................... 30? Application Circuits ....................................................................... 14? Serial I/O Port ................................................................................. 31? Equivalent Input and Output Circuits ......................................... 17? Overview ..................................................................................... 31? Theory of Operation ...................................................................... 18? Instruction Byte Description .................................................... 32? DDS Core ..................................................................................... 18? Serial I/O Port Pin Description ................................................ 32? Digital-to-Analog Converter .................................................... 18? Serial I/O Port Function Description ...................................... 32? Modes of Operation ....................................................................... 19? MSB/LSB Transfer Description ................................................ 32? Channel Constraint Guidelines ................................................ 19? Serial I/O Modes of Operation ................................................. 33? Power Supplies ............................................................................ 19? Register Maps and Bit Descriptions ............................................. 36? Single-Tone Mode ...................................................................... 19? Register Maps .............................................................................. 36? Reference Clock Modes ............................................................. 20? Descriptions for Control Registers .......................................... 39? Scalable DAC Reference Current Control Mode ................... 21? Descriptions for Channel Registers ......................................... 41? Power-Down Functions ............................................................. 21? Outline Dimensions ....................................................................... 44? Modulation Mode ....................................................................... 21? Ordering Guide .......................................................................... 44? Modulation Using SDIO_x Pins for RU/RD........................... 24? REVISION HISTORY 10/2016—Rev. B to Rev. C Changes to Layout ............................................................................. 8 Change to Figure 37 Caption ........................................................ 26 Changes to Table 3 ............................................................................. 9 Updated Outline Dimensions ....................................................... 44 Added Equivalent Input and Output Circuits Section .............. 17 Changes to Figure 35 ...................................................................... 21 7/2008—Rev. A to Rev. B Changes to Setting the Slope of the Linear Sweep Section ....... 25 Added Pin Profile Toggle Rate Parameter in Table 1 ................... 6 Changes to Frequency Linear Sweep Example: AFP Bits = 10 Changes to Figure 24 ...................................................................... 14 S ection .............................................................................................. 26 Changes to Figure 31 ...................................................................... 17 Changes to Figure 37 ...................................................................... 26 Changes to Reference Clock Input Circuitry Section ................ 20 Changes to Figure 38 and Figure 39............................................. 27 Changes to Operation Section ...................................................... 29 Added Table 25 ............................................................................... 31 Changes to Figure 40 ...................................................................... 30 Changes to Figure 41 ...................................................................... 31 Changes to Serial Data I/O (SDIO_0, SDIO_1, SDIO_3) Changes to Figure 42 ...................................................................... 32 Section .............................................................................................. 32 Added Example Instruction Byte Section ................................... 32 Changes to Table 38 ........................................................................ 43 Added Table 27 ............................................................................... 33 Added Exposed Pad Notation to Outline Dimensions ............. 44 Changes to Figure 46, Figure 47, Figure 48, and Figure 49....... 35 Changes to Register Maps and Bit Descriptions Section .......... 36 3/2008—Rev. 0 to Rev. A Added Endnote 1 to Table 30 ........................................................ 38 Changes to Ordering Guide .......................................................... 44 Changes to Features .......................................................................... 1 Inserted Figure 1 ............................................................................... 1 Changes to Input Level Specification ............................................. 4 7/2005—Revision 0: Initial Version Rev. C | Page 2 of 44 CHANNEL REGISTERS Data Sheet AD9959 GENERAL DESCRIPTION The AD9959 consists of four direct digital synthesizer (DDS) frequency tuning word, 14 bits of phase offset, and a 10-bit cores that provide independent frequency, phase, and amplitude output scale multiplier. control on each channel. This flexibility can be used to correct The DAC outputs are supply referenced and must be terminated imbalances between signals due to analog processing, such as into AVDD by a resistor or an AVDD center-tapped transformer. filtering, amplification, or PCB layout-related mismatches. Each DAC has its own programmable reference to enable Because all channels share a common system clock, they are different full-scale currents for each channel. inherently synchronized. Synchronization of multiple devices The DDS acts as a high resolution frequency divider with the is supported. REFCLK as the input and the DAC providing the output. The The AD9959 can perform up to a 16-level modulation of fre- REFCLK input source is common to all channels and can be quency, phase, or amplitude (FSK, PSK, ASK). Modulation is driven directly or used in combination with an integrated performed by applying data to the profile pins. In addition, the REFCLK multiplier (PLL) up to a maximum of 500 MSPS. AD9959 also supports linear sweep of frequency, phase, or The PLL multiplication factor is programmable from 4 to 20, amplitude for applications such as radar and instrumentation. in integer steps. The REFCLK input also features an oscillator The AD9959 serial I/O port offers multiple configurations to circuit to support an external crystal as the REFCLK source. provide significant flexibility. The serial I/O port offers an SPI- The crystal must be between 20 MHz and 30 MHz. The crystal compatible mode of operation that is virtually identical to the can be used in combination with the REFCLK multiplier. SPI operation found in earlier Analog Devices, Inc., DDS products. The AD9959 comes in a space-saving 56-lead LFCSP package. Flexibility is provided by four data pins (SDIO_0/SDIO_1/ The DDS core (AVDD and DVDD pins) is powered by a 1.8 V SDIO_2/SDIO_3) that allow four programmable modes of supply. The digital I/O interface (SPI) operates at 3.3 V and serial I/O operation. requires DVDD_I/O (Pin 49) be connected to 3.3 V. The AD9959 uses advanced DDS technology that provides low The AD9959 operates over the industrial temperature range of power dissipation with high performance. The device incorporates ?40°C to +85°C. four integrated, high speed 10-bit DACs with excellent wideband and narrow-band SFDR. Each channel has a dedicated 32-bit AD9959 CH0_IOUT cos(x) Σ Σ Σ DAC 32 32 15 10 10 CH0_IOUT CH1_IOUT Σ Σ Σ cos(x) 32 32 15 10 10 DAC CH1_IOUT CH2_IOUT cos(x) Σ Σ Σ 32 32 15 10 10 DAC CH2_IOUT CH3_IOUT cos(x) ΣΣΣ 32 32 15 10 10 DAC CH3_IOUT SCALABLE DAC REF DAC_RSET FTW 32 PHASE/ 14 AMP/ 10 CURRENT DFTW ?PHASE ?AMP SYNC_IN TIMING AND CONTROL LOGIC SYNC_OUT PWR_DWN_CTL I/O_UPDATE MASTER_RESET SYSTEM CONTROL CLK SYNC_CLK ÷4 REGISTERS SCLK CS SERIAL REF CLOCK REF_CLK MUX I/O MULTIPLIER SDIO_0 PORT 4× TO 20× SDIO_1 REF_CLK BUFFER/ BUFFER SDIO_2 XTAL PROFILE SDIO_3 OSCILLATOR REGISTERS 1.8V 1.8V CLK_MODE_SEL AVDD DVDD P0 P1 P2 P3 DVDD_I/O Figure 2. Detailed Block Diagram Rev. C | Page 3 of 44 DDS CORE DDS CORE DDS CORE DDS CORE 05246-001? AD9959 Data Sheet SPECIFICATIONS AVDD and DVDD = 1.8 V ± 5%; DVDD_I/O = 3.3 V ± 5%; T = 25°C; RSET = 1.91 k?; external reference clock frequency = 500 MSPS (REFCLK multiplier bypassed), unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments REFERENCE CLOCK INPUT CHARACTERISTICS See Figure 34 and Figure 35 Frequency Range REFCLK Multiplier Bypassed 1 500 MHz REFCLK Multiplier Enabled 10 125 MHz Internal VCO Output Frequency Range 1 VCO Gain Control Bit Set High 255 500 MHz 1 100 160 MHz VCO Gain Control Bit Set Low Crystal REFCLK Source Range 20 30 MHz Input Level 200 1000 mV Measured at each pin (single-ended) Input Voltage Bias Level 1.15 V Input Capacitance 2 pF Input Impedance 1500 Duty Cycle with REFCLK Multiplier Bypassed 45 55 % Duty Cycle with REFCLK Multiplier Enabled 35 65 % CLK Mode Select (Pin 24) Logic 1 Voltage 1.25 1.8 V 1.8 V digital input logic CLK Mode Select (Pin 24) Logic 0 Voltage 0.5 V 1.8 V digital input logic DAC OUTPUT CHARACTERISTICS Must be referenced to AVDD Resolution 10 Bits Full-Scale Output Current 1.25 10 mA Gain Error +10 %FS ?10 Channel-to-Channel Output Amplitude Matching Error ?2.5 +2.5 % Output Current Offset 1 25 μA Differential Nonlinearity ±0.5 LSB Integral Nonlinearity ±1.0 LSB Output Capacitance 3 pF Voltage Compliance Range AVDD ? 0.50 AVDD + 0.50 V Channel-to-Channel Isolation 65 dB DAC supplies tied together (see Figure 19) WIDEBAND SFDR The frequency range for wideband SFDR is defined as dc to Nyquist 1 MHz to 20 MHz Analog Output ?65 dBc 20 MHz to 60 MHz Analog Output dBc ?62 60 MHz to 100 MHz Analog Output dBc ?59 100 MHz to 150 MHz Analog Output ?56 dBc 150 MHz to 200 MHz Analog Output ?53 dBc NARROW-BAND SFDR 1.1 MHz Analog Output (±10 kHz) ?90 dBc 1.1 MHz Analog Output (±50 kHz) dBc ?88 1.1 MHz Analog Output (±250 kHz) dBc ?86 1.1 MHz Analog Output (±1 MHz) dBc ?85 15.1 MHz Analog Output (±10 kHz) ?90 dBc 15.1 MHz Analog Output (±50 kHz) ?87 dBc 15.1 MHz Analog Output (±250 kHz) dBc ?85 15.1 MHz Analog Output (±1 MHz) dBc ?83 40.1 MHz Analog Output (±10 kHz) dBc ?90 40.1 MHz Analog Output (±50 kHz) ?87 dBc 40.1 MHz Analog Output (±250 kHz) ?84 dBc 40.1 MHz Analog Output (±1 MHz) ?82 dBc 75.1 MHz Analog Output (±10 kHz) ?87 dBc Rev. C | Page 4 of 44 Data Sheet AD9959 Parameter Min Typ Max Unit Test Conditions/Comments 75.1 MHz Analog Output (±50 kHz) ?85 dBc 75.1 MHz Analog Output (±250 kHz) ?83 dBc 75.1 MHz Analog Output (±1 MHz) ?82 dBc 100.3 MHz Analog Output (±10 kHz) ?87 dBc 100.3 MHz Analog Output (±50 kHz) ?85 dBc 100.3 MHz Analog Output (±250 kHz) ?83 dBc 100.3 MHz Analog Output (±1 MHz) ?81 dBc 200.3 MHz Analog Output (±10 kHz) ?87 dBc 200.3 MHz Analog Output (±50 kHz) ?85 dBc 200.3 MHz Analog Output (±250 kHz) ?83 dBc 200.3 MHz Analog Output (±1 MHz) ?81 dBc PHASE NOISE CHARACTERISTICS Residual Phase Noise @ 15.1 MHz (f ) OUT @ 1 kHz Offset ?150 dBc/Hz @ 10 kHz Offset ?159 dBc/Hz @ 100 kHz Offset ?165 dBc/Hz @ 1 MHz Offset ?165 dBc/Hz Residual Phase Noise @ 40.1 MHz (fOUT) @ 1 kHz Offset ?142 dBc/Hz @ 10 kHz Offset ?151 dBc/Hz @ 100 kHz Offset ?160 dBc/Hz @ 1 MHz Offset ?162 dBc/Hz Residual Phase Noise @ 75.1 MHz (fOUT) @ 1 kHz Offset ?135 dBc/Hz @ 10 kHz Offset ?146 dBc/Hz @ 100 kHz Offset ?154 dBc/Hz @ 1 MHz Offset ?157 dBc/Hz Residual Phase Noise @ 100.3 MHz (fOUT) @ 1 kHz Offset ?134 dBc/Hz @ 10 kHz Offset ?144 dBc/Hz @ 100 kHz Offset ?152 dBc/Hz @ 1 MHz Offset ?154 dBc/Hz Residual Phase Noise @ 15.1 MHz (fOUT) with REFCLK Multiplier Enabled 5× @ 1 kHz Offset ?139 dBc/Hz @ 10 kHz Offset ?149 dBc/Hz @ 100 kHz Offset ?153 dBc/Hz @ 1 MHz Offset ?148 dBc/Hz Residual Phase Noise @ 40.1 MHz (f ) OUT with REFCLK Multiplier Enabled 5× @ 1 kHz Offset ?130 dBc/Hz @ 10 kHz Offset ?140 dBc/Hz @ 100 kHz Offset ?145 dBc/Hz @ 1 MHz Offset ?139 dBc/Hz Residual Phase Noise @ 75.1 MHz (f ) with REFCLK OUT Multiplier Enabled 5× @ 1 kHz Offset ?123 dBc/Hz @ 10 kHz Offset ?134 dBc/Hz @ 100 kHz Offset ?138 dBc/Hz @ 1 MHz Offset ?132 dBc/Hz Rev. C | Page 5 of 44 AD9959 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments Residual Phase Noise @ 100.3 MHz (fOUT) with REFCLK Multiplier Enabled 5× @ 1 kHz Offset ?120 dBc/Hz @ 10 kHz Offset ?130 dBc/Hz @ 100 kHz Offset ?135 dBc/Hz @ 1 MHz Offset ?129 dBc/Hz Residual Phase Noise @ 15.1 MHz (f ) OUT with REFCLK Multiplier Enabled 20× @ 1 kHz Offset ?127 dBc/Hz @ 10 kHz Offset ?136 dBc/Hz @ 100 kHz Offset ?139 dBc/Hz @ 1 MHz Offset ?138 dBc/Hz Residual Phase Noise @ 40.1 MHz (fOUT) with REFCLK Multiplier Enabled 20× @ 1 kHz Offset ?117 dBc/Hz @ 10 kHz Offset ?128 dBc/Hz @ 100 kHz Offset ?132 dBc/Hz @ 1 MHz Offset ?130 dBc/Hz Residual Phase Noise @ 75.1 MHz (fOUT) with REFCLK Multiplier Enabled 20× @ 1 kHz Offset ?110 dBc/Hz @ 10 kHz Offset ?121 dBc/Hz @ 100 kHz Offset ?125 dBc/Hz @ 1 MHz Offset ?123 dBc/Hz Residual Phase Noise @ 100.3 MHz (f ) with OUT REFCLK Multiplier Enabled 20× @ 1 kHz Offset ?107 dBc/Hz @ 10 kHz Offset ?119 dBc/Hz @ 100 kHz Offset ?121 dBc/Hz @ 1 MHz Offset ?119 dBc/Hz SERIAL PORT TIMING CHARACTERISTICS Maximum Frequency Serial Clock (SCLK) 200 MHz Minimum SCLK Pulse Width Low (tPWL) 1.6 ns Minimum SCLK Pulse Width High (t ) 2.2 ns PWH Minimum Data Setup Time (tDS) 2.2 ns Minimum Data Hold Time 0 ns CS 1.0 ns Minimum Setup Time (tPRE) Minimum Data Valid Time for Read Operation 12 ns MISCELLANEOUS TIMING CHARACTERISTICS MASTER_RESET Minimum Pulse Width 1 Min pulse width = 1 sync clock period I/O_UPDATE Minimum Pulse Width 1 Min pulse width = 1 sync clock period Minimum Setup Time (I/O_UPDATE to SYNC_CLK) 4.8 ns Rising edge to rising edge Minimum Hold Time (I/O_UPDATE to SYNC_CLK) 0 ns Rising edge to rising edge Minimum Setup Time (Profile Inputs to SYNC_CLK) 5.4 ns Minimum Hold Time (Profile Inputs to SYNC_CLK) 0 ns Minimum Setup Time (SDIO Inputs to SYNC_CLK) 2.5 ns Minimum Hold Time (SDIO Inputs to SYNC_CLK) 0 ns Propagation Time Between REF_CLK and SYNC_CLK 2.25 3.5 5.5 ns Profile Pin Toggle Rate 2 Sync clocks CMOS LOGIC INPUTS V 2.0 V IH V 0.8 V IL Logic 1 Current 3 12 μA Logic 0 Current ?12 μA Input Capacitance 2 pF Rev. C | Page 6 of 44 Data Sheet AD9959 Parameter Min Typ Max Unit Test Conditions/Comments CMOS LOGIC OUTPUTS 1 mA load V 2.7 V OH VOL 0.4 V POWER SUPPLY Total Power Dissipation—All Channels On, 540 635 mW Dominated by supply variation Single-Tone Mode Total Power Dissipation—All Channels On, 580 680 mW Dominated by supply variation with Sweep Accumulator Total Power Dissipation—Full Power-Down 13 mW IAVDD—All Channels On, Single-Tone Mode 155 180 mA I —All Channels On, Sweep Accumulator, REFCLK 160 185 mA AVDD Multiplier and 10-Bit Output Scalar Enabled I —All Channels On, Single-Tone Mode 105 125 mA DVDD IDVDD—All Channels On, Sweep Accumulator, REFCLK 125 145 mA Multiplier and 10-Bit Output Scalar Enabled I 40 mA I = read DVDD_I/O DVDD 30 mA IDVDD = write IAVDD Power-Down Mode 0.7 mA I Power-Down Mode 1.1 mA DVDD 2, 3 DATA LATENCY (PIPELINE DELAY) SINGLE-TONE MODE Frequency, Phase, and Amplitude Words to DAC 29 SYSCLK Output with Matched Latency Enabled s Frequency Word to DAC Output with Matched 29 SYSCLK Latency Disabled s Phase Offset Word to DAC Output with Matched 25 SYSCLK Latency Disabled s Amplitude Word to DAC Output with Matched 17 SYSCLK Latency Disabled s 3, 4 DATA LATENCY (PIPELINE DELAY) MODULATION MODE Frequency Word to DAC Output 34 SYSCLK s Phase Offset Word to DAC Output 29 SYSCLK s Amplitude Word to DAC Output 21 SYSCLK s 3, 4 DATA LATENCY (PIPELINE DELAY) LINEAR SWEEP MODE Frequency Rising/Falling Delta Tuning Word to DAC 41 SYSCLK Output s Phase Offset Rising/Falling Delta Tuning Word to 37 SYSCLK DAC Output s Amplitude Rising/Falling Delta Tuning Word to DAC 29 SYSCLK Output s 1 For the VCO frequency range of 160 MHz to 255 MHz, there is no guarantee of operation. 2 Data latency is referenced to I/O_UPDATE. 3 Data latency is fixed. 4 Data latency is referenced to a profile change. Rev. C | Page 7 of 44 AD9959 Data Sheet ABSOLUTE MAXIMUM RATINGS Stresses at or above those listed under Absolute Maximum Table 2. Ratings may cause permanent damage to the product. This is a Parameter Rating stress rating only; functional operation of the product at these Maximum Junction Temperature 150°C or any other conditions above those indicated in the operational DVDD_I/O (Pin 49) 4 V section of this specification is not implied. Operation beyond AVDD, DVDD 2 V the maximum operating conditions for extended periods may Digital Input Voltage (DVDD_I/O = 3.3 V) ?0.7 V to +4 V affect product reliability. Digital Output Current 5 mA Storage Temperature Range –65°C to +150°C Operating Temperature Range –40°C to +85°C ESD CAUTION Lead Temperature (10 sec Soldering) 300°C θJA 21°C/W θJC 2°C/W Rev. C | Page 8 of 44 Data Sheet AD9959 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SYNC_IN 1 PIN 1 42 P2 SYNC_OUT 2 INDICATOR 41 P1 MASTER_RESET 3 40 P0 PWR_DWN_CTL 4 39 AVDD AVDD 5 38 AGND AGND 6 37 AVDD AD9959 AVDD 7 36 CH1_IOUT TOP VIEW CH2_IOUT 8 35 CH1_IOUT CH2_IOUT 9 (Not to Scale) 34 AGND AGND 10 33 AVDD AVDD 11 32 AGND AGND 12 31 AVDD CH3_IOUT 13 30 CH0_IOUT 14 29 CH0_IOUT CH3_IOUT NC = NO CONNECT NOTES 1. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS AN ELECTRICAL CONNECTION AND MUST BE SOLDERED TO GROUND. 2. PIN 49 IS DVDD_I/O AND IS TIED TO 3.3V. Figure 3. Pin Configuration Table 3. Pin Function Descriptions 1 Pin No. Mnemonic I/O Description 1 SYNC_IN I Used to Synchronize Multiple AD9959 Devices. Connects to the SYNC_OUT pin of the master AD9959 device. 2 SYNC_OUT O Used to Synchronize Multiple AD9959 Devices. Connects to the SYNC_IN pin of the slave AD9959 devices. 3 MASTER_RESET I Active High Reset Pin. Asserting the MASTER_RESET pin forces the AD9959 internal registers to their default state, as described in the Register Maps and Bit Descriptions section. 4 PWR_DWN_CTL I External Power-Down Control. 5, 7, 11, 15, 19, 21, AVDD I Analog Power Supply Pins (1.8 V). 26, 31, 33, 37, 39 6, 10, 12, 16, 18, 20, AGND I Analog Ground Pins. 25, 28, 32, 34, 38 45, 55 DVDD I Digital Power Supply Pins (1.8 V). 44, 56 DGND I Digital Power Ground Pins. 8 CH2_IOUT O True DAC Output. Terminates into AVDD. 9 CH2_IOUT O Complementary DAC Output. Terminates into AVDD. 13 CH3_IOUT O True DAC Output. Terminates into AVDD. 14 CH3_IOUT O Complementary DAC Output. Terminates into AVDD. 17 DAC_RSET I Establishes the Reference Current for All DACs. A 1.91 k? resistor (nominal) is connected from Pin 17 to AGND. 22 REF_CLK I Complementary Reference Clock/Oscillator Input. When the REF_CLK is operated in single-ended mode, this pin should be decoupled to AVDD or AGND with a 0.1 μF capacitor. 23 REF_CLK I Reference Clock/Oscillator Input. When the REF_CLK is operated in single-ended mode, this is the input. See the Modes of Operation section for the reference clock configuration. Rev. C | Page 9 of 44 05246-003 AVDD 15 56 DGND AGND 16 55 DVDD DAC_RSET 17 54 SYNC_CLK AGND 18 53 SDIO_3 AVDD 19 52 SDIO_2 AGND 20 51 SDIO_1 AVDD 21 50 SDIO_0 REF_CLK 22 49 DVDD_I/O REF_CLK 23 48 SCLK CLK_MODE_SEL 24 47 CS AGND 25 46 I/O_UPDATE AVDD 26 45 DVDD LOOP_FILTER 27 44 DGND AGND 28 43 P3AD9959 Data Sheet 1 Pin No. Mnemonic I/O Description 24 CLK_MODE_SEL I Control Pin for the Oscillator Section. Caution: Do not drive this pin beyond 1.8 V. When high (1.8 V), the oscillator section is enabled to accept a crystal as the REF_CLK source. When low, the oscillator section is bypassed. 27 LOOP_FILTER I Connects to the external zero compensation network of the PLL loop filter. Typically, the network consists of a 0 ? resistor in series with a 680 pF capacitor tied to AVDD. 29 CH0_IOUT O Complementary DAC Output. Terminates into AVDD. 30 CH0_IOUT O True DAC Output. Terminates into AVDD. 35 CH1_IOUT O Complementary DAC Output. Terminates into AVDD. 36 CH1_IOUT O True DAC Output. Terminates into AVDD. 40 to 43 P0 to P3 I Data pins used for modulation (FSK, PSK, ASK), to start/stop the sweep accumulators or used to ramp up/ramp down the output amplitude. The data is synchronous to the SYNC_CLK (Pin 54). The data inputs must meet the setup and hold time requirements of the SYNC_CLK. The functionality of these pins is controlled by the profile pin configuration (PPC) bits (FR1[14:12]). 46 I/O_UPDATE I A rising edge transfers data from the serial I/O port buffer to active registers. I/O_UPDATE is synchronous to the SYNC_CLK (Pin 54). I/O_UPDATE must meet the setup and hold time requirements of the SYNC_CLK to guarantee a fixed pipeline delay of data to the DAC output; otherwise, a ±1 SYNC_CLK period of pipeline uncertainty exists. The minimum pulse width is one SYNC_CLK period. 47 CS I Active Low Chip Select. Allows multiple devices to share a common I/O bus (SPI). 48 SCLK I Serial Data Clock for I/O Operations. Data bits are written on the rising edge of SCLK and read on the falling edge of SCLK. 49 DVDD_I/O I 3.3 V Digital Power Supply for SPI Port and Digital I/O. 50 SDIO_0 I/O Data Pin SDIO_0 is dedicated to the serial port I/O only. 51, 52 SDIO_1, SDIO_2 I/O Data Pin SDIO_1 and Data Pin SDIO_2 can be used for the serial I/O port or used to initiate a ramp-up/ramp-down (RU/RD) of the DAC output amplitude. 53 SDIO_3 I/O Data Pin SDIO_3 can be used for the serial I/O port or to initiate a ramp-up/ramp-down (RU/RD) of the DAC output amplitude. In single-bit or 2-bit modes, SDIO_3 is used for SYNC_I/O. If the SYNC_I/O function is not used, tie to ground or Logic 0. Do not let SDIO_3 float in single-bit or 2-bit modes. 54 SYNC_CLK O The SYNC_CLK runs at one-fourth the system clock rate; it can be disabled. I/O_UPDATE or data (Pin 40 to Pin 43) is synchronous to the SYNC_CLK. To guarantee a fixed pipeline delay of data to DAC output, I/O_UPDATE or data (Pin 40 to Pin 43) must meet the setup and hold time requirements to the rising edge of SYNC_CLK; otherwise, a ±1 SYNC_CLK period of uncertainty occurs. 1 I = input, O = output. Rev. C | Page 10 of 44 Data Sheet AD9959 TYPICAL PERFORMANCE CHARACTERISTICS REF LVL DELTA 1 (T1) RBW 20kHz RF ATT 20dB DELTA 1 (T1) RBW 20kHz RF ATT 20dB 0dBm –69.47dB VBW 20kHz REF LVL –71.73dB VBW 20kHz 0dBm 4.50901804MHz SWT 1.6s UNIT dB 30.06012024MHz SWT 1.6s UNIT dB 0 0 A A 1 1 –10 –10 –20 –20 1AP 1AP –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 1 1 –80 –80 –90 –90 –100 –100 START 0Hz 25MHz/DIV STOP 250MHz START 0Hz 25MHz/DIV STOP 250MHz Figure 4. Wideband SFDR, f = 1.1 MHz, f = 500 MSPS Figure 7. Wideband SFDR, fOUT = 15.1 MHz, fCLK = 500 MSPS OUT CLK DELTA 1 (T1) RBW 20kHz RF ATT 20dB REF Lv] DELTA 1 (T1) RBW 20kHz RF ATT 20dB REF LVL –62.84dB VBW 20kHz 0dBm –60.13dB VBW 20kHz 0dBm 40.08016032MHz SWT 1.6s UNIT dB 75.15030060MHz SWT 1.6s UNIT dB 0 0 A 1 A 1 –10 –10 –20 –20 1AP 1AP –30 –30 –40 –40 –50 –50 –60 –60 1 1 –70 –70 –80 –80 –90 –90 –100 –100 START 0Hz 25MHz/DIV STOP 250Hz START 0Hz 25MHz/DIV STOP 250MHz Figure 5. Wideband SFDR, f = 40.1 MHz, f = 500 MSPS OUT CLK Figure 8. Wideband SFDR, f = 75.1 MHz, f = 500 MSPS OUT CLK DELTA 1 (T1) RBW 20kHz RF ATT 20dB REF LVL DELTA 1 (T1) RBW 20kHz RF ATT 20dB REF LVL –59.04dB VBW 20kHz 0dBm –53.84dB VBW 20kHz 0dBm 100.70140281MHz SWT 1.6s UNIT dB –101.20240481MHz SWT 1.6s UNIT dB 0 0 A 1 A 1 –10 –10 –20 –20 1AP 1AP –30 –30 –40 –40 –50 –50 –60 –60 1 1 –70 –70 –80 –80 –90 –90 –100 –100 START 0Hz 25MHz/DIV STOP 250MHz START 0Hz 25MHz/DIV STOP 250MHz Figure 6. Wideband SFDR, f = 100.3 MHz, f = 500 MSPS OUT CLK Figure 9. Wideband SFDR, fOUT = 200.3 MHz, fCLK = 500 MSPS Rev. C | Page 11 of 44 (dB) (dB) (dB) 05246-006 05246-005 05246-004 (dB) (dB) (dB) 05246-009 05246-008 05246-007AD9959 Data Sheet REF LVL DELTA 1 (T1) RBW 500Hz RF ATT 20dB REF LVL DELTA 1 (T1) RBW 500Hz RF ATT 20dB 0dBm –84.73dB VBW 500Hz 0dBm –84.86dB VBW 500Hz 254.50901604kHz SWT 20s UNIT dB –200.40080160kHz SWT 20s UNIT dB 0 0 1 A A 1 –10 –10 –20 –20 1AP 1AP –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 1 1 –90 –90 –100 –100 CENTER 1.1MHz 100kHz/DIV SPAN 1MHz CENTER 15.1MHz 100kHz/DIV SPAN 1MHz Figure 10. NBSFDR, ±1 MHz, f = 1.1 MHz, f = 500 MSPS OUT CLK Figure 13. NBSFDR, ±1 MHz, fOUT = 15.1 MHz, fCLK = 500 MSPS REF LVL DELTA 1 (T1) RBW 500Hz RF ATT 20dB REF LVL DELTA 1 (T1) RBW 500Hz RF ATT 20dB 0dBm –84.10dB VBW 500Hz 0dBm –86.03dB VBW 500Hz 120.24048096kHz SWT 20s UNIT dB 262.56513026kHz SWT 20s UNIT dB 0 0 1 A A 1 –10 –10 –20 –20 1AP 1AP –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 1 1 –90 –90 –100 –100 CENTER 40.1MHz 100kHz/DIV SPAN 1MHz CENTER 75.1MHz 100kHz/DIV SPAN 1MHz Figure 11. NBSFDR, ±1 MHz, fOUT = 40.1 MHz, fCLK = 500 MSPS Figure 14. NBSFDR, ±1 MHz, f = 75.1 MHz, f = 500 MSPS OUT CLK REF LVL DELTA 1 (T1) RBW 500Hz RF ATT 20dB REF LVL DELTA 1 (T1) RBW 500Hz RF ATT 20dB 0dBm –82.63dB VBW 500Hz 0dBm –83.72dB VBW 500Hz 400.80160321kHz SWT 20s UNIT dB –400.80160321kHz SWT 20s UNIT dB 0 0 A A 1 1 –10 –10 –20 –20 1AP 1AP –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 1 1 –90 –90 –100 –100 CENTER 100.3MHz 100kHz/DIV SPAN 1MHz CENTER 200.3MHz 100kHz/DIV SPAN 1MHz Figure 12. NBSFDR, ±1 MHz, fOUT = 100.3 MHz, fCLK = 500 MSPS Figure 15. NBSFDR, ±1 MHz, fOUT = 200. 3MHz, fCLK = 500 MSPS Rev. C | Page 12 of 44 (dB) (dB) (dB) 05246-012 05246-011 05246-010 (dB) (dB) (dB) 05246-014 05246-013 05246-015Data Sheet AD9959 –100 –60 –110 75.1MHz –65 SINGLE DAC POWER PLANE –120 –70 –130 100.3MHz –140 –75 –150 40.1MHz –80 SEPARATE DAC POWER PLANES –160 15.1MHz –170 –85 10 100 1k 10k 100k 1M 10M 25.3 50.3 75.3 100.3 125.3 150.3 175.3 200.3 FREQUENCY OF COUPLING SPUR (MHz) FREQUENCY OFFSET (Hz) Figure 16. Residual Phase Noise (SSB) with fOUT = 15.1 MHz, 40.1 MHz, Figure 19. Channel Isolation at 500 MSPS Operation; Conditions are Channel 75.1 MHz, 100.3 MHz; fCLK = 500 MHz with REFCLK Multiplier Bypassed of Interest Fixed at 110.3 MHz, the Other Channels Are Frequency Swept –70 600 4 CHANNELS ON –80 500 –90 3 CHANNELS ON –100 100.3MHz 400 –110 2 CHANNELS ON 75.1MHz –120 300 –130 1 CHANNEL ON 200 –140 40.1MHz –150 15.1MHz 100 –160 –170 0 10 100 1k 10k 100k 1M 10M 500 450 400 350 300 250 200 150 100 50 FREQUENCY OFFSET (Hz) REFERENCE CLOCK FREQUENCY (MHz) Figure 17. Residual Phase Noise (SSB) with fOUT = 15.1 MHz, 40.1 MHz, Figure 20. Power Dissipation vs. Reference Clock Frequency vs. Channel(s) 75.1 MHz, 100.3 MHz; fCLK = 500 MHz with REFCLK Multiplier = 5× Power On/Off –70 –45 –80 –50 –90 SFDR AVERAGED –100 100.3MHz –55 –110 75.1MHz –120 –60 –130 40.1MHz –65 –140 15.1MHz –150 –70 –160 –170 –75 10 100 1k 10k 100k 1M 10M 1.1 15.1 40.1 75.1 100.3 200.3 FREQUENCY OFFSET (Hz) f (MHz) OUT Figure 18. Residual Phase Noise (SSB) with f = 15.1 MHz, 40.1 MHz, OUT Figure 21. Averaged Channel SFDR vs. fOUT 75.1 MHz,100.3 MHz; f = 500 MHz with REFCLK Multiplier = 20× CLK Rev. C | Page 13 of 44 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) 05246-036 05246-035 05246-034 SFDR (dBc) TOTAL POWER DISSIPATION (mW) CHANNEL ISOLATION (dBc) 05246-045 05246-038 05246-037AD9959 Data Sheet APPLICATION CIRCUITS PULSE ANTENNA AD9959 RADIATING ELEMENTS FILTER FILTER CH0 FILTER FILTER CH1 FILTER FILTER CH2 CH3 FILTER FILTER LO REFCLK Figure 22. Phase Array Radar Using Precision Frequency/Phase Control from DDS in FMCW or Pulsed Radar Applications; DDS Provides Either Continuous Wave or Frequency Sweep AD8349 I BASEBAND AD8348 AD8347 AD8346 ADL5390 CH2 LO CH0 IMAGE RF OUTPUT FREQUENCY AD9959 CH1 REFCLK CH3 LO ±90 DEGREES Q BASEBAND Figure 23. Single-Sideband-Suppressed Carrier Upconversion AD9510, AD9511, ADF4106 ÷ CHARGE PHASE LOOP VCO PUMP COMPARATOR FILTER REFERENCE ÷ LPF REFCLK AD9959 Figure 24. DDS in PLL Locking to Reference Offering Distribution with Fine Frequency and Delay Adjust Tuning Rev. C | Page 14 of 44 05246-042 05249-039 05246-043Data Sheet AD9959 AD9510 CLOCK DISTRIBUTOR CLOCK WITH SOURCE DELAY EQUALIZATION REF_CLK AD9510 SYNCHRONIZATION DELAY EQUALIZATION SYNC_OUT SYNC_IN C1 DATA S1 A1 FPGA AD9959 (MASTER) SYNC_CLK C2 DATA S2 A2 FPGA AD9959 (SLAVE 1) SYNC_CLK CENTRAL C3 CONTROL DATA S3 A3 FPGA AD9959 (SLAVE 2) SYNC_CLK C4 DATA S4 A4 FPGA AD9959 (SLAVE 3) SYNC_CLK A_END Figure 25. Synchronizing Multiple Devices to Increase Channel Capacity Using the AD9510 as a Clock Distributor for the Reference and SYNC_CLK OPTICAL FIBER CHANNEL WITH MULTIPLE DISCRETE WAVELENGTHS WDM SPLITTER SOURCE WDM SIGNAL INPUTS CH0 AMP CH0 CH1 AMP CH1 ACOUSTIC OPTICAL AD9959 TUNABLE FILTER CH2 REFCLK AMP CH2 CH3 CH3 AMP OUTPUTS CH0 CH1 CH2 CH3 SELECTABLE WAVELENGTH FROM EACH CHANNEL VIA DDS TUNING AOTF Figure 26. DDS Providing Stimulus for Acoustic Optical Tunable Filter CH0 – ADCMP563 AD9959 CH1 REFCLK + Figure 27. Agile Clock Source with Duty Cycle Control Using the Phase Offset Value in DDS to Change the DC Voltage to the Comparator Rev. C | Page 15 of 44 05246-044 05246-041 05246-046AD9959 Data Sheet PROGRAMMABLE 1 TO 32 DIVIDER AND DELAY ADJUST CLOCK OUTPUT SELECTION(S) AD9515 LVPECL AD9514 LVDS AD9513 n CMOS AD9512 CH0 AD9515 LVPECL AD9514 LVDS n AD9513 CMOS CH1 IMAGE AD9512 AD9959 AD9515 LVPECL REFCLK CH2 AD9514 LVDS AD9513 n CMOS AD9512 CH3 IMAGE AD9515 LVPECL AD9514 LVDS AD9513 n CMOS AD9512 n = DEPENDENT ON PRODUCT SELECTION Figure 28. Clock Generation Circuit Using the AD9512/AD9513/AD9514/AD9515 Series of Clock Distribution Chips Rev. C | Page 16 of 44 05246-040Data Sheet AD9959 EQUIVALENT INPUT AND OUTPUT CIRCUITS DVDD_I/O = 3.3V INPUT OUTPUT AVOID OVERDRIVING DIGITAL INPUTS. FORWARD BIASING DIODES MAY COUPLE DIGITAL NOISE ON POWER PINS. Figure 29. CMOS Digital Inputs CHx_IOUT CHx_IOUT TERMINATE OUTPUTS INTO AVDD. DO NOT EXCEED VOLTAGE COMPLIANCE OF OUTPUTS. Figure 30. DAC Outputs AVDD Z Z 1.5k? 1.5k? REF_CLK REF_CLK AVDD AVDD AMP OSC OSC REF_CLK INPUTS ARE INTERNALLY BIASED AND NEED TO BE AC-COUPLED. OSC INPUTS ARE DC-COUPLED. REF_CLK Figure 31. REF_CLK/ Inputs Rev. C | Page 17 of 44 05246-032 05246-002 05246-033AD9959 Data Sheet THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER DDS CORE The AD9959 incorporates four 10-bit current output DACs. The AD9959 has four DDS cores, each consisting of a 32-bit The DAC converts a digital code (amplitude) into a discrete phase accumulator and phase-to-amplitude converter. Together, analog quantity. The DAC current outputs can be modeled as a these digital blocks generate a digital sine wave when the phase current source with high output impedance (typically 100 k?). accumulator is clocked and the phase increment value (frequency Unlike many DACs, these current outputs require termination tuning word) is greater than 0. The phase-to-amplitude converter into AVDD via a resistor or a center-tapped transformer for simultaneously translates phase information to amplitude expected current flow. information by a cos(θ) operation. Each DAC has complementary outputs that provide a combined The output frequency (f ) of each DDS channel is a function OUT full-scale output current (I + I ). The outputs always sink OUT OUT of the rollover rate of each phase accumulator. The exact relationship is given in the following equation: current, and their sum equals the full-scale current at any point in time. The full-scale current is controlled by means of an (FTW)(f ) S f = external resistor (RSET) and the scalable DAC current control OUT 32 2 bits discussed in the Modes of Operation section. The resistor, where: R , is connected between the DAC_RSET pin and analog SET fS is the system clock rate. ground (AGND). The full-scale current is inversely proportional 31 FTW is the frequency tuning word and is 0 ≤ FTW ≤ 2 . to the resistor value as follows: 32 2 represents the phase accumulator capacity. 18.91 R = SET Because all four channels share a common system clock, they I (max) OUT are inherently synchronized. The maximum full-scale output current of the combined DAC The DDS core architecture also supports the capability to phase outputs is 15 mA, but limiting the output to 10 mA provides offset the output signal, which is performed by the channel optimal spurious-free dynamic range (SFDR) performance. phase offset word (CPOW). The CPOW is a 14-bit register that The DAC output voltage compliance range is AVDD + 0.5 V to stores a phase offset value. This value is added to the output of AVDD ? 0.5 V. Voltages developed beyond this range may cause the phase accumulator to offset the current phase of the output excessive harmonic distortion. Proper attention should be paid signal. Each channel has its own phase offset word register. This to the load termination to keep the output voltage within its feature can be used for placing all channels in a known phase compliance range. Exceeding this range could potentially dam- relationship relative to one another. The exact value of phase age the DAC output circuitry. offset is given by the following equation: LPF CHx_IOUT POW 1:1 ? ? Φ = × 360 ° ? ? 14 2 ? ? DAC AVDD 50? CHx_IOUT Figure 32. Typical DAC Output Termination Configuration Rev. C | Page 18 of 44 05246-016Data Sheet AD9959 MODES OF OPERATION There are many combinations of modes (for example, single- POWER SUPPLIES tone, modulation, linear sweep) that the AD9959 can perform The AVDD and DVDD supply pins provide power to the DDS simultaneously. However, some modes require multiple data core and supporting analog circuitry. These pins connect to a pins, which can impose limitations. The following guidelines 1.8 V nominal power supply. can help determine if a specific combination of modes can be The DVDD_I/O pin connects to a 3.3 V nominal power supply. performed simultaneously by the AD9959. All digital inputs are 3.3 V logic except for the CLK_MODE_SEL CHANNEL CONSTRAINT GUIDELINES input. CLK_MODE_SEL (Pin 24) is an analog input and should be operated by 1.8 V logic. ? Single-tone mode, two-level modulation mode, and linear sweep mode can be enabled on any channel and in any SINGLE-TONE MODE combination at the same time. Single-tone mode is the default mode of operation after a master ? Any one or two channels in any combination can perform reset signal. In this mode, all four DDS channels share a common four-level modulation. The remaining channels can be in address location for the frequency tuning word (Register 0x04) single-tone mode. and phase offset word (Register 0x05). Channel enable bits are ? Any channel can perform eight-level modulation. The provided in combination with these shared addresses. As a three remaining channels can be in single-tone mode. result, the frequency tuning word and/or phase offset word can ? Any channel can perform 16-level direct modulation. The be independently programmed between channels (see the three remaining channels can be in single-tone mode. following Step 1 through Step 5). The channel enable bits do not ? The RU/RD function can be used on all four channels in require an I/O update to enable or disable a channel. single-tone mode. See the Output Amplitude Control See the Register Maps and Bit Descriptions section for a Mode section for the RU/RD function. description of the channel enable bits in the channel select ? When Profile Pin P2 and Profile Pin P3 are used for RU/RD, register (CSR, Register 0x00). The channel enable bits are any two channels can perform two-level modulation with enabled or disabled immediately after the CSR data byte is RU/RD or any two channels can perform linear frequency written. or phase sweep with RU/RD. The other two channels can be in single-tone mode. Address sharing enables channels to be written simultaneously, if desired. The default state enables all channel enable bits. ? When Profile Pin P3 is used for RU/RD, any channel can Therefore, the frequency tuning word and/or phase offset word be used in eight-level modulation with RU/RD. The other is common to all channels but written only once through the three channels can be in single-tone mode. serial I/O port. ? When the SDIO_1, SDIO_2, and SDIO_3 pins are used for RU/RD, any one or two channels, any three channels, or The following steps present a basic protocol to program a all four channels can perform two-level modulation with different frequency tuning word and/or phase offset word for RU/RD. Any channels not in the two-level modulation can each channel using the channel enable bits. be in single-tone mode. 1. Power up the DUT and issue a master reset. A master reset ? When the SDIO_1, SDIO_2, and SDIO_3 pins are used for places the part in single-tone mode and single-bit mode for RU/RD, any one or two channels can perform four-level serial programming operations (refer to the Serial I/O Modes modulation with RU/RD. Any channels not in four-level of Operation section). Frequency tuning words and phase modulation can be in single-tone mode. offset words default to 0 at this point. ? When the SDIO_1, SDIO_2, and SDIO_3 pins are used for 2. Enable only one channel enable bit (Register 0x00) and RU/RD, any channel can perform 16-level modulation with disable the other channel enable bits. RU/RD. The other three channels can be in single-tone mode. 3. Using the serial I/O port, program the desired frequency ? Amplitude modulation, linear amplitude sweep modes, tuning word (Register 0x04) and/or the phase offset word and the RU/RD function cannot operate simultaneously, (Register 0x05) for the enabled channel. but frequency and phase modulation can operate simulta- neously as the RU/RD function. 4. Repeat Step 2 and Step 3 for each channel. 5. Send an I/O update signal. After an I/O update, all channels should output their programmed frequency and/or phase offset value. Rev. C | Page 19 of 44 AD9959 Data Sheet Single-Tone Mode—Matched Pipeline Delay The charge pump current in the PLL defaults to 75 μA. This setting typically produces the best phase noise characteristics. In single-tone mode, the AD9959 offers matched pipeline delay Increasing the charge pump current may degrade phase noise, to the DAC input for all frequency, phase, and amplitude changes. but it decreases the lock time and changes the loop bandwidth. This avoids having to deal with different pipeline delays between the three input ports for such applications. The feature is enabled Enabling the on-chip oscillator for crystal operation is performed by asserting the matched pipe delays active bit found in the by driving CLK_MODE_SEL (Pin 24) to logic high (1.8 V channel function register (CFR, Register 0x03). This feature logic). With the on-chip oscillator enabled, connection of an is available in single-tone mode only. REF_CLK external crystal to the REF_CLK and inputs is made, producing a low frequency reference clock. The frequency of REFERENCE CLOCK MODES the crystal must be in the range of 20 MHz to 30 MHz. The AD9959 supports multiple reference clock configurations Table 4 summarizes the clock modes of operation. See Table 1 to generate the internal system clock. As an alternative to for more details. clocking the part directly with a high frequency clock source, the system clock can be generated using the internal, PLL-based Reference Clock Input Circuitry reference clock multiplier. An on-chip oscillator circuit is also The reference clock input circuitry has two modes of operation available for providing a low frequency reference signal by controlled by the logic state of Pin 24 (CLK_MODE_SEL). The connecting a crystal to the clock input pins. Enabling these first mode (logic low) configures as an input buffer. In this features allows the part to operate with a low frequency clock mode, the reference clock must be ac-coupled to the input due source and still provide a high update rate for the DDS and to internal dc biasing. This mode supports either differential DAC. However, using the clock multiplier changes the output or single-ended configurations. If single-ended mode is chosen, phase noise characteristics. For best phase noise performance, the complementary reference clock input (Pin 22) should be a clean, stable clock with a high slew is required (see Figure 17 decoupled to AVDD or AGND via a 0.1 μF capacitor. Figure 33 and Figure 18). to Figure 35 exemplify typical reference clock configurations for Enabling the PLL allows multiplication of the reference clock the AD9959. frequency from 4× to 20×, in integer steps. The PLL multiplica- 1:1 0.1μF REF_CLK BALUN tion value is represented by a 5-bit multiplier value. These bits PIN 23 50? REFCLK are located in Function Register 1 (FR1, Register 0x01), Bits[22:18] REF_CLK SOURCE PIN 22 (see the Register Maps and Bit Descriptions section). 0.1μF When FR1[22:18] is programmed with values ranging from Figure 33. Differential Coupling from Single-Ended Source 4 to 20 (decimal), the clock multiplier is enabled. The integer The reference clock inputs can also support an LVPECL or value in the register represents the multiplication factor. The system clock rate with the clock multiplier enabled is equal to PECL driver as the reference clock source. the reference clock rate multiplied by the multiplication factor. 0.1μF REF_CLK PIN 23 LVPECL/ If FR1[22:18] is programmed with a value less than 4 or greater TERMINATION PECL than 20, the clock multiplier is disabled and the multiplication DRIVER REF_CLK PIN 22 0.1μF factor is effectively 1. Figure 34. Differential Clock Source Hook-Up Whenever the PLL clock multiplier is enabled or the multiplica- tion value is changed, time should be allowed to lock the PLL The second mode of operation (Pin 24 = logic high = 1.8 V) (typically 1 ms). provides an internal oscillator for crystal operation. In this mode, both clock inputs are dc-coupled via the crystal leads Note that the output frequency of the PLL is restricted to a and are bypassed. The range of crystal frequencies supported is frequency range of 100 MHz to 500 MHz. However, there is a from 20 MHz to 30 MHz. Figure 35 shows the configuration VCO gain control bit that must be used appropriately. The VCO for using a crystal. gain control bit defines two ranges (low/high) of frequency output. The VCO gain control bit defaults to low (see Table 1 for details). Table 4. Clock Configuration CLK_MODE_SEL, Pin 24 FR1[22:18] PLL Divider Ratio = M Crystal Oscillator Enabled System Clock (f ) Min/Max Freq. Range (MHz) SYSCLK High = 1.8 V Logic 4 ≤ M ≤ 20 Yes f = f × M 100 < f < 500 SYSCLK OSC SYSCLK High = 1.8 V Logic M < 4 or M > 20 Yes fSYSCLK = fOSC 20 < fSYSCLK < 30 Low 4 ≤ M ≤ 20 No f = f × M 100 < f < 500 SYSCLK REFCLK SYSCLK Low M < 4 or M > 20 No f = f 0 < f < 500 SYSCLK REFCLK SYSCLK Rev. C | Page 20 of 44 05246-017 05246-018Data Sheet AD9959 When FR1[6] = 1 and the PWR_DWN_CTL input pin is high, 39pF REF_CLK the AD9959 is put into full power-down mode. In this mode, all PIN 23 25MHz functions are powered down. This includes the DAC and PLL, XTAL REF_CLK which take a significant amount of time to power up. When the PIN 22 39pF PLL is bypassed, the PLL is shut down to conserve power. When the PWR_DWN_CTL input pin is high, the individual Figure 35.Crystal Input Configuration power-down bits (CFR[7:6] and FR1[7]) are invalid (don’t care) and unused. When the PWR_DWN_CTL input pin is low, the SCALABLE DAC REFERENCE CURRENT CONTROL individual power-down bits control the power-down modes of MODE operation. RSET is common to all four DACs. As a result, the full-scale Note that the power-down signals are all designed such that currents are equal by default. The scalable DAC reference can Logic 1 indicates the low power mode and Logic 0 indicates the be used to set the full-scale current of each DAC independent powered-up mode. from one another. This is accomplished by using the register bits CFR[9:8]. Table 5 shows how each DAC can be individually MODULATION MODE scaled for independent channel control. This scaling provides The AD9959 can perform 2-/4-/8-/16-level modulation of for binary attenuation. frequency, phase, or amplitude. Modulation is achieved by applying data to the profile pins. Each channel can be program- Table 5. DAC Full-Scale Current Control med separately, but the ability to modulate multiple channels CFR[9:8] LSB Current State simultaneously is constrained by the limited number of profile 11 Full scale pins. For instance, 16-level modulation uses all four profile pins, 01 Half scale which inhibits modulation for three channels. 10 Quarter scale In addition, the AD9959 has the ability to ramp up or ramp 00 Eighth scale down the output amplitude before, during, or after a modulation POWER-DOWN FUNCTIONS (FSK, PSK only) sequence. This is performed by using the 10-bit The AD9959 supports an externally controlled power-down output scalar. If the RU/RD feature is desired, unused profile feature and the more common software programmable power- pins or unused SDIO_1/SDIO_2/SDIO_3 pins can be confi- down bits found in previous Analog Devices DDS products. gured to initiate the operation. See the Output Amplitude Control Mode section for more details of the RU/RD feature. The software control power-down allows the input clock circui- try, the DAC, and the digital logic (for each separate channel) to In modulation mode, each channel has its own set of control be individually powered down via unique control bits (CFR[7:6]). bits to determine the type (frequency, phase, or amplitude) These bits are not active when the externally controlled power- of modulation. Each channel has 16 profile (channel word) down pin (PWR_DWN_CTL) is high. When the input pin, registers for flexibility. Register 0x0A through Register 0x18 PWR_DWN_CTL, is high, the AD9959 enters a power-down are profile registers for modulation of frequency, phase, or mode based on the FR1[6] bit. When the PWR_DWN_CTL amplitude. Register 0x04, Register 0x05, and Register 0x06 input pin is low, the external power-down control is inactive. are dedicated registers for frequency, phase, and amplitude, respectively. These registers contain the first frequency, phase When FR1[6] = 0 and the PWR_DWN_CTL input pin is high, offset, and amplitude word. the AD9959 is put into a fast recovery power-down mode. In this mode, the digital logic and the DAC digital logic are powered Frequency modulation has 32-bit resolution, phase modulation is down. The DAC bias circuitry, PLL, oscillator, and clock input 14 bits, and amplitude is 10 bits. When modulating phase or circuitry are not powered down. amplitude, the word value must be MSB aligned in the profile (channel word) registers and the unused bits are don’t care bits. Rev. C | Page 21 of 44 05246-019AD9959 Data Sheet In modulation mode, the amplitude frequency phase (AFP) Because of the number of available channels and limited data select bits (CFR[23:22]) and modulation level bits (FR1[9:8]) pins, it is necessary to assign the profile pins and/or SDIO_1, are programmed to configure the modulation type and level SDIO_2, and SDIO_3 pins to a dedicated channel. This is con- (see Table 6 and Table 7). Note that the linear sweep enable bit trolled by the profile pin configuration (PPC) bits (FR1[14:12]). must be set to Logic 0 in direct modulation mode. Each of the following modulation descriptions incorporates data pin assignments. Table 6. Modulation Type Configuration Two-Level Modulation—No RU/RD AFP Select Linear Sweep Enable (CFR[23:22]) (CFR[14]) Description The modulation level bits (FR1[9:8]) are set to 00 (two-level). 00 X Modulation disabled The AFP select bits (CFR[23:22]) are set to the desired modulation 01 0 Amplitude modulation type. The RU/RD bits (FR1[11:10]) and the linear sweep enable 10 0 Frequency modulation bit (CFR[14]) are disabled. Table 9 displays how the profile pins 11 0 Phase modulation and channels are assigned. As shown in Table 9, only Profile Pin P0 can be used to modulate Table 7. Modulation Level Selection Channel 0. If frequency modulation is selected and Profile Pin Modulation Level (FR1[9:8]) Description P0 is Logic 0, Channel Frequency Tuning Word 0 (Register 00 Two-level modulation 0x04) is chosen; if Profile Pin P0 is Logic 1, Channel Word 1 01 Four-level modulation (Register 0x0A) is chosen. 10 Eight-level modulation 11 16-level modulation Four-Level Modulation—No RU/RD The modulation level bits are set to 01 (four-level). The AFP When modulating, the RU/RD function can be limited based select bits (CFR[23:22]) are set to the desired modulation type. on pins available for controlling the feature. The SDIO_x pins The RU/RD bits (FR1[11:10]) and the linear sweep enable bit are for RU/RD only, not for modulation. (CFR[14]) are disabled. Note that the other two channels not Table 8. RU/RD Profile Pin Assignments being used should have their AFP select bits set to 00 due to the Ramp-Up/Ramp-Down lack of profile pins. Table 10 displays how the profile pins and (RU/RD) (FR1[11:10]) Description channels are assigned to each other. 00 RU/RD disabled For the conditions in Table 10, the profile (channel word) 01 Only Profile Pin P2 and Profile Pin P3 register chosen is based on the 2-bit value presented to Profile available for RU/RD operation Pins [P0:P1] or Profile Pins [P2:P3]. 10 Only Profile Pin P3 available for RU/RD operation For example, if PPC = 010, [P0:P1] = 11, and [P2:P3] = 01, then 11 Only SDIO_1, SDIO_2, and SDIO_3 the contents of the Channel Word 3 register of Channel 0 are pins available for RU/RD operation; presented to the output of Channel 0 and the contents of the this forces the serial I/O to be used Channel Word 1 register of Channel 3 are presented to the only in 1-bit mode output of Channel 3. If the profile pins are used for RU/RD, Logic 0 is for ramp-up and Logic 1 is for ramp-down. Table 9. Profile Pin Channel Assignments Profile Pin Configuration (PPC) (FR1[14:12]) P0 P1 P2 P3 Description XXX CH0 CH1 CH2 CH3 Two-level modulation, all channels, no RU/RD Table 10. Profile Pin and Channel Assignments Profile Pin Configuration (PPC) (FR1[14:12]) P0 P1 P2 P3 Description 000 CH0 CH0 CH1 CH1 Four-level modulation on CH0 and CH1, no RU/RD 001 CH0 CH0 CH2 CH2 Four-level modulation on CH0 and CH2, no RU/RD 010 CH0 CH0 CH3 CH3 Four-level modulation on CH0 and CH3, no RU/RD 011 CH1 CH1 CH2 CH2 Four-level modulation on CH1 and CH2, no RU/RD 100 CH1 CH1 CH3 CH3 Four-level modulation on CH1 and CH3, no RU/RD 101 CH2 CH2 CH3 CH3 Four-level modulation on CH2 and CH3, no RU/RD Rev. C | Page 22 of 44 Data Sheet AD9959 Eight-Level Modulation—No RU/RD For the conditions in Table 12, the profile register chosen is based on the 4-bit value presented to Profile Pins [P0:P3]. The modulation level bits (FR1[9:8]) are set to 10 (eight-level). For example, if PPC = X11 and [P0:P3] = 1110, the contents of The AFP select bits (CFR[23:22]) are set to a nonzero value. the Channel Word 14 register of Channel 3 is presented to the The RU/RD bits (FR1[11:10]) and the linear sweep enable bit output of Channel 3. (CFR[14]) are disabled. Note that the AFP select bits of the three channels not being used must be set to 00. Table 11 shows Two-Level Modulation Using Profile Pins for RU/RD the assignment of profile pins and channels. When the RU/RD bits = 01, Profile Pin P2 and Profile Pin P3 For the condition in Table 11, the choice of channel word registers are available for RU/RD. Note that only a modulation level of is based on the 3-bit value presented to Profile Pins [P0:P2]. For two is available in this mode. See Table 13 for available pin example, if PPC = X10 and [P0:P2] = 111, the contents of the assignments. Channel Word 7 register of Channel 2 are presented to the output Eight-Level Modulation Using a Profile Pin for RU/RD of Channel 2. When the RU/RD bits = 10, Profile Pin P3 is available for RU/RD. 16-Level Modulation—No RU/RD Note that only a modulation level of eight is available in this The modulation level bits (FR1[9:8]) are set to 11 (16-level). The mode. See Table 14 for available pin assignments. AFP select bits (CFR[23:22]) are set to the desired modulation type. The RU/RD bits (FR1[11:10]) and the linear sweep enable bit (CFR[14]) are disabled. The AFP select bits of the three channels not being used must be set to 00. Table 12 displays how the profile pins and channels are assigned. Table 11. Profile Pin and Channel Assignments for Eight-Level Modulation (No RU/RD) Profile Pin Config. (PPC) (FR1[14:12]) P0 P1 P2 P3 Description X00 CH0 CH0 CH0 X Eight-level modulation on CH0, no RU/RD X01 CH1 CH1 CH1 X Eight-level modulation on CH1, no RU/RD X10 CH2 CH2 CH2 X Eight-level modulation on CH2, no RU/RD X11 CH3 CH3 CH3 X Eight-level modulation on CH3, no RU/RD Table 12. Profile Pin and Channel Assignments for 16-Level Modulation (No RU/RD) Profile Pin Config. (PPC) (FR1[14:12]) P0 P1 P2 P3 Description X00 CH0 CH0 CH0 CH0 16-level modulation on CH0, no RU/RD X01 CH1 CH1 CH1 CH1 16-level modulation on CH1, no RU/RD X10 CH2 CH2 CH2 CH2 16-level modulation on CH2, no RU/RD X11 CH3 CH3 CH3 CH3 16-level modulation on CH3, no RU/RD Table 13. Profile Pin and Channel Assignments for Two-Level Modulation (RU/RD Enabled) Profile Pin Config. (PPC) (FR1[14:12]) P0 P1 P2 P3 Description 000 CH0 CH1 CH0 RU/RD CH1 RU/RD Two-level modulation on CH0 and CH1 with RU/RD 001 CH0 CH2 CH0 RU/RD CH2 RU/RD Two-level modulation on CH0 and CH2 with RU/RD 010 CH0 CH3 CH0 RU/RD CH3 RU/RD Two-level modulation on CH0 and CH3 with RU/RD 011 CH1 CH2 CH1 RU/RD CH2 RU/RD Two-level modulation on CH1 and CH2 with RU/RD 100 CH1 CH3 CH1 RU/RD CH3 RU/RD Two-level modulation on CH1 and CH3 with RU/RD 101 CH2 CH3 CH2 RU/RD CH3 RU/RD Two-level modulation on CH2 and CH3 with RU/RD Table 14. Profile Pin and Channel Assignments for Eight-Level Modulation (RU/RD Enabled) Profile Pin Config. (PPC) (FR1[14:12]) P0 P1 P2 P3 Description X00 CH0 CH0 CH0 CH0 RU/RD Eight-level modulation on CH0 with RU/RD X01 CH1 CH1 CH1 CH1 RU/RD Eight-level modulation on CH1 with RU/RD X10 CH2 CH2 CH2 CH2 RU/RD Eight-level modulation on CH2 with RU/RD X11 CH3 CH3 CH3 CH3 RU/RD Eight-level modulation on CH3 with RU/RD Rev. C | Page 23 of 44 AD9959 Data Sheet For the configuration shown in Table 17, the profile (channel MODULATION USING SDIO_x PINS FOR RU/RD word) register is chosen based on the 2-bit value presented to For RU/RD bits = 11, the SDIO_1, SDIO_2, and SDIO_3 pins Profile Pins [P1:P2] or [P3:P4]. are available for RU/RD. In this mode, modulation levels of 2, 4, and 16 are available. Note that the serial I/O port can be used only For example, if PPC = 011, [P0:P1] = 11, and [P2:P3] = 01, in 1-bit serial mode. the contents of the Channel Word 3 register of Channel 1 are presented to the output of Channel 1, and the contents of the Two-Level Modulation Using SDIO Pins for RU/RD Channel Word 1 register of Channel 2 are presented to the Table 15. Profile Pin and Channel Assignments in Two-Level output of Channel 2. SDIO_1 and SDIO_2 provide the RU/RD Modulation (RU/RD Enabled) function. Profile Pin Config. (PPC) 16-Level Modulation Using SDIO Pins for RU/RD (FR1[14:12]) P0 P1 P2 P3 The RU/RD bits = 11 (the SDIO_1 pin is available for RU/RD), XXX CH0 CH1 CH2 CH3 and the level is set to 16. See the pin assignments shown in For the configuration in Table 15, each profile pin is dedicated Table 18. to a specific channel. In this case, the SDIO_x pins can be used For the configuration shown in Table 18, the profile (channel for the RU/RD function, as described in Table 16. word) register is chosen based on the 4-bit value presented to Four-Level Modulation Using SDIO Pins for RU/RD Profile Pins [P0:P3]. For example, if PPC = X10 and [P0:P3] = For RU/RD bits = 11 (the SDIO_1 and SDIO_2 pins are avail- 1101, then the contents of the Channel Word 13 register of able for RU/RD), the modulation level is set to 4. See Table 17 Channel 2 is presented to the output of Channel 2. The SDIO_1 for pin assignments, including SDIO_x pin assignments. pin provides the RU/RD function. Table 16. Channel and SDIO_1/SDIO_2/SDIO_3 Pin Assignments for RU/RD Operation SDIO_1 SDIO_2 SDIO_3 Description 0 0 0 Triggers the ramp-up function for CH0 0 0 1 Triggers the ramp-down function for CH0 0 1 0 Triggers the ramp-up function for CH1 0 1 1 Triggers the ramp-down function for CH1 1 0 0 Triggers the ramp-up function for CH2 1 0 1 Triggers the ramp-down function for CH2 1 1 0 Triggers the ramp-up function for CH3 1 1 1 Triggers the ramp-down function for CH3 Table 17. Channel and Profile Pin Assignments, Including SDIO_1/SDIO_2/SDIO_3 Pin Assignments for RU/RD Operation Profile Pin Configuration (PPC) (FR1[14:12]) P0 P1 P2 P3 SDIO_1 SDIO_2 SDIO_3 000 CH0 CH0 CH1 CH1 CH0 RU/RD CH1 RU/RD N/A 001 CH0 CH0 CH2 CH2 CH0 RU/RD CH2 RU/RD N/A 010 CH0 CH0 CH3 CH3 CH0 RU/RD CH3 RU/RD N/A 011 CH1 CH1 CH2 CH2 CH1 RU/RD CH2 RU/RD N/A 100 CH1 CH1 CH3 CH3 CH1 RU/RD CH3 RU/RD N/A 101 CH2 CH2 CH3 CH3 CH2 RU/RD CH3 RU/RD N/A Table 18. Channel and Profile Pin Assignments, Including SDIO_1 Pin Assignments for RU/RD Operation Profile Pin Configuration (PPC) (FR1[14:12]) P0 P1 P2 P3 SDIO_1 SDIO_2 SDIO_3 X00 CH0 CH0 CH0 CH0 CH0 RU/RD N/A N/A X01 CH1 CH1 CH1 CH1 CH1 RU/RD N/A N/A X10 CH2 CH2 CH2 CH2 CH2 RU/RD N/A N/A X11 CH3 CH3 CH3 CH3 CH3 RU/RD N/A N/A Rev. C | Page 24 of 44 Data Sheet AD9959 LINEAR SWEEP MODE Setting the Slope of the Linear Sweep Linear sweep mode enables the user to sweep frequency, phase, The slope of the linear sweep is set by the intermediate step size or amplitude from a starting point (S0) to an endpoint (E0). (delta-tuning word) between S0 and E0 and the time spent The purpose of linear sweep mode is to provide better band- (sweep ramp rate word) at each step. The resolution of the width containment compared to direct modulation by replacing delta-tuning word is 32 bits for frequency, 14 bits for phase, and greater instantaneous changes with more gradual, user-defined 10 bits for amplitude. The resolution for the delta ramp rate changes between S0 and E0. word is eight bits. In linear sweep mode, S0 is loaded into the Channel Word 0 In linear sweep, each channel is assigned a rising delta word register (S0 is represented by one of three registers: Register 0x04, (RDW, Register 0x08) and a rising sweep ramp rate word Register 0x05, or Register 0x06, depending on the type of sweep) (RSRR, Register 0x07). These settings apply when sweeping up and E0 is always loaded into Channel Word 1 (Register 0x0A). toward E0. The falling delta word (FDW, Register 0x09) and If E0 is configured for frequency sweep, the resolution is 32 bits, falling sweep ramp rate (FSRR, Register 0x07) apply when phase sweep is 14 bits, and amplitude sweep is 10 bits. When sweeping down toward S0. Figure 36 displays a linear sweep up sweeping phase or amplitude, the word value must be MSB aligned and then down using a profile pin. Note that the linear sweep in the Channel Word 1 register. The unused bits are don’t care no-dwell bit is disabled; otherwise, the sweep accumulator bits. The profile pins are used to trigger and control the direction returns to 0 upon reaching E0. of the linear sweep for frequency, phase, and amplitude. All E0 channels can be programmed separately for a linear sweep. In linear sweep mode, Profile Pin P0 is dedicated to Channel 0. RDW FDW Profile Pin P1 is dedicated to Channel 1, and so on. ?f,p,a ?f,p,a The AD9959 has the ability to ramp up or ramp down (RU/RD) the output amplitude (using the 10-bit output scalar) before and RSRR FSRR after a linear sweep. If the RU/RD feature is desired, unused profile pins or unused SDIO_1/SDIO_2/SDIO_3 pins can be ?t ?t configured for the RU/RD operation. S0 PROFILE PIN To enable linear sweep mode for a particular channel, the AFP select bits (CFR[23:22]), the modulation level bits (FR1[9:8]), TIME and the linear sweep enable bit (CFR[14]) are programmed. Figure 36. Linear Sweep Parameters The AFP select bits determine the type of linear sweep to be For a piecemeal or a nonlinear transition between S0 and E0, performed. The modulation level bits must be set to 00 (two- the delta-tuning words and ramp rate words can be repro- level) for that specific channel (see Table 19 and Table 20) grammed during the transition to produce the desired response. Table 19. Linear Sweep Parameter to Sweep The formulas for calculating the step size of RDW or FDW for AFP Select Linear Sweep Enable delta frequency, delta phase, or delta amplitude are as follows: (CFR[23:22]) (CFR[14]) Description RDW ? ? 00 1 N/A ?f ? ?SYSCLK (Hz) ? ? 32 ? 2 ? 01 1 Amplitude sweep 10 1 Frequency sweep RDW ? ? ΔΦ ? ? 360 ? ? ? 14 11 1 Phase sweep 2 ? ? RDW Table 20. Modulation Level Assignments ? ? ?a ? ? 1024 (DAC full-scale current) ? ? 10 2 Modulation Level (FR1[9:8]) Description ? ? 00 (Required in Linear Sweep) Two-level modulation The formula for calculating delta time from RSRR or FSRR is 01 Four-level modulation t ? ?RSRR ? ?1/SYNC _CLK 10 Eight-level modulation 11 16-level modulation At 500 MSPS operation (SYNC_CLK = 125 MHz), the maxi- mum time interval between steps is 1/125 MHz × 256 = 2.048 μs. The minimum time interval is (1/125 MHz) × 1 = 8.0 ns. The sweep ramp rate block (timer) consists of a loadable 8-bit down counter that continuously counts down from the loaded value to 1. When the ramp rate timer equals 1, the proper ramp rate value is loaded and the counter begins counting down to 1 again. Rev. C | Page 25 of 44 (FREQUENCY/PHASE/AMPLITUDE) LINEAR SWEEP 05246-020AD9959 Data Sheet This load and countdown operation continues for as long as the When the profile pin transitions from high to low, the FDW is timer is enabled. However, the count can be reloaded before applied to the input of the sweep accumulator and the FSRR bits reaching 1 by either of the following two methods: are loaded into the sweep rate timer. ? Method 1 is to change the profile pin. When the profile pin The FDW accumulates at the rate given by the falling sweep ramp changes from Logic 0 to Logic 1, the rising sweep ramp rate rate (FSRR) until the output is equal to the CFTW0 register (Register 0x04) value. The sweep is then complete, and the output (RSRR) register value is loaded into the ramp rate timer, is held constant in frequency. which then proceeds to count down as normal. When the profile pin changes from Logic 1 to Logic 0, the falling sweep See Figure 37 for the linear sweep block diagram. Figure 39 ramp rate (FSRR) register value is loaded into the ramp depicts a frequency sweep with no-dwell mode disabled. In this rate timer, which then proceeds to count down as normal. mode, the output follows the state of the profile pin. A phase or ? Method 2 is to set the CFR[14] bit and issue an I/O update. amplitude sweep works in the same manner. If sweep is enabled and CFR[14] is set, the ramp rate timer LINEAR SWEEP NO-DWELL MODE loads the value determined by the profile pin. If the profile If the linear sweep no-dwell bit is set (CFR[15]), the rising sweep is pin is high, the ramp rate timer loads the RSRR; if the profile started in an identical manner to the dwell linear sweep mode; pin is low, the ramp rate timer loads FSRR. that is, upon detecting Logic 1 on the profile input pin, the rising Frequency Linear Sweep Example: AFP Bits = 10 sweep action is initiated. The word continues to sweep up at the In the following example, the modulation level bits (FR1[9:8]) = 00, rate set by the rising sweep ramp rate at the resolution set by the the linear sweep enable bit (CFR[14]) = 1, and the linear sweep rising delta word until it reaches the terminal value. Upon reaching no-dwell bit (CFR[15]) = 0. the terminal value, the output immediately reverts to the starting point and remains until Logic 1 is detected on the profile pin. In linear sweep mode, when the profile pin transitions from low to high, the RDW is applied to the input of the sweep accumulator Figure 38 shows an example of the no-dwell mode. The points and the RSRR register is loaded into the sweep rate timer. labeled A indicate where a rising edge is detected on the profile pin, and the points labeled B indicate where the AD9959 has The RDW accumulates at the rate given by the rising sweep determined that the output has reached E0 and reverts to S0. ramp rate (RSRR) bits until the output is equal to the CW1 The falling sweep ramp rate bits (LSRR[15:8]) and the falling register value. The sweep is then complete, and the output is delta word bits (FDW[31:0]) are unused in this mode. held constant in frequency. SWEEP ACCUMULATOR SWEEP ADDER 0 0 32 32 32 32 –1 MUX Z 0 FDW 0 32 MUX 0 1 MUX MUX 0 1 RDW 1 1 32 PROFILE PIN CFTW0 RAMP RATE TIMER: 8-BIT LOADABLE DOWN COUNTER ACCUMULATOR RESET LIMIT LOGICTO LOGIC KEEP SWEEP BETWEEN 8 32 S0 AND E0 PROFILE PIN CW1 MUX 0 1 RATE TIME LOAD CONTROL FSRR RSRR LOGIC Figure 37. Linear Sweep Block Diagram (Frequency Sweep) Rev. C | Page 26 of 44 05246-021Data Sheet AD9959 f OUT BB B FTW1 AA A FTW0 TIME SINGLE-TONE MODE P0 = 0 P0 = 1 P0 = 0 P0 = 1 P0 = 0 P0 = 1 LINEAR SWEEP MODE ENABLE—NO-DWELL BIT SET Figure 38. Linear Sweep Mode (No-Dwell Enabled) f OUT B FTW1 A FTW0 TIME SINGLE-TONE LINEAR SWEEP MODE MODE P0 = 0 P0 = 1 P0 = 0 AT POINT A: LOAD RISING RAMP RATE REGISTER, APPLY RDW<31:0> AT POINT B: LOAD FALLING RAMP RATE REGISTER, APPLY FDW<31:0> Figure 39. Linear Sweep Mode (No-Dwell Disabled) Continuous Clear Bits SWEEP AND PHASE ACCUMULATOR CLEARING FUNCTIONS The continuous clear bits are static control signals that, when active high, hold the respective accumulator at 0 while the bit is The AD9959 allows two different clearing functions. The first active. When the bit goes low, the respective accumulator is is a continuous zeroing of the sweep logic and phase accumula- allowed to operate. tor (clear and hold). The second is a clear and release or automatic zeroing function. CFR[4] is the autoclear sweep accumulator bit Clear and Release Bits and CFR[2] is the autoclear phase accumulator bit. The continuous The autoclear sweep accumulator bit, when set, clears and clear bits are located in CFR, where CFR[3] clears the sweep releases the sweep accumulator upon an I/O update or a change accumulator and CFR[1] clears the phase accumulator. in the profile input pins. The autoclear phase accumulator bit, when set, clears and releases the phase accumulator upon an I/O update or a change in the profile pins. The automatic clearing function is repeated for every subsequent I/O update or change in profile pins until the clear and release bits are reset via the serial port. Rev. C | Page 27 of 44 05246-048 05246-047AD9959 Data Sheet OUTPUT AMPLITUDE CONTROL MODE A special feature of this mode is that the maximum output amplitude allowed is limited by the contents of the amplitude The 10-bit scale factor (multiplier) controls the ramp-up and scale factor (ACR[9:0]). This allows the user to ramp to a value ramp-down (RU/RD) time of an on/off emission from the DAC. In burst transmissions of digital data, it reduces the adverse less than full scale. spectral impact of abrupt bursts of data. The multiplier can Ramp Rate Timer be bypassed by clearing the amplitude multiplier enable bit The ramp rate timer is a loadable down counter that generates (ACR[12] = 0). the clock signal to the 10-bit counter that generates the internal Automatic and manual RU/RD modes are supported. The auto- scale factor. The ramp rate timer is loaded with the value of the matic mode generates a zero-scale up to a full-scale (10 bits) LSRR (Register 0x07) each time the counter reaches 1 (decimal). linear ramp at a rate determined by ACR (Register 0x06). The This load and countdown operation continues for as long as the start and direction of the ramp can be controlled by either the timer is enabled unless the timer is forced to load before profile pins or the SDIO_1/SDIO_2/SDIO_3 pins. reaching a count of 1. Manual mode allows the user to directly control the output If the load ARR at I/O_UPDATE bit (ACR[10]) is set, the ramp amplitude by manually writing to the amplitude scale factor rate timer is loaded at an I/O update, a change in profile input, value in the ACR (Register 0x06). Manual mode is enabled by or upon reaching a value of 1. The ramp timer can be loaded setting ACR[12] = 1 and ACR[11] = 0. before reaching a count of 1 by three methods. Automatic RU/RD Mode Operation ? In the first method, the profile pins or the SDIO_1/ Automatic RU/RD mode is active when both ACR[12] and SDIO_2/SDIO_3 pins are changed. When the control ACR[11] are set. When automatic RU/RD is enabled, the scale signal changes state, the ACR value is loaded into the ramp factor is internally generated and applied to the multiplier input rate timer, which then proceeds to count down as normal. port for scaling the output. The scale factor is the output of a 10-bit ? In the second method, the load ARR at I/O_UPDATE bit counter that increments/decrements at a rate set by the 8-bit (ACR[10]) is set, and an I/O update is issued. output ramp rate register. The scale factor increments if the ? The third method is to change from inactive automatic external pin is high and decrements if the pin is low. The inter- RU/RD mode to active automatic RU/RD mode. nally generated scale factor step size is controlled by ACR[15:14]. RU/RD Pin-to-Channel Assignment Table 21 describes the increment/decrement step size of the internally generated scale factor per ACR[15:14]. When all four channels are in single-tone mode, the profile pins are used for RU/RD operation. Table 21. Increment/Decrement Step Size Assignments When linear sweep and RU/RD are activated, the SDIO_1/ Increment/Decrement Step Size SDIO_2/SDIO_3 pins are used for RU/RD operation. (ACR [15:14]) Size 00 1 In modulation mode, refer to the Modulation Mode section for pin assignments. 01 2 10 4 Table 22. Profile Pin Assignments for RU/RD Operation 11 8 Profile Pin RU/RD Operation P0 CH0 P1 CH1 P2 CH2 P3 CH3 Table 23. Channel Assignments of SDIO_1/SDIO_2/SDIO_3 Pins for RU/RD Operation Linear Sweep and RU/RD Modes Enabled Simultaneously SDIO_1 SDIO_2 SDIO_3 Ramp-Up/Ramp-Down Control Signal Assignment Enable for CH0 0 0 0 Ramp-up function for CH0 Enable for CH0 0 0 1 Ramp-down function for CH0 Enable for CH1 0 1 0 Ramp-up function for CH1 Enable for CH1 0 1 1 Ramp-down function for CH1 Enable for CH2 1 0 0 Ramp-up function for CH2 Enable for CH2 1 0 1 Ramp-down function for CH2 Enable for CH3 1 1 0 Ramp-up function for CH3 Enable for CH3 1 1 1 Ramp-down function for CH3 Rev. C | Page 28 of 44 Data Sheet AD9959 SYNCHRONIZING MULTIPLE AD9959 DEVICES The AD9959 allows easy synchronization of multiple AD9959 Table 24. System Clock Offset (Delay) Assignments devices. At power-up, the phase of SYNC_CLK can be offset System Clock SYNC_OUT/SYNC_IN between multiple devices. To correct for the offset and align the Offset (FR2[1:0]) Propagation Delay SYNC_CLK edges, there are three methods (one automatic mode 00 0 ≤ delay ≤ 1 and two manual modes) of synchronizing the SYNC_CLK edges. 01 1 ≤ delay ≤ 2 These modes force the internal state machines of multiple 10 2 ≤ delay ≤ 3 devices to a known state, which aligns the SYNC_CLK edges. 11 3 ≤ delay ≤ 4 In addition, the user must send a coincident I/O_UPDATE to Automatic Synchronization Status Bits multiple devices to maintain synchronization. Any mismatch in If a slave device falls out of sync, the sync status bit is set high. REF_CLK phase between devices results in a corresponding The multidevice sync status bit (FR2[5]) can be read through phase mismatch on the SYNC_CLK edges. the serial port. It is automatically cleared when read. AUTOMATIC MODE SYNCHRONIZATION The synchronization routine continues to operate regardless of In automatic mode, multiple part synchronization is achieved the state of FR2[5]. FR2[5] can be masked by writing Logic 1 to by connecting the SYNC_OUT pin on the master device to the the multidevice sync mask bit (FR2[4]). If FR2[5] is masked, it is SYNC_IN pins of the slave devices. Devices are configured as held low. master or slave through programming bits, accessible via the MANUAL SOFTWARE MODE SYNCHRONIZATION serial port. Manual software mode is enabled by setting the manual software A configuration for synchronizing multiple AD9959 devices in sync bit (FR1[0]) to Logic 1 in a device. In this mode, the I/O automatic mode is shown in the Application Circuits section. In update that writes the manual software sync bit to Logic 0 stalls this configuration, the AD9510 provides coincident REF_CLK the state machine of the clock generator for one system clock and SYNC_OUT signals to all devices. cycle. Stalling the clock generation state machine by one cycle Operation changes the phase relationship of SYNC_CLK between devices by one system clock period (90°). The first steps are to program the master and slave devices for their respective roles and then write the auto sync enable bit Note that the user may have to repeat this process until the (FR2[7]) = 1. Enabling the master device is performed by writing devices have their SYNC_CLK signals in phase. The SYNC_IN its multidevice sync master enable bit in Function Register 2 input can be left floating because it has an internal pull-up. The (FR2[6]) = 1. This causes the SYNC_OUT of the master device SYNC_OUT pin is not used. to output a pulse that has a pulse width equal to one system The synchronization is complete when the master and slave clock period and a frequency equal to one-fourth of the system devices have their SYNC_CLK signals in phase. clock frequency. Enabling devices as slaves is performed by writing FR2[6] = 0. MANUAL HARDWARE MODE SYNCHRONIZATION In automatic synchronizing mode, the slave devices sample Manual hardware mode is enabled by setting the manual hardware sync bit (FR1[1]) to Logic 1 in a device. In manual hardware SYNC_OUT pulses from the master device on the SYNC_IN synchronization mode, the SYNC_CLK stalls by one system of the slave devices, and a comparison of all state machines is clock cycle each time a rising edge is detected on the SYNC_IN made by the autosynchronization circuitry. If the slave devices input. Stalling the SYNC_CLK state machine by one cycle changes state machines are not identical to the master, the slave devices state machines are stalled for one system clock cycle. This proce- the phase relationship of SYNC_CLK between devices by one dure synchronizes the slave devices within three SYNC_CLK system clock period (90°). periods. Note that the user may have to repeat the process until the Delay Time Between SYNC_OUT and SYNC_IN devices have their SYNC_CLK signals in phase. The SYNC_IN input can be left floating because it has an internal pull-up. The When the delay between SYNC_OUT and SYNC_IN exceeds SYNC_OUT is not used. one system clock period, the system clock offset bits (FR2[1:0]) are used to compensate. The default state of these bits is 00, which The synchronization is complete when the master and slave implies that the SYNC_OUT of the master and the SYNC_IN of devices have their SYNC_CLK signals in phase. the slave have a propagation delay of less than one system clock period. If the propagation time is greater than one system clock period, the time should be measured and the appropriate offset programmed. Table 24 describes the delays required per system clock offset value. Rev. C | Page 29 of 44 AD9959 Data Sheet If the setup time between these signals is met, then constant I/O_UPDATE, SYNC_CLK, AND SYSTEM CLOCK latency (pipeline) to the DAC output exists. For example, if RELATIONSHIPS repetitive changes to phase offset via the SPI port is desired, the I/O_UPDATE and SYNC_CLK are used together to transfer latency of those changes to the DAC output is constant; otherwise, data from the serial I/O buffer to the active registers in the a time uncertainty of one SYNC_CLK period is present. device. Data in the buffer is inactive. The I/O_UPDATE is essentially oversampled by the SYNC_CLK. SYNC_CLK is a rising edge active signal. It is derived from Therefore, I/O_UPDATE must have a minimum pulse width the system clock and a divide-by-4 frequency divider. The greater than one SYNC_CLK period. SYNC_CLK, which is externally provided, can be used to The timing diagram shown in Figure 40 depicts when data in synchronize external hardware to the AD9959 internal clocks. the buffer is transferred to the active registers. I/O_UPDATE initiates the start of a buffer transfer. It can be sent synchronously or asynchronously relative to the SYNC_CLK. SYSCLK AB SYNC_CLK I/O_UPDATE DATA IN N – 1 NN + 1 REGISTERS DATA IN N N + 1 N + 2 I/O BUFFERS THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B. Figure 40. I/O_UPDATE Transferring Data from I/O Buffer to Active Registers Rev. C | Page 30 of 44 05246-049Data Sheet AD9959 SERIAL I/O PORT Phase 2 of the I/O cycle consists of the actual data transfer OVERVIEW (write/read) between the serial port controller and the serial The AD9959 serial I/O port offers multiple configurations to port buffer. The number of bytes transferred during this phase provide significant flexibility. The serial I/O port offers an SPI- of the communication cycle is a function of the register being compatible mode of operation that is virtually identical to the accessed. The actual number of additional SCLK rising edges SPI operation found in earlier Analog Devices DDS products. required for the data transfer and instruction byte depends on The flexibility is provided by four data pins (SDIO_0, SDIO_1, the number of bytes in the register and the serial I/O mode of SDIO_2, SDIO_3) that allow four programmable modes of operation. serial I/O operation. For example, when accessing Function Register 1 (FR1), which Three of the four data pins (SDIO_1, SDIO_2, SDIO_3) can be is three bytes wide, Phase 2 of the I/O cycle requires that three used for functions other than serial I/O port operation. These pins bytes be transferred. After transferring all data bytes per the can also be used to initiate a ramp-up or ramp-down (RU/RD) instruction byte, the communication cycle is completed for that of the 10-bit amplitude output scalar. In addition, SDIO_3 can register. be used to provide the SYNC_I/O function that resynchronizes At the completion of a communication cycle, the AD9959 serial the serial I/O port controller if it is out of proper sequence. port controller expects the next set of rising SCLK edges to be The maximum speed of the serial I/O port SCLK is 200 MHz, the instruction byte for the next communication cycle. All data but the four data pins (SDIO_0, SDIO_1, SDIO_2, SDIO_3) written to the AD9959 is registered on the rising edge of SCLK. can be used to further increase data throughput. The maximum Data is read on the falling edge of SCLK (see Figure 43 through data throughput using all the SDIO pins (SDIO_0, SDIO_1, Figure 49). The timing specifications for Figure 41 and Figure 42 SDIO_2, SDIO_3) is 800 Mbps. are described in Table 25. Note that all channels share Register 0x03 to Register 0x18, which t t PRE SCLK are shown in the Register Maps and Bit Descriptions section. CS This address sharing enables all four DDS channels to be written t DSU to simultaneously. For example, if a common frequency tuning t SCLKPWL SCLK word is desired for all four channels, it can be written once t SCLKPWH through the serial I/O port to all four channels. This is the t DHLD default mode of operation (all channels enabled). To enable SDIO_x each channel to be independent, the four channel enable bits found in the channel select register (CSR, Register 0x00) must Figure 41. Setup and Hold Timing for the Serial I/O Port be used. CS There are effectively four sets or copies of addresses (Register 0x03 to Register 0x18) that the channel enable bits can access to provide channel independence. See the Descriptions for Control Registers SCLK section for further details of programming channels that are common to or independent from each other. To properly read SDIO_x back Register 0x03 to Register 0x18, the user must enable only SDO (SDIO_2) one channel enable bit at a time. t DV Serial operation of the AD9959 occurs at the register level, not the byte level; that is, the controller expects that all bytes Figure 42. Timing Diagram for Data Read for Serial I/O Port contained in the register address are accessed. The SYNC_I/O Table 25. Timing Specifications function can be used to abort an I/O operation, thereby allowing Parameter Min Unit Description fewer than all bytes to be accessed. This feature can be used to t 1.0 ns min PRE CS setup time program only a part of the addressed register. Note that only tSCLK 5.0 ns min Period of serial data clock completed bytes are affected. tDSU 2.2 ns min Serial data setup time There are two phases to a serial communications cycle. Phase 1 tSCLKPWH 2.2 ns min Serial data clock pulse width high is the instruction cycle, which writes the instruction byte into t 1.6 ns min Serial data clock pulse width low SCLKPWL the AD9959. Each bit of the instruction byte is registered on t 0 ns min Serial data hold time DHLD each corresponding rising edge of SCLK. The instruction byte tDV 12 ns min Data valid time defines whether the upcoming data transfer is a write or read operation. The instruction byte contains the serial address of the address register. Rev. C | Page 31 of 44 05246-024 05246-023AD9959 Data Sheet Each set of communication cycles does not require an I/O update this pin. The SDO function is not available in 2-bit or 4-bit serial to be issued. The I/O update transfers data from the I/O port I/O modes. buffer to active registers. The I/O update can be sent for each SYNC_I/O communication cycle or can be sent when all serial operations The SYNC_I/O function is available in 1-bit and 2-bit modes. are complete. However, data is not active until an I/O update is SDIO_3 serves as the SYNC_I/O pin when this function is sent, with the exception of the channel enable bits in the channel active. Bits CSR[2:1] control the configuration of this pin. select register (CSR). These bits do not require an I/O update to Otherwise, the SYNC_I/O function is used to synchronize the be enabled. I/O port state machines without affecting the addressable register INSTRUCTION BYTE DESCRIPTION contents. An active high input on the SYNC_I/O (SDIO_3) pin causes the current communication cycle to abort. After SDIO_3 The instruction byte contains the following information: returns low (Logic 0), another communication cycle can begin, MSB LSB starting with the instruction byte write. The SYNC_I/O function is D7 D6 D5 D4 D3 D2 D1 D0 not available in 4-bit serial I/O mode. 1 1 R/W x x A4 A3 A2 A1 A0 MSB/LSB TRANSFER DESCRIPTION 1 x = don’t care bit. The AD9959 serial port can support both most significant bit Bit D7 of the instruction byte (R/W) determines whether a read (MSB) first or least significant bit (LSB) first data formats. This or write data transfer occurs after the instruction byte write. A functionality is controlled by CSR[0]. MSB first is the default logic high indicates a read operation. A logic low indicates a mode. When CSR[0] is set high, the AD9959 serial port is in write operation. LSB first format. The instruction byte must be written in the format indicated by CSR[0], that is, if the AD9959 is in LSB first Bit D4 to Bit D0 of the instruction byte determine which register is mode, the instruction byte must be written from LSB to MSB. If accessed during the data transfer portion of the communication the AD9959 is in MSB first mode (default), the instruction byte cycle. The internal byte addresses are generated by the AD9959. must be written from MSB to LSB. SERIAL I/O PORT PIN DESCRIPTION Example Operation Serial Data Clock (SCLK) To write Function Register 1 (FR1, Register 0x01) in MSB first The serial data clock pin is used to synchronize data to and from format, apply an instruction byte of 00000001 starting with the the internal state machines of the AD9959. The maximum MSB (in the following example instruction byte, the MSB is SCLK toggle frequency is 200 MHz. D7). From this instruction, the internal controller recognizes a CS Chip Select ( ) write transfer of three bytes starting with the MSB, FR1[23]. Bytes are written on each consecutive rising SCLK edge until The chip select pin allows more than one AD9959 device to be Bit 0 is transferred. When the last data bit is written, the I/O on the same set of serial communications lines. The chip select communication cycle is complete and the next byte is considered is an active low enable pin. SDIO_x inputs go to a high imped- an instruction byte. CS CS ance state when is high. If is driven high during any 1 CS Example Instruction Byte communication cycle, that cycle is suspended until is CS MSB LSB reactivated low. The pin can be tied low in systems that maintain control of SCLK. D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 1 Serial Data I/O (SDIO_0, SDIO_1, SDIO_3) Of the four SDIO pins, only the SDIO_0 pin is a dedicated SDIO 1 Note that the bit values are for example purposes only. pin. SDIO_1, SDIO_2, and SDIO_3 can also be used to ramp To write Function Register 1 (FR1) in LSB first format, apply an up/ramp down the output amplitude. Bits[2:1] in the channel instruction byte of 00000001, starting with the LSB bit (in the select register (CSR, Register 0x00) control the configuration preceding example instruction byte, the LSB is D0). From this of these pins. See the Serial I/O Modes of Operation for more instruction, the internal controller recognizes a write transfer of information. three bytes, starting with the LSB, FR1[0]. Bytes are written on SERIAL I/O PORT FUNCTION DESCRIPTION each consecutive rising SCLK edge until Bit 23 is transferred. When the last data bit is written, the I/O communication cycle is Serial Data Out (SDO) complete and the next byte is considered an instruction byte. The SDO function is available in single-bit (3-wire) mode only. In SDO mode, data is read from the SDIO_2 pin for protocols that use separate lines for transmitting and receiving data (see Table 26 for pin configuration options). Bits[2:1] in the channel select register (CSR, Register 0x00) control the configuration of Rev. C | Page 32 of 44 Data Sheet AD9959 In single-bit serial mode, 2-wire interface operation, the SERIAL I/O MODES OF OPERATION SDIO_0 pin is the single serial data I/O pin. In single-bit serial The following are the four programmable modes of serial I/O mode 3-wire interface operation, the SDIO_0 pin is the serial port operation: data input pin and the SDIO_2 pin is the output data pin. ? Single-bit serial 2-wire mode (default mode) Regardless of the number of wires used in the interface, the ? Single-bit serial 3-wire mode SDIO_3 pin is configured as an input and operates as the ? 2-bit serial mode SYNC_I/O pin in the single-bit serial mode and 2-bit serial ? 4-bit serial mode (SYNC_I/O not available) mode. The SDIO_1 pin is unused in this mode (see Table 26). 2-Bit Serial Mode Table 26 displays the function of all six serial I/O interface pins, depending on the mode of serial I/O operation programmed. The SPI port operation in 2-bit serial mode is identical to the SPI port operation in single-bit serial mode, except that two bits Table 26. Serial I/O Port Pin Function vs. Serial I/O Mode of data are registered on each rising edge of SCLK. Therefore, it Single-Bit Single-Bit 2-Bit 4-Bit only takes four clock cycles to transfer eight bits of information. Serial 2-Wire Serial 3-Wire Serial Serial The SDIO_0 pin contains the even numbered data bits using Pin Mode Mode Mode Mode the notation D[7:0], and the SDIO_1 pin contains the odd SCLK Serial clock Serial clock Serial clock Serial clock numbered data bits. This even and odd numbered pin/data CS Chip select Chip select Chip select Chip alignment is valid in both MSB and LSB first formats (see select Figure 44). SDIO_0 Serial data I/O Serial data in Serial data Serial 4-Bit Serial Mode I/O data I/O SDIO_1 Not used for Not used for Serial data Serial The SPI port in 4-bit serial mode is identical to the SPI port in 1 1 SDIO SDIO I/O data I/O single-bit serial mode, except that four bits of data are registered SDIO_2 Not used for Serial data Not used Serial on each rising edge of SCLK. Therefore, it takes only two clock 1 1 SDIO out (SDO) for SDIO data I/O cycles to transfer eight bits of information. The SDIO_0 and SDIO_3 SYNC_I/O SYNC_I/O SYNC_I/O Serial SDIO_2 pins contain even numbered data bits using the notation data I/O D[7:0], and the SDIO_0 pin contains the LSB of the nibble. The 1 In serial mode, these pins (SDIO_0/SDIO_1/SDIO_2/SDIO_3) can be used for SDIO_1 and SDIO_3 pins contain the odd numbered data bits, RU/RD operation. and the SDIO_1 pin contains the LSB of the nibble to be accessed. The two bits in the channel select register, CSR[2:1], set the Note that when programming the device for 4-bit serial mode, serial I/O mode of operation and are defined in Table 27. it is important to keep the SDIO_3 pin at Logic 0 until the device is Table 27. Serial I/O Mode of Operation programmed out of the single-bit serial mode. Failure to do so Serial I/O Mode Select can result in the serial I/O port controller being out of sequence. (CSR[2:1]) Mode of Operation Figure 43 through Figure 45 represent write timing diagrams 00 Single-bit serial mode (2-wire mode) for each of the serial I/O modes available. Both MSB and LSB 01 Single-bit serial mode (3-wire mode) first modes are shown. LSB first bits are shown in parentheses. 10 2-bit serial mode The clock stall low/high feature shown is not required. It is used 11 4-bit serial mode to show that data (SDIO) must have the proper setup time Single-Bit Serial (2-Wire and 3-Wire) Modes relative to the rising edge of SCLK. The single-bit serial mode interface allows read/write access to Figure 46 through Figure 49 represent read timing diagrams for all registers that configure the AD9959. MSB first or LSB first each of the serial I/O modes available. Both MSB and LSB first transfer formats are supported. In addition, the single-bit serial modes are shown. LSB first bits are shown in parentheses. The mode interface port can be configured either as a single pin I/O, clock stall low/high feature shown is not required. It is used to which allows a 2-wire interface, or as two unidirectional pins show that data (SDIO) must have the proper setup time relative for input/output, which enable a 3-wire interface. Single-bit to the rising edge of SCLK for the instruction byte and the read mode allows the use of the SYNC_I/O function. data that follows the falling edge of SCLK. Rev. C | Page 33 of 44 AD9959 Data Sheet INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK I7 I6 I5 I4 I3 I2 I1 I0 D7 D6 D5 D4 D3 D2 D1 D0 SDIO_0 (I0) (I1) (I2) (I3) (I4) (I5) (I6) (I7) (D0) (D1) (D2) (D3) (D4) (D5) (D6) (D7) Figure 43. Single-Bit Serial Mode Write Timing—Clock Stall Low INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK I7 I5 I3 I1 D7 D5 D3 D1 SDIO_1 (I1) (I3) (I5) (I7) (D1) (D3) (D5) (D7) I6 I4 I2 I0 D6 D4 D2 D0 SDIO_0 (I0) (I2) (I4) (I6) (D0) (D2) (D4) (D6) Figure 44. 2-Bit Serial Mode Write Timing—Clock Stall Low INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK I7 I3 D7 D3 SDIO_3 (I7) (I3) (D3) (D7) I6 I2 D6 D2 SDIO_2 (I2) (I6) (D2) (D6) I5 I1 D5 D1 SDIO_1 (I1) (I5) (D1) (D5) I4 I0 D4 D0 SDIO_0 (I0) (I4) (D0) (D4) Figure 45. 4-Bit Serial Mode Write Timing—Clock Stall Low Rev. C | Page 34 of 44 05246-027 05246-026 05246-025Data Sheet AD9959 INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK I7 I6 I5 I4 I3 I2 I1 I0 D7 D6 D5 D4 D3 D2 D1 D0 SDIO_0 (I0) (I1) (I2) (I3) (I4) (I5) (I6) (I7) (D0) (D1) (D2) (D3) (D4) (D5) (D6) (D7) Figure 46. Single-Bit Serial Mode (2-Wire) Read Timing—Clock Stall High DATA TRANSFER CYCLE INSTRUCTION CYCLE CS SCLK I7 I6 I5 I4 I3 I2 I1 I0 DON''T CARE SDIO_0 (I0) (I1) (I2) (I3) (I4) (I5) (I6) (I7) SDO D7 D6 D5 D4 D3 D2 D1 D0 (D0) (D1) (D2) (D3) (D4) (D5) (D6) (D7) (SDIO_2 PIN) Figure 47. Single-Bit Serial Mode (3-Wire) Read Timing—Clock Stall Low INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK I7 I5 I3 I1 D7 D5 D3 D1 SDIO_1 (D1) (D3) (D5) (D7) (I1) (I3) (I5) (I7) I6 I4 I2 I0 D6 D4 D2 D0 SDIO_0 (I0) (I2) (I4) (I6) (D0) (D2) (D4) (D6) Figure 48. 2-Bit Serial Mode Read Timing—Clock Stall High INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK I7 I3 D7 D3 SDIO_3 (I3) (I7) (D3) (D7) I6 I2 D6 D2 SDIO_2 (I2) (I6) (D2) (I6) I5 I1 D5 D1 (I1) (I5) (D1) (D5) SDIO_1 I4 I0 D4 D0 (I0) (I4) (D0) (D4) SDIO_0 Figure 49. 4-Bit Serial Mode Read Timing—Clock Stall High Rev. C | Page 35 of 44 05246-031 05246-030 05246-028 05246-029AD9959 Data Sheet REGISTER MAPS AND BIT DESCRIPTIONS REGISTER MAPS Table 28. Control Register Map Register Name (Serial Bit Bit 7 Bit 0 Default Address) Range (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Value Channel [7:0] Channel 3 Channel 2 Channel 1 Channel 0 Must Serial I/O mode LSB first 0xF0 1 1 1 1 Select enable enable enable enable be 0 select[2:1] Register (CSR) (0x00) Function [23:16] VCO gain PLL divider ratio[22:18] Charge pump 0x00 Register 1 control control[17:16] (FR1) (0x01) [15:8] Open Profile pin configuration (PPC)[14:12] Ramp-up/ Modulation level[9:8] 0x00 ramp-down (RU/RD)[11:10] [7:0] Reference External power- SYNC_CLK DAC reference Open[3:2] Manual Manual 0x00 clock input down mode disable power-down hardware software power-down sync sync Function [15:8] All channels All channels All channels All channels Open[11:10] Open[9:8] 0x00 Register 2 autoclear clear sweep autoclear phase clear phase (FR2) sweep accumulator accumulator accumulator (0x02) accumulator [7:0] Auto sync Multidevice sync Multidevice sync Multidevice sync Open[3:2] System clock 0x00 enable master enable status mask offset[1:0] 1 Channel enable bits do not require an I/O update to be activated. These bits are active immediately after the byte containing the bits is written. All other bits need an I/O update to become active. The four channel enable bits shown in Table 28 are used to enable/disable any combination of the four channels. The default for all four channels is enabled. In the channel select register, if the user wants four different 3. Enable the Channel 1 enable bit only, located in the frequencies for all four DDS channels, use the following channel select register, and disable the other three protocol: channels. 4. Write the desired frequency tuning word for Channel 1. Enable (Logic 1) the Channel 0 enable bit, which is 1 in Step 3, then disable the Channel 1 enable bit. located in the channel select register, and disable the other three channels (Logic 0). 2. Write the desired frequency tuning word for Channel 0, as described in Step 1, and then disable the Channel 0 enable bit (Logic 0). Rev. C | Page 36 of 44 Data Sheet AD9959 Table 29. Channel Register Map Register Name Bit Bit 7 Bit 0 Default (Serial Address) Range (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Value Channel [23:16] Amplitude freq. phase Open[21:16] 0x00 Function (AFP) select[23:22] 1 Register [15:8] Linear Linear Load SRR at Open[12:11] Must be 0 DAC full-scale current 0x03 (CFR) sweep sweep I/O_UPDATE control[9:8] (0x03) no-dwell enable Digital DAC Matched Autoclear Clear sweep Autoclear Clear phase Sine [7:0] 0x02 2 power- power- pipe delays sweep accumulator phase accumulator wave down down active accumulator accumulator output enable Channel [31:24] Frequency Tuning Word 0[31:24] 0x00 Frequency [23:16] Frequency Tuning Word 0[23:16] N/A Tuning [15:8] Frequency Tuning Word 0[15:8] N/A 1 Word 0 [7:0] Frequency Tuning Word 0[7:0] N/A (CFTW0) (0x04) Channel [15:8] Open[15:14] Phase Offset Word 0[13:8] 0x00 Phase [7:0] Phase Offset Word 0[7:0] 0x00 Offset 1 Word 0 (CPOW0) (0x05) Amplitude [23:16] Amplitude ramp rate[23:16] N/A Control [15:8] Increment/decrement Open Amplitude Ramp-up/ Load ARR at Amplitude scale 0x00 Register step size[15:14] multiplier ramp-down I/O_UPDATE factor[9:8] (ACR) enable enable (0x06) [7:0] Amplitude scale factor[7:0] 0x00 Linear [15:8] Falling sweep ramp rate (FSRR)[15:8] N/A Sweep [7:0] Rising sweep ramp rate (RSRR)[7:0] N/A Ramp 1 Rate (LSRR) (0x07) LSR Rising [31:24] Rising delta word[31:24] N/A Delta [23:16] Rising delta word[23:16] N/A 1 Word [15:8] Rising delta word[15:8] N/A (RDW) [7:0] Rising delta word[7:0] N/A (0x08) LSR Falling [31:24] Falling delta word[31:24] N/A Delta [23:16] Falling delta word[23:16] N/A 1 Word [15:8] Falling delta word[15:8] N/A (FDW) [7:0] Falling delta word[7:0] N/A (0x09) 1 There are four sets of channel registers and profile registers, one per channel. This is not shown in the Table 29 or Table 30 because the addresses of all channel registers and profile registers are the same for each channel. Therefore, the channel enable bits (CSR[7:4]) determine if the channel registers and/or profile registers of each channel are written to or not. 2 The clear phase accumulator bit is set to Logic 1 after a master reset. It self-clears or is set to Logic 0 when an I/O update is asserted. Rev. C | Page 37 of 44 AD9959 Data Sheet 1 Table 30. Profile Register Map Bit Bit 7 Bit 0 Default Register Name (Address) Range (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Value Channel Word 1 (CW1) (0x0A) [31:0] Frequency tuning word[31:0] or phase word[31:18] or amplitude word[31:22] N/A Channel Word 2 (CW2) (0x0B) [31:0] Frequency tuning word[31:0] or phase word[31:18] or amplitude word[31:22] N/A Channel Word 3 (CW3) (0x0C) [31:0] Frequency tuning word[31:0] or phase word[31:18] or amplitude word[31:22] N/A Channel Word 3 (CW4) (0x0D) [31:0] Frequency tuning word[31:0] or phase word[31:18] or amplitude word[31:22] N/A Channel Word 5 (CW5) (0x0E) [31:0] Frequency tuning word[31:0] or phase word[31:18] or amplitude word[31:22] N/A Channel Word 6 (CW6) (0x0F) [31:0] Frequency tuning word[31:0] or phase word[31:18] or amplitude word[31:22] N/A Channel Word 7 (CW7) (0x10) [31:0] Frequency tuning word[31:0] or phase word[31:18] or amplitude word[31:22] N/A Channel Word 8 (CW8) (0x11) [31:0] Frequency tuning word[31:0] or phase word[31:18] or amplitude word[31:22] N/A Channel Word 9 (CW9) (0x12) [31:0] Frequency tuning word[31:0] or phase word[31:18] or amplitude word[31:22] N/A Channel Word 10 (CW10) (0x13) [31:0] Frequency tuning word[31:0] or phase word[31:18] or amplitude word[31:22] N/A Channel Word 11 (CW11) (0x14) [31:0] Frequency tuning word[31:0] or phase word[31:18] or amplitude word[31:22] N/A Channel Word 12 (CW12) (0x15) [31:0] Frequency tuning word[31:0] or phase word[31:18] or amplitude word[31:22] N/A Channel Word 13 (CW13) (0x16) [31:0] Frequency tuning word[31:0] or phase word[31:18] or amplitude word[31:22] N/A Channel Word 14 (CW14) (0x17) [31:0] Frequency tuning word[31:0] or phase word[31:18] or amplitude word[31:22] N/A Channel Word 15 (CW15) (0x18) [31:0] Frequency tuning word[31:0] or phase word[31:18] or amplitude word[31:22] N/A 1 Each channel word register has a capacity of 32 bits. If phase or amplitude is stored in the channel word registers, it must be first MSB aligned per the bit range. Only the MSB byte is shown for each channel word register. Rev. C | Page 38 of 44 Data Sheet AD9959 DESCRIPTIONS FOR CONTROL REGISTERS Channel Select Register (CSR)—Address 0x00 One byte is assigned to this register. The CSR determines if channels are enabled or disabled by the status of the four channel enable bits. All four channels are enabled by their default state. The CSR also determines which serial mode of operation is selected. In addition, the CSR offers a choice of MSB first or LSB first format. Table 31. Bit Descriptions for CSR Bit Mnemonic Description 7:4 Channel [3:0] enable Bits are active immediately after being written. They do not require an I/O update to take effect. There are four sets of channel registers and profile (channel word) registers, one per channel. This is not shown in the channel register map or the profile register map. The addresses of all channel registers and profile registers are the same for each channel. Therefore, the channel enable bits distinguish the channel registers and profile registers values of each channel. For example, 1001 = only Channel 3 and Channel 0 receive commands from the channel registers and profile registers. 0010 = only Channel 1 receives commands from the channel registers and profile registers. 3 Must be 0 Must be set to 0. 2:1 Serial I/O mode select 00 = single-bit serial (2-wire mode). 01 = single-bit serial (3-wire mode). 10 = 2-bit serial mode. 11 = 4-bit serial mode. See the Serial I/O Modes of Operation section for more details. 0 LSB first 0 = the serial interface accepts serial data in MSB first format (default). 1 = the serial interface accepts serial data in LSB first format. Function Register 1 (FR1)—Address 0x01 Three bytes are assigned to this register. FR1 is used to control the mode of operation of the chip. Table 32. Bit Descriptions for FR1 Bit Mnemonic Description 23 VCO gain control 0 = the low range (system clock below 160 MHz) (default). 1 = the high range (system clock above 255 MHz). 22:18 PLL divider ratio If the value is 4 or 20 (decimal) or between 4 and 20, the PLL is enabled and the value sets the multiplication factor. If the value is outside of 4 and 20 (decimal), the PLL is disabled. 17:16 Charge pump control 00 (default) = the charge pump current is 75 μA. 01 = charge pump current is 100 μA. 10 = charge pump current is 125 μA. 11 = charge pump current is 150 μA. 15 Open 14:12 Profile pin configuration (PPC) The profile pin configuration bits control the configuration of the data and SDIO_x pins for the different modulation modes. See the Modulation Mode section in this document for details. 11:10 Ramp-up/ramp-down (RU/RD) The RU/RD bits control the amplitude ramp-up/ramp-down time of a channel. See the Output Amplitude Control Mode section for more details. 9:8 Modulation level The modulation (FSK, PSK, and ASK) level bits control the level (2/4/8/16) of modulation to be performed for a channel. See the Modulation Mode section for more details. 7 Reference clock input 0 = the clock input circuitry is enabled for operation (default). power-down 1 = the clock input circuitry is disabled and is in a low power dissipation state. 6 External power-down mode 0 = the external power-down mode is in fast recovery power-down mode (default). In this mode, when the PWR_DWN_CTL input pin is high, the digital logic and the DAC digital logic are powered down. The DAC bias circuitry, PLL, oscillator, and clock input circuitry are not powered down. 1 = the external power-down mode is in full power-down mode. In this mode, when the PWR_DWN_CTL input pin is high, all functions are powered down. This includes the DAC and PLL, which take a significant amount of time to power up. Rev. C | Page 39 of 44 AD9959 Data Sheet Bit Mnemonic Description 5 SYNC_CLK disable 0 = the SYNC_CLK pin is active (default). 1 = the SYNC_CLK pin assumes a static Logic 0 state (disabled). In this state, the pin drive logic is shut down. However, the synchronization circuitry remains active internally to maintain normal device operation. 4 DAC reference power-down 0 = DAC reference is enabled (default). 1 = DAC reference is powered down. 3:2 Open See the Synchronizing Multiple AD9959 Devices section for details. 1 Manual hardware sync 0 = the manual hardware synchronization feature of multiple devices is inactive (default). 1 = the manual hardware synchronization feature of multiple devices is active. 0 Manual software sync 0 = the manual software synchronization feature of multiple devices is inactive (default). 1 = the manual software synchronization feature of multiple devices is active. See the Synchronizing Multiple AD9959 Devices section for details. Function Register 2 (FR2)—Address 0x02 Two bytes are assigned to this register. The FR2 is used to control the various functions, features, and modes of the AD9959. Table 33. Bit Descriptions for FR2 Bit Mnemonic Description 15 All channels autoclear sweep 0 = a new delta word is applied to the input, as in normal operation, but not loaded into the accumulator accumulator (default). 1 = this bit automatically and synchronously clears (loads 0s into) the sweep accumulator for one cycle upon reception of the I/O_UPDATE sequence indicator on all four channels. 14 All channels clear 0 = the sweep accumulator functions as normal (default). sweep accumulator 1 = the sweep accumulator memory elements for all four channels are asynchronously cleared. 13 All channels autoclear phase 0 = a new frequency tuning word is applied to the inputs of the phase accumulator, but not accumulator loaded into the accumulator (default). 1 = this bit automatically and synchronously clears (loads 0s into) the phase accumulator for one cycle upon receipt of the I/O update sequence indicator on all four channels. 12 All channels clear phase 0 = the phase accumulator functions as normal (default). accumulator 1 = the phase accumulator memory elements for all four channels are asynchronously cleared. 11:8 Open 7 Auto sync enable See the Synchronizing Multiple AD9959 Devices section for more details. 6 Multidevice sync master enable See the Synchronizing Multiple AD9959 Devices section for more details. 5 Multidevice sync status See the Synchronizing Multiple AD9959 Devices section for more details. 4 Multidevice sync mask See the Synchronizing Multiple AD9959 Devices section for more details. 3: 2 Open 1:0 System clock offset See the Synchronizing Multiple AD9959 Devices section for more details. Rev. C | Page 40 of 44 Data Sheet AD9959 DESCRIPTIONS FOR CHANNEL REGISTERS Channel Function Register (CFR)—Address 0x03 Three bytes are assigned to this register. Table 34. Bit Descriptions for CFR Bit Mnemonic Description 23:22 Amplitude frequency Controls what type of modulation is to be performed for that channel. See the Modulation Mode section phase (AFP) select for details. 21:16 Open 15 Linear sweep no-dwell 0 = the linear sweep no-dwell function is inactive (default). 1 = the linear sweep no-dwell function is active. If CFR[15] is active, the linear sweep no-dwell function is activated. See the Linear Sweep Mode section for details. If CFR[14] is clear, this bit is don’t care. 14 Linear sweep enable 0 = the linear sweep capability is inactive (default). 1 = the linear sweep capability is enabled. When enabled, the delta frequency tuning word is applied to the frequency accumulator at the programmed ramp rate. 13 Load SRR at 0 = the linear sweep ramp rate timer is loaded only upon timeout (timer = 1) and is not loaded because I/O_UPDATE of an I/O_UPDATE input signal (default). 1 = the linear sweep ramp rate timer is loaded upon timeout (timer = 1) or at the time of an I/O_UPDATE input signal. 12:11 Open 10 Must be 0 Must be set to 0. 9:8 DAC full-scale current 11 = the DAC is at the largest LSB value (default). control See Table 5 for other settings. 7 Digital power-down 0 = the digital core is enabled for operation (default). 1 = the digital core is disabled and is in its lowest power dissipation state. 6 DAC power-down 0 = the DAC is enabled for operation (default). 1 = the DAC is disabled and is in its lowest power dissipation state. 5 Matched pipe delays 0 = matched pipe delay mode is inactive (default). active 1 = matched pipe delay mode is active. See the Single-Tone Mode—Matched Pipeline Delay section for details. 4 Autoclear sweep 0 = the current state of the sweep accumulator is not impacted by receipt of an I/O_UPDATE signal accumulator (default). 1 = the sweep accumulator is automatically and synchronously cleared for one cycle upon receipt of an I/O_UPDATE signal. 3 Clear sweep 0 = the sweep accumulator functions as normal (default). accumulator 1 = the sweep accumulator memory elements are asynchronously cleared. 2 Autoclear phase 0 = the current state of the phase accumulator is not impacted by receipt of an I/O_UPDATE signal accumulator (default). 1 = the phase accumulator is automatically and synchronously cleared for one cycle upon receipt of an I/O_UPDATE signal. 1 Clear phase 0 = the phase accumulator functions as normal (default). accumulator 1 = the phase accumulator memory elements are asynchronously cleared. 0 Sine wave output 0 = the angle-to-amplitude conversion logic employs a cosine function (default). enable 1 = the angle-to-amplitude conversion logic employs a sine function. Rev. C | Page 41 of 44 AD9959 Data Sheet Channel Frequency Tuning Word 0 (CFTW0)—Address 0x04 Four bytes are assigned to this register. Table 35. Description for CFTW0 Bit Mnemonic Description 31:0 Frequency Tuning Word 0 Frequency Tuning Word 0 for each channel. Channel Phase Offset Word 0 (CPOW0)—Address 0x05 Two bytes are assigned to this register. Table 36. Description for CPOW0 Bit Mnemonic Description 15:14 Open 13:0 Phase Offset Word 0 Phase Offset Word 0 for each channel Amplitude Control Register (ACR)—Address0x06 Three bytes are assigned to this register. Table 37. Description for ACR Bit Mnemonic Description 23:16 Amplitude ramp rate Amplitude ramp rate value. 15:14 Increment/decrement Amplitude increment/decrement step size. step size 13 Open 12 Amplitude multiplier 0 = amplitude multiplier is disabled. The clocks to this scaling function (auto RU/RD) are stopped enable for power saving, and the data from the DDS core is routed around the multipliers (default). 1 = amplitude multiplier is enabled. 11 Ramp-up/ramp-down This bit is valid only when ACR[12] is active high. enable 0 = when ACR[12] is active, Logic 0 on ACR[11] enables the manual RU/RD operation. See the Output Amplitude Control Mode section for details (default). 1 = if ACR[12] is active, a Logic 1 on ACR[11] enables the auto RU/RD operation. See the Output Amplitude Control Mode section for details. 10 Load ARR at 0 = the amplitude ramp rate timer is loaded only upon timeout (timer = 1) and is not loaded due I/O_UPDATE to an I/O_UPDATE input signal (default). 1 = the amplitude ramp rate timer is loaded upon timeout (timer = 1) or at the time of an I/O_UPDATE input signal. 9:0 Amplitude scale factor Amplitude scale factor for each channel. Rev. C | Page 42 of 44 Data Sheet AD9959 Linear Sweep Ramp Rate (LSRR)—Address 0x07 Two bytes are assigned to this register. Table 38. Description for LSRR Bit Mnemonic Description 15:8 Falling sweep ramp rate (FSRR) Linear falling sweep ramp rate. 7:0 Rising sweep ramp rate (RSRR) Linear rising sweep ramp rate. LSR Rising Delta Word (RDW)—Address 0x08 Four bytes are assigned to this register. Table 39. Description for RDW Bit Mnemonic Description 31:0 Rising delta word 32-bit rising delta-tuning word. LSR Falling Delta Word (FDW)—Address 0x09 Four bytes are assigned to this register. Table 40. Description for FDW Bit Mnemonic Description 31:0 Falling delta word 32-bit falling delta-tuning word. Rev. C | Page 43 of 44 AD9959 Data Sheet OUTLINE DIMENSIONS 0.30 8.10 0.60 MAX 0.23 8.00 SQ 0.18 7.90 0.60 MAX 43 56 1 42 0.50 PIN 1 BSC INDICATOR 7.85 EXPOSED 6.25 7.75 SQ PAD 6.10 SQ 7.65 5.95 29 14 28 15 0.50 0.25 MIN TOP VIEW BOTTOM VIEW 0.40 6.50 REF 0.30 0.80 MAX 1.00 12° MAX 0.65 TYP FOR PROPER CONNECTION OF 0.85 THE EXPOSED PAD, REFER TO 0.05 MAX 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY SIDE VIEW SEATING 0.20 REF 0.08 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2 Figure 50. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 8 mm × 8 mm Body, Very Thin Quad (CP-56-1) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9959BCPZ –40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-56-1 AD9959BCPZ-REEL7 –40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-56-1 AD9959/PCBZ Evaluation Board 1 Z = RoHS Compliant Part. ?2005–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05246-0-10/16(C) Rev. C | Page 44 of 44 PIN 1 INDICATOR 06-07-2012-A |
|