Ultralow Power, Low Distortion,
Fully Differential ADC Drivers
Data Sheet
ADA4940-1/ADA4940-2
Rev. E Document Feedback
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FEATURES
Small signal bandwidth: 260 MHz
Ultralow power 1.25mA
Extremely low harmonic distortion
?122 dB THD at 50 kHz
?96 dB THD at 1 MHz
Low input voltage noise: 3.9 nV/√Hz
0.35 mV maximum offset voltage
Balanced outputs
Settling time to 0.1%: 34 ns
Rail-to-rail output: ?VS + 0.1 V to +VS ? 0.1 V
Adjustable output common-mode voltage
Flexible power supplies: 3 V to 7 V (LFCSP)
Disable pin to reduce power consumption
ADA4940-1 is available in LFCSP and SOIC packages
APPLICATIONS
Low power PulSAR?/SAR ADC drivers
Single-ended-to-differential conversion
Differential buffers
Line drivers
Medical imaging
Industrial process controls
Portable electronics
GENERAL DESCRIPTION
The ADA4940-1/ADA4940-2 are low noise, low distortion fully
differential amplifiers with very low power consumption. They
are an ideal choice for driving low power, high resolution, high
performance SAR and Σ-Δ analog-to-digital converters (ADCs)
with resolutions up to 16 bits from dc to 1 MHz on only 1.25 mA
of quiescent current. The adjustable level of the output common-
mode voltage allows the ADA4940-1/ADA4940-2 to match the
input common-mode voltage of multiple ADCs. The internal
common-mode feedback loop provides exceptional output balance,
as well as suppression of even-order harmonic distortion products.
With the ADA4940-1/ADA4940-2, differential gain configurations
are easily realized with a simple external feedback network of
four resistors determining the closed-loop gain of the amplifier.
The ADA4940-1/ADA4940-2 are fabricated using Analog Devices,
Inc., SiGe complementary bipolar process, enabling them to
achieve very low levels of distortion with an input voltage noise
of only 3.9 nV/√Hz. The low dc offset and excellent dynamic
performance of the ADA4940-1/ADA4940-2 make them well
suited for a variety of data acquisition and signal processing
applications.
FUNCTIONAL BLOCK DIAGRAMS
NOTES
1. CONNECT THE EXPOSED PAD TO
–V
S
OR GROUND.
DISABLE–FB
+IN
–IN
+FB
–OUT
ADA4940-1
+OUT
V
OCM
+
V
S
+
V
S
+
V
S
+
V
S
–
V
S
–
V
S
–
V
S
–
V
S
12
11
10
1
3
4 9
2
65 7 8
1
6
1
5
1
4
1
3
0
845
2-
0
0
1
Figure 1. ADA4940-1
–IN1
+FB1
+V
S1
+V
S1
–FB2
+IN2
–
I
N
2
+
F
B
2
+
V
S
2
V
O
C
M
2
+
O
U
T
2
+
V
S
2
–
V
S
1
–
V
S
1
–
F
B
1
+
I
N
1
D
I
S
A
B
L
E
1
–
O
U
T
1
DISABLE2
–V
S2
–V
S2
V
OCM1
+OUT1
ADA4940-2
–OUT2
0
742
9-
20
2
2
1
3
4
5
6
18
17
16
15
14
13
8 9
1
0
1
17
1
2
2
0
1
9
2
1
2
2
2
3
2
4
NOTES
1. CONNECT THE EXPOSED PAD TO
–V
S
OR GROUND.
Figure 2. ADA4940-2
The ADA4940-1 is available in a 3 mm × 3 mm, 16-lead LFCSP
and an 8-lead SOIC. The ADA4940-2 is available in a 4 mm ×
4 mm, 24-lead LFCSP. The pinouts are optimized to facilitate
printed circuit board (PCB) layout and minimize distortion.
The ADA4940-1/ADA4940-2 are specified to operate over the
?40°C to +125°C temperature range.
Table 1. Similar Products to ADA4940-1/ADA4940-2
Product
ISUPPLY
(mA)
Bandwidth
(MHz)
Slew Rate
(V/μs)
Noise
(nV/√Hz)
AD8137 3 110 450 8.25
ADA4932-1 9 560 2800 3.6
ADA4941-1 2.2 31 22 5.1
Table 2. Complementary Products to ADA4940-1/ADA4940-2
Product
Power
(mW)
Throughput
(MSPS)
Resolution
(Bits)
SNR
(dB)
AD7982 7.0 1 18 98
AD7984 10.5 1.333 18 96.5
AD7621 65 3 16 88
AD7623 45 1.333 16 88
ADA4940-1/ADA4940-2 Data Sheet
Rev. E | Page 2 of 30
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
VS = 5 V .......................................................................................... 4
VS = 3 V .......................................................................................... 6
Absolute Maximum Ratings ............................................................ 8
Thermal Resistance ...................................................................... 8
Maximum Power Dissipation ..................................................... 8
ESD Caution .................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 11
Test Circuits ..................................................................................... 20
Terminology .................................................................................... 21
Definition of Terms .................................................................... 21
Theory of Operation ...................................................................... 22
Applications Information .............................................................. 23
Analyzing an Application Circuit ............................................ 23
Setting the Closed-Loop Gain .................................................. 23
Estimating the Output Noise Voltage ...................................... 23
Impact of Mismatches in the Feedback Networks ................. 24
Calculating the Input Impedance of an Application Circuit 24
Input Common-Mode Voltage Range ..................................... 25
Input and Output Capacitive AC Coupling ............................ 26
Setting the Output Common-Mode Voltage .......................... 26
DISABLE Pin .............................................................................. 26
Driving a Capacitive Load ......................................................... 26
Driving a High Precision ADC ................................................ 27
Layout, Grounding, and Bypassing .............................................. 28
ADA4940-1 LFCSP Example .................................................... 28
Outline Dimensions ....................................................................... 29
Ordering Guide .......................................................................... 30
Data Sheet ADA4940-1/ADA4940-2
Rev. E | Page 3 of 30
REVISION HISTORY
4/2018—Rev. D to Rev. E
Changes to Figure 2........................................................................... 1
Changes to Figure 6......................................................................... 10
Updated Outline Dimensions ........................................................ 29
5/2016—Rev. C to Rev. D
Changes to Figure 1........................................................................... 1
Deleted Figure 2................................................................................. 1
Added Figure 2; Renumbered Sequentially ................................... 1
Updated Outline Dimensions ........................................................ 29
Changes to Ordering Guide ........................................................... 30
9/2013—Rev. B to Rev. C
Updated Outline Dimensions ........................................................ 30
Changes to Ordering Guide ........................................................... 31
3/2012—Rev. A to Rev. B
Reorganized Layout ........................................................... Universal
Added ADA4940-1 8-Lead SOIC Package ..................... Universal
Changes to Features Section, Table 1, and Figure 1; Replaced
Figure 2 ............................................................................................... 1
Changed VS = ±2 V(or +5 V) Section to VS = +5 V Section ....... 3
Changes to VS = +5 V Section and Table 3 .................................... 3
Changes to Table 4 and Table 5 ....................................................... 4
Changes to VS = 3 V Section and Table 6 ....................................... 5
Changes to Table 7 and Table 8 ....................................................... 6
Added Figure 5 and Table 12, Renumbered Sequentially ............ 9
Changes to Figure 7, Figure 8, and Figure 9 ................................ 10
Added Figure 15 and Figure 18; Changes to Figure 13,
Figure 14, and Figure 16 ................................................................. 11
Changes to Figure 19 and Figure 20 ............................................. 12
Changes to Figure 25, Figure 26, and Figure 27; Added
Figure 28, Figure 29, and Figure 30 .............................................. 13
Changes to Figure 31, Figure 32, Figure 33, Figure 34, Figure 35,
and Figure 36 ................................................................................... 14
Changes to Figure 37, Figure38, Figure 39, and Figure 41 ........ 15
Changes to Figure 49, Figure 50, and Figure 51 .......................... 17
Added Figure 55 and Figure 57 ..................................................... 18
Changes to Differential VOS, Differential CMRR, and VOCM
CMRR Section ................................................................................. 20
Changes to Calculating the Input Impedance of an Application
Circuit Section ................................................................................. 23
Changes to Figure 71 ...................................................................... 25
Changes to Driving a High Precision ADC Section and
Figure 73 ........................................................................................... 26
Changed ADA4940-1 Example Section to ADA4940-1 LFCSP
Example Section .............................................................................. 27
Changes to Ordering Guide ........................................................... 29
12/2011—Rev. 0 to Rev. A
Changes to Features Section, General Description Section, and
Table 1 ................................................................................................. 1
Replaced Figure 1 and Figure 2 ....................................................... 1
Changes to VS = ±2.5 V (or +5 V) Section and Table 3 ............... 3
Changes to Table 6 ............................................................................ 5
Replaced Figure 7, Figure 8, Figure 9, and Figure 10 ................... 9
Replaced Figure 14, Figure 15, and Figure 17 ............................. 10
Replaced Figure 24 and Figure 27 ................................................. 12
Changes to Figure 37 ...................................................................... 14
Replaced Figure 43 and Figure 46 ................................................. 15
Replaced Figure 53 .......................................................................... 18
Changes to Estimating the Output Noise Voltage Section, Table 14,
Table 15, and Calculating the Input Impedance of an Application
Circuit Section ................................................................................. 21
Changes to Input Common-Mode Voltage Range Section ....... 22
Changes to Driving a High Precision ADC Section and
Figure 65 ........................................................................................... 24
10/2011—Revision 0: Initial Version
ADA4940-1/ADA4940-2 Data Sheet
Rev. E | Page 4 of 30
SPECIFICATIONS
V
S
= 5 V
VOCM = midsupply, RF = RG = 1 k?, RL, dm = 1 k?, TA = 25°C, LFCSP package, unless otherwise noted. TMIN to TMAX = ?40°C to +125°C.
(See Figure 61 for the definition of terms.)
+D
IN
or nullD
IN
to V
OUT, dm
Performance
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
?3 dB Small Signal Bandwidth VOUT, dm = 0.1 V p-p, G = 1 260 MHz
VOUT, dm = 0.1 V p-p, G = 2 220 MHz
VOUT, dm = 0.1 V p-p, G = 5 75 MHz
?3 dB Large Signal Bandwidth VOUT, dm = 2 V p-p, G = 1 25 MHz
VOUT, dm = 2 V p-p, G = 2 22 MHz
VOUT, dm = 2 V p-p, G = 5 19 MHz
Bandwidth for 0.1 dB Flatness VOUT, dm = 2 V p-p, G = 1 and G = 2 14.5 MHz
Slew Rate VOUT, dm = 2 V step 95 V/μs
Settling Time to 0.1% VOUT, dm = 2 V step 34 ns
Overdrive Recovery Time G = 2, VIN, dm = 6 V p-p, triangle wave 86 ns
NOISE/HARMONIC PERFORMANCE
HD2/HD3 VOUT, dm = 2 V p-p, fC = 10 kHz ?125/?118 dBc
VOUT, dm = 2 V p-p, fC = 50 kHz ?123/?126 dBc
VOUT, dm = 2 V p-p, fC = 50 kHz, G = 2 ?124/?117 dBc
VOUT, dm = 2 V p-p, fC = 1 MHz ?102/?96 dBc
VOUT, dm = 2 V p-p, fC = 1 MHz, G = 2 ?100/–92 dBc
IMD3 VOUT, dm = 2 V p-p, f1 = 1.9 MHz, f2 = 2.1 MHz ?99 dBc
Input Voltage Noise f = 100 kHz 3.9 nV/√Hz
Input Current Noise f = 100 kHz 0.81 pA/√Hz
Crosstalk VOUT, dm = 2 V p-p, fC = 1 MHz ?110 dB
INPUT CHARACTERISTICS
Input Offset Voltage VIP = VIN = VOCM = 0 V ?0.35 ±0.06 +0.35 mV
Input Offset Voltage Drift TMIN to TMAX 1.2 μV/°C
Input Bias Current ?1.6 ?1.1 μA
Input Bias Current Drift TMIN to TMAX ?4.5 nA/°C
Input Offset Current ?500 ±50 +500 nA
Input Common-Mode Voltage Range ?VS ? 0.2 to
+VS ? 1.2
V
Input Resistance Differential 33 k?
Common mode 50 M?
Input Capacitance 1 pF
Common-Mode Rejection Ratio (CMRR) ΔVOS, dm/ΔVIN, cm, ?VIN, cm = ±1 V dc 86 119 dB
Open-Loop Gain 91 99 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Each single-ended output ?VS + 0.1 to
+VS ? 0.1
?VS + 0.07 to
+VS ? 0.07
V
Linear Output Current f = 1 MHz, RL, dm = 22 ?, SFDR = ?60 dBc 46 mA peak
Output Balance Error f = 1 MHz, ΔVOUT, cm/ΔVOUT, dm ?65 ?60 dB
Data Sheet ADA4940-1/ADA4940-2
Rev. E | Page 5 of 30
V
OCM
to V
OUT, cm
Performance
Table 4.
Parameter Test Conditions/Comments Min Typ Max Unit
VOCM DYNAMIC PERFORMANCE
?3 dB Small Signal Bandwidth VOUT, cm = 0.1 V p-p 36 MHz
?3 dB Large Signal Bandwidth VOUT, cm = 1 V p-p 29 MHz
Slew Rate VOUT, cm = 1 V p-p 52 V/μs
Input Voltage Noise f = 100 kHz 83 nV/√Hz
Gain ΔVOUT, cm/ΔVOCM, ΔVOCM = ±1 V 0.99 1 1.01 V/V
VOCM CHARACTERISTICS
Input Common-Mode Voltage Range ?VS + 0.8 to
+VS ? 0.7
V
Input Resistance 250 k?
Offset Voltage VOS, cm = VOUT, cm ? VOCM; VIP = VIN = VOCM = 0 V ?6 ±1 +6 mV
Input Offset Voltage Drift TMIN to TMAX 20 μV/°C
Input Bias Current ?7 +4 +7 μA
CMRR ΔVOS, dm/ΔVOCM, ΔVOCM = ±1 V 86 100 dB
General Performance
Table 5.
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Operating Range LFCSP 3 7 V
SOIC 3 6 V
Quiescent Current per Amplifier Enabled 1.05 1.25 1.38 mA
Quiescent Current Drift TMIN to TMAX 4.25 μA/°C
Disabled 13.5 28.5 μA
+PSRR ΔVOS, dm/ΔVS, ΔVS = 1 V p-p 80 90 dB
?PSRR ΔVOS, dm/ΔVS, ΔVS = 1 V p-p 80 96 dB
DISABLE (DISABLE PIN)
DISABLE Input Voltage Disabled ≤(?VS + 1) V
Enabled ≥(?VS + 1.8) V
Turn-Off Time 10 μs
Turn-On Time 0.6 μs
DISABLE Pin Bias Current per Amplifier
Enabled DISABLE = +2.5 V 2 5 μA
Disabled DISABLE = ?2.5 V ?10 ?5 μA
OPERATING TEMPERATURE RANGE ?40 +125 °C
ADA4940-1/ADA4940-2 Data Sheet
Rev. E | Page 6 of 30
V
S
= 3 V
VOCM = midsupply, RF = RG = 1 k?, RL, dm = 1 k?, TA = 25°C, LFCSP package, unless otherwise noted. TMIN to TMAX = ?40°C to +125°C.
(See Figure 61 for the definition of terms.)
+D
IN
or nullD
IN
to V
OUT, dm
Performance
Table 6.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
?3 dB Small Signal Bandwidth VOUT, dm = 0.1 V p-p 240 MHz
VOUT, dm = 0.1 V p-p, G = 2 200 MHz
VOUT, dm = 0.1 V p-p, G = 5 70 MHz
?3 dB Large Signal Bandwidth VOUT, dm = 2 V p-p 24 MHz
VOUT, dm = 2 V p-p, G = 2 20 MHz
VOUT, dm = 2 V p-p, G = 5 17 MHz
Bandwidth for 0.1 dB Flatness VOUT, dm = 0.1 V p-p 14 MHz
Slew Rate VOUT, dm = 2 V step 90 V/μs
Settling Time to 0.1% VOUT, dm = 2 V step 37 ns
Overdrive Recovery Time G = 2, VIN, dm = 3.6 V p-p, triangle wave 85 ns
NOISE/HARMONIC PERFORMANCE
HD2/HD3 VOUT, dm = 2 V p-p, fC = 50 kHz (HD2/HD3) ?115/?121 dBc
VOUT, dm = 2 V p-p, fC = 1 MHz (HD2/HD3) ?104/?96 dBc
IMD3 VOUT, dm = 2 V p-p, f1 = 1.9 MHz, f2 = 2.1 MHz ?98 dBc
Input Voltage Noise f = 100 kHz 3.9 nV/√Hz
Input Current Noise f = 100 kHz 0.84 pA/√Hz
Crosstalk VOUT, dm = 2 V p-p, fC = 1 MHz ?110 dB
INPUT CHARACTERISTICS
Input Offset Voltage VIP = VIN = VOCM = 1.5 V ?0.4 ±0.06 +0.4 mV
Input Offset Voltage Drift TMIN to TMAX 1.2 μV/°C
Input Bias Current ?1.6 ?1.1 μA
Input Bias Current Drift TMIN to TMAX ?4.5 nA/°C
Input Offset Current ?500 ±50 +500 nA
Input Common-Mode Voltage Range ?VS ? 0.2 to
+VS ? 1.2
V
Input Resistance Differential 33 k?
Common mode 50 M?
Input Capacitance 1 pF
Common-Mode Rejection Ratio (CMRR) ΔVOS, dm/ΔVIN, cm, ?VIN, cm = ±0.25 V dc 86 114 dB
Open-Loop Gain 91 99 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Each single-ended output ?VS + 0.08 to
+VS ? 0.08
?VS + 0.04 to
+VS ? 0.04
V
Linear Output Current f = 1 MHz, RL, dm = 26 ?, SFDR = ?60 dBc 38 mA peak
Output Balance Error f = 1 MHz, ΔVOUT, cm/ΔVOUT, dm ?65 ?60 dB
Data Sheet ADA4940-1/ADA4940-2
Rev. E | Page 7 of 30
V
OCM
to V
OUT, cm
Performance
Table 7.
Parameter Test Conditions/Comments Min Typ Max Unit
VOCM DYNAMIC PERFORMANCE
?3 dB Small Signal Bandwidth VOUT, cm = 0.1 V p-p 36 MHz
?3 dB Large Signal Bandwidth VOUT, cm = 1 V p-p 26 MHz
Slew Rate VOUT, cm = 1 V p-p 48 V/μs
Input Voltage Noise f = 100 kHz 92 nV/√Hz
Gain ΔVOUT, cm/ΔVOCM, ΔVOCM = ±0.25 V 0.99 1 1.01 V/V
VOCM CHARACTERISTICS
Input Common-Mode Voltage Range ?VS + 0.8 to
+VS ? 0.7
V
Input Resistance 250 k?
Offset Voltage VOS, cm = VOUT, cm ? VOCM; VIP = VIN = VOCM = 1.5 V ?7 ±1 +7 mV
Input Offset Voltage Drift TMIN to TMAX 20 μV/°C
Input Bias Current ?5 +1 +5 μA
CMRR ΔVOS,dm/ΔVOCM, ΔVOCM = ±0.25 V 80 100 dB
General Performance
Table 8.
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Operating Range LFCSP 3 7 V
SOIC 3 6 V
Quiescent Current per Amplifier Enabled 1 1.18 1.33 mA
TMIN to TMAX 4.25 μA/°C
Disabled 7 22 μA
+PSRR ΔVOS, dm/ΔVS, ΔVS = 0.25 V p-p 80 90 dB
?PSRR ΔVOS, dm/ΔVS, ΔVS = 0.25 V p-p 80 96 dB
DISABLE (DISABLE PIN)
DISABLE Input Voltage Disabled ≤(?VS + 1) V
Enabled ≥(?VS + 1.8) V
Turn-Off Time 16 μs
Turn-On Time 0.6 μs
DISABLE Pin Bias Current per Amplifier
Enabled DISABLE = +3 V 0.3 1 μA
Disabled DISABLE = 0 V ?6 ?3 μA
OPERATING TEMPERATURE RANGE ?40 +125 °C
ADA4940-1/ADA4940-2 Data Sheet
Rev. E | Page 8 of 30
ABSOLUTE MAXIMUM RATINGS
Table 9.
Parameter Rating
Supply Voltage 8 V
VOCM ±VS
Differential Input Voltage 1.2 V
Operating Temperature Range ?40°C to +125°C
Storage Temperature Range ?65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
ESD
Field Induced Charged Device Model (FICDM) 1250 V
Human Body Model (HBM) 2000 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for the device soldered on a circuit board in still air.
Table 10.
Package Type θJA Unit
8-Lead SOIC (Single)/4-Layer Board 158 °C/W
16-Lead LFCSP (Single)/4-Layer Board 91.3 °C/W
24-Lead LFCSP (Dual)/4-Layer Board 65.1 °C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4940-1/
ADA4940-2 packages is limited by the associated rise in
junction temperature (TJ) on the die. At approximately 150°C,
which is the glass transition temperature, the plastic changes its
properties. Even temporarily exceeding this temperature limit
can change the stresses that the package exerts on the die,
permanently shifting the parametric performance of the
ADA4940-1/ADA4940-2. Exceeding a junction temperature
of 150°C for an extended period can result in changes in the
silicon devices, potentially causing failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power dissipation is the voltage between the supply pins (±VS)
times the quiescent current (IS). The load current consists of the
differential and common-mode currents flowing to the load, as
well as currents flowing through the external feedback networks
and internal common-mode feedback loop. The internal
resistor tap used in the common-mode feedback loop places a
negligible differential load on the output. Consider rms voltages
and currents when dealing with ac signals.
Airflow reduces θJA. In addition, more metal directly in contact
with the package leads from metal traces, through holes, ground,
and power planes reduces the θJA.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead SOIC (θJA =
158°C/W, single) the 16-lead LFCSP (θJA = 91.3°C/W, single)
and 24-lead LFCSP (θJA = 65.1° C / W, dual) packages on a JEDEC
standard 4-layer board. θJA values are approximations.
3.5
0
–40 –20 0 20 40 60 12010080
MA
XI
MU
M PO
W
ER
D
I
SSI
PA
T
I
O
N
(W
)
AMBIENT TEMPERATURE (°C) 08452-
004
0.5
1.0
1.5
2.0
2.5
3.0
ADA4940-2 (LFCSP)
ADA4940-1 (LFCSP)
ADA4940-1 (SOIC)
Figure 3. Maximum Safe Power Dissipation vs. Ambient Temperature
ESD CAUTION
Data Sheet ADA4940-1/ADA4940-2
Rev. E | Page 9 of 30
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
08452-
101NOTES
1. CONNECT THE EXPOSED PAD TO
–V
S
OR GROUND.
DISABLE–FB
+IN
–IN
+FB
–OUT
ADA4940-1
+OUT
V
OCM
+V
S
+V
S
+V
S
+V
S
–V
S
–V
S
–V
S
–V
S
PIN 1
INDICATOR
12
11
10
1
3
4 9
2
65 7 8
16 15 14 13
Figure 4. ADA4940-1 Pin Configuration (16-Lead LFCSP)
Table 11. ADA4940-1 Pin Function Descriptions (16-Lead LFCSP)
Pin No. Mnemonic Description
1 ?FB Negative Output for Feedback Component Connection.
2 +IN Positive Input Summing Node.
3 ?IN Negative Input Summing Node.
4 +FB Positive Output for Feedback Component Connection.
5 to 8 +VS Positive Supply Voltage.
9 VOCM Output Common-Mode Voltage.
10 +OUT Positive Output for Load Connection.
11 ?OUT Negative Output for Load Connection.
12 DISABLE Disable Pin.
13 to 16 ?VS Negative Supply Voltage.
Exposed pad (EPAD) Connect the exposed pad to ?VS or ground.
08452-
003
–IN 1
V
OCM
2
+V
S
3
+OUT 4
+IN8
DISABLE7
–V
S
6
–OUT5
ADA4940-1
Figure 5. ADA4940-1 Pin Configuration (8-Lead SOIC)
Table 12. ADA4940-1 Pin Function Descriptions (8-Lead SOIC)
Pin No. Mnemonic Description
1 ?IN Negative Input Summing Node
2 VOCM Output Common-Mode Voltage
3 +VS Positive Supply Voltage
4 +OUT Positive Output for Load Connection
5 ?OUT Negative Output for Load Connection
6 ?VS Negative Supply Voltage
7 DISABLE Disable Pin
8 +IN Positive Input Summing Node
ADA4940-1/ADA4940-2 Data Sheet
Rev. E | Page 10 of 30
08452-
102NOTES
1. CONNECT THE EXPOSED PAD TO
–V
S
OR GROUND.
–IN1
+FB1
+V
S1
+V
S1
–FB2
+IN2
–I
N2
+
F
B2
+V
S2
V
O
CM
2
+
OU
T2
+V
S2
–V
S1
–V
S1
–
F
B1
+
I
N1
DI
S
ABL
E
1
–O
UT
1
DISABLE2
–V
S2
–V
S2
V
OCM1
+OUT1
ADA4940-2
–OUT2
2
1
3
4
5
6
18
17
16
15
14
13
8 9
10
1
17
12
20 1921222324
Figure 6. ADA4940-2 Pin Configuration (24-Lead LFCSP)
Table 13. ADA4940-2 Pin Function Descriptions (24-Lead LFCSP)
Pin No. Mnemonic Description
1 ?IN1 Negative Input Summing Node 1.
2 +FB1 Positive Output Feedback Pin 1.
3, 4 +VS1 Positive Supply Voltage 1.
5 ?FB2 Negative Output Feedback Pin 2.
6 +IN2 Positive Input Summing Node 2.
7 ?IN2 Negative Input Summing Node 2.
8 +FB2 Positive Output Feedback Pin 2.
9, 10 +VS2 Positive Supply Voltage 2.
11 VOCM2 Output Common-Mode Voltage 2.
12 +OUT2 Positive Output 2.
13 ?OUT2 Negative Output 2.
14 DISABLE2 Disable Pin 2.
15, 16 ?VS2 Negative Supply Voltage 2.
17 VOCM1 Output Common-Mode Voltage 1.
18 +OUT1 Positive Output 1.
19 ?OUT1 Negative Output 1.
20 DISABLE1 Disable Pin 1.
21, 22 ?VS1 Negative Supply Voltage 1.
23 ?FB1 Negative Output Feedback Pin 1.
24 +IN1 Positive Input Summing Node 1.
Exposed pad (EPAD) Connect the exposed pad to ?VS or ground.
Data Sheet ADA4940-1/ADA4940-2
Rev. E | Page 11 of 30
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±2.5 V, G = 1, RF = RG = 1 k?, RT = 52.3 ? (when used), RL = 1 k?, unless otherwise noted. See Figure 59 and Figure 60 for the
test circuits.
3
–9
0.1 1 10 100 1000
NO
RM
AL
I
Z
E
D G
AI
N (
d
B)
FREQUENCY (MHz)
08452-
006
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
V
OUT, dm
= 0.1V p-p
G = 2, R
L
= 1kΩ
G = 2, R
L
= 200Ω
G = 1, R
L
= 200Ω
G = 1, R
L
= 1kΩ
Figure 7. Small Signal Frequency Response for Various Gains and Loads
(LFCSP)
08452-
007
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
0.1 1 10 100 1000
G
AI
N (
d
B)
FREQUENCY (MHz)
V
OUT, dm
= 0.1V p-p
V
S
= ±3.5V
V
S
= ±2.5V
V
S
= ±1.5V
Figure 8. Small Signal Frequency Response for Various Supplies (LFCSP)
Figure 9. Small Signal Frequency Response for Various Temperatures (LFCSP)
3
–9
0.1 1 10 100 1000
NO
RM
AL
I
Z
E
D G
AI
N (
d
B)
FREQUENCY (MHz)
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
V
OUT
= 2V p-p
G = 2, R
L
= 1kΩ
G = 1, R
L
= 1kΩ
08452-
009
G = 1, R
L
= 200Ω
G = 2, R
L
= 200Ω
Figure 10. Large Signal Frequency Response for Various Gains and Loads
08452-
010
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
0.1 1 10 100 1000
G
AI
N (
d
B)
FREQUENCY (MHz)
V
OUT
= 2V p-p
V
S
= ±3.5V
V
S
= ±2.5V
V
S
= ±1.5V
Figure 11. Large Signal Frequency Response for Various Supplies
3
–9
1 10 100 1000
G
AI
N (
d
B)
FREQUENCY (MHz)
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
V
OUT, dm
= 2V p-p
08452-
0
1
1
–40°C
+25°C
+125°C
Figure 12. Large Signal Frequency Response for Various Temperatures
3
–9
1 10 100 1000
G
AI
N (
d
B)
FREQUENCY (MHz)
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
V
OUT, dm
= 0.1V p-p
08452-
008
–40°C
+25°C
+125°C
ADA4940-1/ADA4940-2 Data Sheet
Rev. E | Page 12 of 30
08452-
012
4
3
–9
0.1 1 10 100 1000
G
AI
N (
d
B)
FREQUENCY (MHz)
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
V
OUT, dm
= 0.1V p-p
LFCSP-1
LFCSP-2:CH1
LFCSP-2: CH2
SOIC-1
Figure 13. Small Signal Frequency Response for Various Packages
3
–9
0.1 1 10 100 1000
G
AI
N (
d
B)
FREQUENCY (MHz)
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
V
OUT, dm
= 0.1V p-p
V
OCM
= 0V
V
OCM
= +1V
V
OCM
= –1V
08452-
013
Figure 14. Small Signal Frequency Response at Various VOCM Levels (LFCSP)
4
3
–9
0.1 1 10 100 1000
G
AI
N (
d
B)
FREQUENCY (MHz)
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
V
OUT, dm
= 0.1V p-p
08452-
205
V
OCM
= –1V
V
OCM
= 0V
V
OCM
= +1V
Figure 15. Small Signal Frequency Response for Various VOCM (SOIC)
3
–9
1 10 100 1000
G
AI
N (
d
B)
FREQUENCY (MHz)
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
V
OUT
= 2V p-p
08452-
015
LFCSP-1
LFCSP-2: CH1
LFCSP-2: CH2
SOIC-1
Figure 16. Large Signal Frequency Response for Various Packages
3
–9
0.1 1 10 100 1000
G
AI
N (
d
B)
FREQUENCY (MHz)
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
V
OCM
= –1V
V
OCM
= 0V
V
OCM
= +1V
08452-
016
V
OUT, dm
= 2V p-p
Figure 17. Large Signal Frequency Response at Various VOCM Levels
4
3
–9
0.1 1 10 100 1000
G
AI
N (
d
B)
FREQUENCY (MHz)
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
V
OUT, dm
= 0.1V p-p
08452-
203
LFCSP: R
L
= 1kΩ
LFCSP: R
L
= 200Ω
SOIC: R
L
= 1kΩ
SOIC: R
L
= 200Ω
Figure 18. Small Signal Frequency Response for Various Packages and Loads
Data Sheet ADA4940-1/ADA4940-2
Rev. E | Page 13 of 30
4
–9
1 10 100 1000
G
AI
N (
d
B)
FREQUENCY (MHz)
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
C
DIFF
= 0pF
V
OUT
= 0.1V p-p
C
COM1
= C
COM2
= 2pF
C
COM1
= C
COM2
= 0.5pF
C
COM1
= C
COM2
= 1pF
C
COM1
= C
COM2
= 0pF
08452-
014
Figure 19. Small Signal Frequency Response for Various Capacitive Loads
(LFCSP)
0.25
–0.25
0.1 10001 10 100
NO
RM
AL
I
Z
E
D G
AI
N (
d
B)
FREQUENCY (MHz)
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
V
OUT, dm
= 0.1V p-p
G = 2, R
L
= 200Ω
G = 2, R
L
= 1kΩ
G = 1, R
L
= 200Ω
G = 1, R
L
= 1kΩ
08452-
018
Figure 20. 0.1 dB Flatness Small Signal Frequency Response for
Various Gains and Loads (LFCSP)
3
–9
1 10 100 1000
G
AI
N (
d
B)
FREQUENCY (MHz)
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
V
S
= ±1.5V
V
S
= ±2.5V
08452-
019
V
OUT, dm
= 0.1V p-p
Figure 21. VOCM Small Signal Frequency Response for Various Supplies
4
–9
1 10 100 1000
G
AI
N (
d
B)
FREQUENCY (MHz)
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
C
COM1
= C
COM2
= 0pF
C
COM1
= C
COM2
= 0.5pF
C
COM1
= C
COM2
= 1pF
C
COM1
= C
COM2
= 2pF
C
DIFF
= 0pF
V
OUT
= 2V p-p
08452-
017
Figure 22. Large Signal Frequency Response for Various Capacitive Loads
0.25
–0.25
0.1 10001 10 100
NO
RM
AL
I
Z
E
D G
AI
N (
d
B)
FREQUENCY (MHz)
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
V
OUT, dm
= 2V p-p
G = 1, R
L
= 1kΩ
G = 1, R
L
= 200Ω
G = 2, R
L
= 1kΩ
G = 2, R
L
= 200Ω
08452-
021
Figure 23. 0.1 dB Flatness Large Signal Frequency Response for
Various Gains and Loads
3
–9
1 10 100 1000
G
AI
N (
d
B)
FREQUENCY (MHz)
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
V
S
= ±1.5V
V
S
= ±2.5V
08452-
022
V
OUT, dm
= 1V p-p
Figure 24. VOCM Large Signal Frequency Response for Various Supplies
ADA4940-1/ADA4940-2 Data Sheet
Rev. E | Page 14 of 30
–20
–130
0.01 0.1 1 10
HARM
O
NI
C DI
S
T
O
RT
I
O
N (
d
Bc)
FREQUENCY (MHz)
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
V
OUT, dm
= 2V p-p
HD3, G = 2
HD3, G = 1
HD2, G = 1
08452-
023
HD2, G = 2
Figure 25. Harmonic Distortion vs. Frequency for Various Gains (LFCSP)
–20
–130
0.01 0.1 1 10
HARM
O
NI
C DI
S
T
O
RT
I
O
N (
d
Bc)
FREQUENCY (MHz)
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
V
OUT, dm
= 2V p-p
HD3, R
L
= 200?
HD3, R
L
= 1k?
HD2, R
L
= 1k?
HD2, R
L
= 200?
08452-
020
Figure 26. Harmonic Distortion vs. Frequency for Various Loads (LFCSP)
–20
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
08452-
0240.01 0.1 1 10
HARM
O
NI
C DI
S
T
O
RT
I
O
N (
d
Bc)
FREQUENCY (MHz)
V
OUT, dm
= 2V p-p
HD2, V
S
= ±1.5V
HD3, V
S
= ±3.5V
HD3, V
S
= ±2.5V
HD2, V
S
= ±2.5V
HD3, V
S
= ±1.5V
HD2, V
S
= ±3.5V
Figure 27. Harmonic Distortion vs. Frequency for Various Supplies (LFCSP)
–20
–130
0.01 0.1 1 10
HARM
O
NI
C DI
S
T
O
RT
I
O
N (
d
Bc)
FREQUENCY (MHz)
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
08452-
200
HD2, G = 1
HD3, G = 1
HD2, G = 2
HD3, G = 2
V
OUT, dm
= 2V p-p
Figure 28. Harmonic Distortion vs. Frequency vs. Gain (SOIC)
–20
–130
0.01 0.1 1 10
HARM
O
NI
C DI
S
T
O
RT
I
O
N (
d
Bc)
FREQUENCY (MHz)
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
08452-
201
HD2, R
L
= 1kΩ
HD3, R
L
= 1kΩ
HD2, R
L
= 200Ω
HD3, R
L
= 200Ω
V
OUT, dm
= 2V p-p
Figure 29. Harmonic Distortion vs. Frequency for Various Loads (SOIC)
–20
–130
0.01 0.1 1 10
HARM
O
NI
C DI
S
T
O
RT
I
O
N (
d
Bc)
FREQUENCY (MHz)
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
08452-
202
HD2, ±2.5V
HD3, ±2.5V
HD2, ±1.5V
HD3, ±1.5V
V
OUT, dm
= 2V p-p
Figure 30. Harmonic Distortion vs. Frequency for Various Supplies (SOIC)
Data Sheet ADA4940-1/ADA4940-2
Rev. E | Page 15 of 30
–20
–130
0.01 0.1 1 10
S
P
URI
O
US
-
F
RE
E
DY
NAM
I
C RANG
E
(
d
Bc)
FREQUENCY (MHz)
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
08452-
030
V
OUT, dm
= 2V p-p
LFCSP: R
L
= 1kΩ
LFCSP: R
L
= 200Ω
SOIC: R
L
= 1kΩ
SOIC: R
L
= 200Ω
Figure 31. Spurious-Free Dynamic Range vs. Frequency at
RL = 200 ? and RL = 1 k?
–20
–150
–2.5 2.5
HARM
O
NI
C DI
S
T
O
RT
I
O
N (
d
Bc)
V
OCM
(V)
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0
V
OUT, dm
= 2V p-p
HD2 AT 1MHz
HD2 AT 100kHz
HD3 AT 1MHz
HD3 AT 100kHz
08452-
025
Figure 32. Harmonic Distortion vs. VOCM for 100 kHz and 1 MHz,
±2.5 V Supplies (LFCSP)
–20
–130
0.01 0.1 1 10
HARM
O
NI
C DI
S
T
O
RT
I
O
N (
d
Bc)
FREQUENCY (MHz)
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30 HD3 AT V
OUT, dm
= 8V p-p
HD2 AT V
OUT, dm
= 8V p-p
HD2 AT V
OUT, dm
= 4V p-p
HD2 AT V
OUT, dm
= 2V p-p
HD3 AT V
OUT, dm
= 2V p-p
08452-
026
HD3 AT V
OUT, dm
= 4V p-p
Figure 33. Harmonic Distortion vs. Frequency for Various VOUT, dm (LFCSP)
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
0 1 2 3 4 5 6 7 8 9 10
HARM
O
NI
C DI
S
T
OR
TION
(
dB
c
)
V
OUT, dm
(V p-p)
V
S
= ±1.5V HD3
V
S
= +3V, 0V HD3
V
S
= +3V, 0V HD2
V
S
= ±3.5V HD3
V
S
= ±2.5V HD3
V
S
= ±3.5V HD2
V
S
= ±1.5V HD2
f = 1MHz
08452-
027
V
S
= ±2.5V HD2
Figure 34. Harmonic Distortion vs. VOUT, dm for Various Supplies, f = 1 MHz
(LFCSP)
–20
–140
0 3.02.5
HARM
O
NI
C DI
S
T
O
RT
I
O
N (
d
Bc)
V
OCM
(V)
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
0.5 1.0 1.5 2.0
+V
S
= +3V, –V
S
= 0V
V
OUT, dm
= 2V p-p
HD2 AT 1MHz
HD3 AT 1MHz
HD3 AT 100kHz
HD2 AT 100kHz
08452-
028
Figure 35. Harmonic Distortion vs. VOCM for 100 kHz and 1 MHz, 3 V Supply
(LFCSP)
–20
–140
0.01 0.1 1 10
HARM
O
NI
C DI
S
T
O
RT
I
O
N (
d
Bc)
FREQUENCY (MHz)
–120
–130
–110
–100
–90
–80
–70
–60
–50
–40
–30
V
OUT, dm
= 2V p-p
08452-
029
HD3, R
F
= R
G
= 499?
HD2, R
F
= R
G
= 499?
HD3, R
F
= R
G
= 1k?
HD2, R
F
= R
G
= 1k?
Figure 36. Harmonic Distortion vs. Frequency for Various RF and RG (LFCSP)
ADA4940-1/ADA4940-2 Data Sheet
Rev. E | Page 16 of 30
10
0
–120
–110
1.5 2.5
NO
RM
AL
I
Z
E
D S
P
E
CT
RUM
(
d
Bc)
FREQUENCY (MHz) 08452-
033
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.42.3
V
OUT, dm
= 2V p-p
(ENVELOPE)
Figure 37. 2 MHz Intermodulation Distortion (LFCSP)
130
40
50
60
70
80
90
100
110
120
0.1 1 10 100
CM
RR (
d
B)
FREQUENCY (MHz)
08452-
100
SOIC
LFCSP
Figure 38. CMRR vs. Frequency
–10
–80
0.1 1 10 100
O
UT
P
UT
BAL
ANCE
(
d
B)
FREQUENCY (MHz)
–70
–60
–50
–20
–30
–40
08452-
032
V
OUT, dm
= 2V p-p
Figure 39. Output Balance vs. Frequency
–60
–130
0.1 1 10 100
CRO
S
S
T
AL
K (
d
B)
FREQUENCY (MHz)
–120
–110
–100
–70
–80
–90
08452-
039
CHANNEL 1 TO CHANNEL 2
CHANNEL 2 TO CHANNEL 1
V
OUT, dm
= 2V p-p
Figure 40. Crosstalk vs. Frequency, ADA4940-2
120
20
0.1 1 10 100
P
S
RR (
d
B)
FREQUENCY (MHz)
30
40
50
60
70
80
110
90
100
08452-
034
+PSRR
–PSRR
Figure 41. PSRR vs. Frequency
100
–40
0
–210
10k 100k 1M 10M 100M 1G
G
AI
N (
d
B)
P
HAS
E
(
Deg
rees)
FREQUENCY (Hz) 08452-
035
–195
–180
–165
–150
–135
–120
–105
–90
–75
–60
–45
–30
–15
–30
–20
–10
0
10
20
30
40
50
60
70
80
90
Figure 42. Open-Loop Gain and Phase vs. Frequency
Data Sheet ADA4940-1/ADA4940-2
Rev. E | Page 17 of 30
8
–8
–6
–4
0
2
4
6
–2
0 1000
OU
TP
U
T V
OLTA
GE
(
V
)
TIME (ns) 08452-
041
100 200 300 400 500 600 700 800 900
G = +2
V
OUT, dm
2 × V
IN
Figure 43. Output Overdrive Recovery, G = 2
100
10
1
10 100 1k 10k 100k 1M 10M
IN
P
U
T V
OLTA
GE
N
OIS
E
(
nV
/√
H
z
)
FREQUENCY (Hz)
08452-
037
Figure 44. Voltage Noise Spectral Density, Referred to Input
1.50
–1.25
0
–2.75
0 100
OU
TP
U
T V
OLTA
GE
(
V
)
D
I
SA
B
L
E PI
N
VO
L
T
A
G
E (V)
TIME (μs)
08452-
038
–2.50
–2.25
–2.00
–1.75
–1.50
–1.25
–1.00
–0.75
–0.50
–0.25
–1.00
–0.75
–0.50
–0.25
0
0.25
0.50
0.75
1.00
1.25
10 20 30 40 50 60 70 80 90
–OUT, V
ICM
= 1V
+OUT, V
ICM
= 1V
DISABLE
+IN –OUT
+OUT
–FB
+FB
–IN
V
OCM
0.1μF
R1 R2
R2
+2.5V
–2.5V
R1
V
ICM
DISABLE
0V
–2.5V
Figure 45. DISABLE Pin Turn-Off Time
2.0
–2.0
0.5
–0.5
0 80
VO
L
T
A
G
E (V)
E
RRO
R (
%)
TIME (ns)
08452-
065
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
–1.6
–1.2
–0.8
–0.4
0
0.4
0.8
1.2
1.6
10 20 30 40 50 60 70
%ERROR
OUTPUT
INPUT
V
OUT, dm
= 2V p-p
Figure 46. 0.1% Settling Time
100
10
1
0.1
0.01
0.1 1 10 100
O
UT
P
UT
I
M
P
E
DANCE
(
?
)
FREQUENCY (MHz) 08452-
040
Figure 47. Closed-Loop Output Impedance Magnitude vs. Frequency, G = 1
2.50
–0.25 –2.75
0 2.0
OU
TP
U
T V
OLTA
GE
(
V
)
D
I
SA
B
L
E PI
N
VO
L
T
A
G
E (V)
TIME (μs)
08452-
057
–2.50
–2.25
–2.00
–1.75
–1.50
–1.25
–1.00
–0.75
–0.50
–0.25
0
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
–OUT, V
ICM
= 1V
DISABLE
+OUT, V
ICM
= 1V
+IN –OUT
+OUT
–FB
+FB
–IN
VOCM
0.1μF
R1 R2
R2
+2.5V
–2.5V
R1
VICM
DISABLE
0V
–2.5V
Figure 48. DISABLE Pin Turn-On Time
ADA4940-1/ADA4940-2 Data Sheet
Rev. E | Page 18 of 30
100
–100
0 150
OU
TP
U
T V
OLTA
GE
(
m
V
)
TIME (ns)
–80
–60
–40
–20
0
20
40
60
80
10 20 30 40 50 60 70 80 90 100 110 120 130 140
V
OUT, dm
= 0.1V p-p
G = 2, R
L
= 1kΩ
G = 1, R
L
= 1kΩ
G = 1, R
L
= 200Ω
G = 2, R
L
= 200Ω
08452-
042
Figure 49. Small Signal Transient Response for Various Gains and Loads
(LFCSP)
–100
–80
–60
–40
–20
0
20
40
60
80
100
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
OU
TP
U
T V
O
LT
A
G
E (m
V)
TIME (ns)
V
OUT, dm
= 0.1V
V
S
= ±1.5V
V
S
= ±3.5V
V
S
= ±2.5V
08452-
043
Figure 50. Small Signal Transient Response for Various Supplies (LFCSP)
100
–100
0 150
OU
TP
U
T V
OLTA
GE
(
m
V
)
TIME (ns)
–80
–60
–40
–20
0
20
40
60
80
10 20 30 40 50 60 70 80 90 100 110 120 130 140
C
DIFF
= 0pF
V
OUT, dm
= 0.1V p-p
C
COM1
= C
COM2
= 0pF
C
COM1
= C
COM2
= 0.5pF
C
COM1
= C
COM2
= 1pF
C
COM1
= C
COM2
= 2pF
08452-
044
Figure 51. Small Signal Transient Response for Various Capacitive Loads
(LFCSP)
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
OU
TP
U
T V
OLTA
GE
(
V
)
TIME (ns)
V
OUT, dm
= 2V p-p
G = 1, R
L
= 1kΩ
G = 1, R
L
= 200Ω
G = 2, R
L
= 1kΩ
G = 2, R
L
= 200Ω
08452-
045
0 30020 40 60 80 100 120 140 160 180 200 220 240 260 280
Figure 52. Large Signal Transient Response for Various Gains and Loads
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300
OU
TP
U
T V
O
LT
A
G
E (V)
TIME (ns)
V
OUT, dm
= 2V p-p
V
S
= ±3.5V
V
S
= ±1.5V
V
S
= ±2.5V
08452-
046
Figure 53. Large Signal Transient Response for Various Supplies
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
OU
TP
U
T V
OLTA
GE
(
V
)
TIME (ns)
C
DIFF
= 0pF
V
OUT, dm
= 2V p-p
C
COM1
= C
COM2
= 0pF
C
COM1
= C
COM2
= 0.5pF
C
COM1
= C
COM2
= 1pF
C
COM1
= C
COM2
= 2pF
08452-
047
0 30020 40 60 80 100 120 140 160 180 200 220 240 260 280
Figure 54. Large Signal Transient Response for Various Capacitive Loads
Data Sheet ADA4940-1/ADA4940-2
Rev. E | Page 19 of 30
100
–100
–80
–60
–40
–20
0
20
40
60
80
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
OU
TP
U
T V
OLTA
GE
(
m
V
)
TIME (ns)
V
OUT, dm
= 0.1V p-p
08452-
204
LFCSP-1
LFCSP-2: CH1
LFCSP-2: CH2
SOIC-1
Figure 55. Small Signal Transient Response for Various Packages, CL = 0 pF
100
–100
0 150
OU
TP
U
T V
OLTA
GE
(
m
V
)
TIME (ns)
–80
–60
–40
–20
0
20
40
60
80
10 20 30 40 50 60 70 80 90 100 110 120 130 140
V
OUT, dm
= 0.1V p-p
V
S
= ±1.5V
V
S
= ±2.5V
08452-
048
Figure 56. VOCM Small Signal Transient Response
100
–100
–80
–60
–40
–20
0
20
40
60
80
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
OU
TP
U
T V
OLTA
GE
(
m
V
)
TIME (ns)
V
OUT, dm
= 0.1V p-p
08452-
206
LFCSP-1
LFCSP-2: CH1
LFCSP-2: CH2
SOIC-1
Figure 57. Small Signal Transient Response for Various Packages, CL = 2 pF
1.00
–1.00
0 300
OU
TP
U
T V
OLTA
GE
(
V
)
TIME (ns)
–0.75
–0.50
–0.25
0
0.25
0.50
0.75
20 40 60 80 100 120 140 160 180 200 220 240 260 280
V
OUT, dm
= 1V p-p
V
S
= ±1.5V
V
S
= ±2.5V
08452-
053
Figure 58. VOCM Large Signal Transient Response
ADA4940-1/ADA4940-2 Data Sheet
Rev. E | Page 20 of 30
TEST CIRCUITS
ADA4940-1/
ADA4940-2
54.9?
475?
475?
54.9?
+2.5V
–2.5V
1k?
1k?50?
NETWORK
ANALYZER
OUTPUT
NETWORK
ANALYZER
INPUT
1k?
1k?
V
OCM
52.3?
25.5?
V
IN
08452-
067
50?
50?
Figure 59. Equivalent Basic Test Circuit
ADA4940-1/
ADA4940-2
+2.5V
–2.5V
1k?
1k?50?
1k?
475?
475?
1k?
V
OCM
52.3?
54.9?
54.9?
100?
HP
LP
2:1
50?
CT
V
IN
LOW-PASS
FILTER
DC-COUPLED
GENERATOR
DUAL
FILTER
08452-
056
25.5?
Figure 60. Test Circuit for Distortion Measurements
Data Sheet ADA4940-1/ADA4940-2
Rev. E | Page 21 of 30
TERMINOLOGY
DEFINITION OF TERMS
ADA4940-1/
ADA4940-2
R
L, dm
V
OUT, dm
R
F
R
F
R
G
R
G
+FB
+IN
+OUT
–OUT
–
+
+D
IN
+V
OCM
–D
IN
–FB
–IN
08
452
-
090
Figure 61. Circuit Definitions
Differential Voltage
Differential voltage refers to the difference between two node
voltages. For example, the differential output voltage (or
equivalently, output differential mode voltage) is defined as
VOUT, dm = (V+OUT ? V?OUT)
where V+OUT and V?OUT refer to the voltages at the +OUT and
?OUT terminals with respect to a common reference.
Similarly, the differential input voltage is defined as
VIN, dm = (+DIN ? (?DIN))
Common-Mode Voltage (CMV)
CMV refers to the average of two node voltages. The output
common-mode voltage is defined as
VOUT, cm = (V+OUT + V?OUT)/2
Similarly, the input common-mode voltage is defined as
VIN, cm = (+DIN + (?DIN))/2
Common-Mode Offset Voltage
The common-mode offset voltage is defined as the difference
between the voltage applied to the VOCM terminal and the
common mode of the output voltage.
VOS, cm = VOUT, cm ? VOCM
Differential V
OS
, Differential CMRR, and V
OCM
CMRR
The differential mode and common-mode voltages each have
their own error sources. The differential offset (VOS, dm) is the
voltage error between the +IN and ?IN terminals of the amplifier.
Differential CMRR reflects the change of VOS, dm in response to
changes to the common-mode voltage at the input terminals
+DIN and ?DIN.
dmOS,
cmIN,
DIFF
ΔV
ΔV
CMRR ?
VOCM CMRR reflects the change of VOS, dm in response to
changes to the common-mode voltage at the output terminals.
dmOS,
OCM
V
ΔV
ΔV
CMRR
OCM
?
Balance
Balance is a measure of how well the differential signals are
matched in amplitude; the differential signals are exactly 180°
apart in phase. By this definition, the output balance is the
magnitude of the output common-mode voltage divided by
the magnitude of the output differential mode voltage.
dmOUT
cmOUT
V
V
ErrorBalanceOutput
,
,
?
ADA4940-1/ADA4940-2 Data Sheet
Rev. E | Page 22 of 30
THEORY OF OPERATION
The ADA4940-1/ADA4940-2 are high speed, low power
differential amplifiers fabricated on Analog Devices advanced
dielectrically isolated SiGe bipolar process. They provide two
closely balanced differential outputs in response to either
differential or single-ended input signals. An external feedback
network that is similar to a voltage feedback operational
amplifier sets the differential gain. The output common-mode
voltage is independent of the input common-mode voltage and
is set by an external voltage at the VOCM terminal. The PNP
input stage allows input common-mode voltages between the
negative supply and 1.2 V below the positive supply. A rail-to-
rail output stage supplies a wide output voltage range.
The DISABLE pin can reduce the supply current of the
amplifier to 13.5 μA.
Figure 62 shows the ADA4940-1/ADA4940-2 architecture.
The differential feedback loop consists of the differential trans-
conductance GDIFF working through the GO output buffers and
the RF/RG feedback networks. The common-mode feedback
loop is set up with a voltage divider across the two differential
outputs to create an output voltage midpoint and a common-
mode transconductance, GCM.
08452-
058
G
O
C
C
C
C
R
F
R
G
G
CM
G
DIFF
G
O
R
G
V
REF
–OUT
+OUT
R
F
+D
IN
–D
IN
+IN
–IN V
OCM
Figure 62. ADA4940-1/ADA4940-2 Architectural Block
The differential feedback loop forces the voltages at +IN and ?IN
to equal each other. This fact sets the following relationships:
F
OUT
G
IN
R
V
R
D
?
?=
+
F
OUT
G
IN
R
V
R
D
+
?=
?
Subtracting the previous equations gives the relationship that
shows RF and RG setting the differential gain.
(V+OUT ? V?OUT) = (+DIN – (?DIN)) ×
G
F
R
R
The common-mode feedback loop drives the output common-
mode voltage that is sampled at the midpoint of the output
voltage divider to equal the voltage at VOCM. This results in the
following relationships:
V+OUT = VOCM +
2
dmOUT,
V
V?OUT = VOCM ?
2
dmOUT,
V
Note that the differential amplifier’s summing junction input
voltages, +IN and ?IN, are set by both the output voltages and
the input voltages.
?
?
?
?
?
?
?
?
+
+
?
?
?
?
?
?
?
?
+
+=
?+
GF
G
OUT
GF
F
ININ
RR
R
V
RR
R
DV
?
?
?
?
?
?
?
?
+
+
?
?
?
?
?
?
?
?
+
?=
+?
GF
G
OUT
GF
F
ININ
RR
R
V
RR
R
DV
Data Sheet ADA4940-1/ADA4940-2
Rev. E | Page 23 of 30
APPLICATIONS INFORMATION
ANALYZING AN APPLICATION CIRCUIT
The ADA4940-1/ADA4940-2 use open-loop gain and negative
feedback to force their differential and common-mode output
voltages in such a way as to minimize the differential and common-
mode error voltages. The differential error voltage is defined as
the voltage between the differential inputs labeled +IN and ?IN (see
Figure 61). For most purposes, this voltage is zero. Similarly, the
difference between the actual output common-mode voltage and
the voltage applied to VOCM is also zero. Starting from these two
assumptions, any application circuit can be analyzed.
SETTING THE CLOSED-LOOP GAIN
Determine the differential mode gain of the circuit in Figure 61
by using the following equation:
G
F
dmIN
dmOUT
R
R
V
V
=
,
,
This assumes that the input resistors (RG) and feedback resistors
(RF) on each side are equal.
ESTIMATING THE OUTPUT NOISE VOLTAGE
Estimate the differential output noise of the ADA4940-1/
ADA4940-2 by using the noise model in Figure 63. The input-
referred noise voltage density, vnIN, is modeled as a differential
input, and the noise currents, inIN? and inIN+, appear between
each input and ground. The noise currents are assumed equal
and produce a voltage across the parallel combination of the gain
and feedback resistances. vnCM is the noise voltage density at the
VOCM pin. Each of the four resistors contributes (4kTRx)
1/2
. Table 14
summarizes the input noise sources, the multiplication factors,
and the output-referred noise density terms. For more noise
calculation information, go to the Analog Devices Differential
Amplifier Calculator (DiffAmpCalc?), click
ADIDiffAmpCalculator.zip, and follow the on-screen prompts.
ADA4940-1/
ADA4940-2
+
R
F2
V
nOD
V
nCM
V
OCM
V
nIN
R
F1
R
G2
R
G1
V
nRF1
V
nRF2
V
nRG1
V
nRG2
i
nIN+
i
nIN–
08452-
050
Figure 63. ADA4940-1/ADA4940-2 Noise Model
As with conventional op amp, the output noise voltage densities
can be estimated by multiplying the input-referred terms at +IN
and ?IN by the appropriate output factor,
where:
( )
21
N
ββ
G
+
=
2
is the circuit noise gain.
G1F1
G1
1
RR
R
β
+
= and
G2F2
G2
2
RR
R
β
+
= are the feedback factors.
When RF1/RG1 = RF2/RG2, then β1 = β2 = β, and the noise gain
becomes
G
F
N
R
R
β
G +== 1
1
Note that the output noise from VOCM goes to zero in this case.
The total differential output noise density, vnOD, is the root-sum-
square of the individual output noise terms.
∑
=
=
8
1i
2
nOinOD
vv
Table 14. Output Noise Voltage Density Calculations
Input Noise Contribution Input Noise Term
Input Noise
Voltage Density
Output
Multiplication Factor
Output-Referred Noise
Voltage Density Term
Differential Input vnIN vnIN GN vnO1 = GN (vnIN)
Inverting Input inIN? inIN? × (RG2||RF2) GN vnO2 = GN [inIN? × (RG2||RF2)]
Noninverting Input inIN+ inIN+ × (RG1||RF1) GN vnO3 = GN [inIN+ × (RG1||RF1)]
VOCM Input vnCM vnCM GN (β1 ? β2) vnO4 = GN (β1 ? β2)(vnCM)
Gain Resistor RG1 vnRG1 (4kTRG1)
1/2
GN (1 ? β2) vnO5 = GN (1 ? β2)(4kTRG1)
1/2
Gain Resistor RG2 vnRG2 (4kTRG2)
1/2
GN (1 ? β1) vnO6 = GN (1 ? β1)(4kTRG2)
1/2
Feedback Resistor RF1 vnRF1 (4kTRF1)
1/2
1 vnO7 = (4kTRF1)
1/2
Feedback Resistor RF2 vnRF2 (4kTRF2)
1/2
1 vnO8 = (4kTRF2)
1/2
ADA4940-1/ADA4940-2 Data Sheet
Rev. E | Page 24 of 30
Table 15 and Table 16 list several common gain settings, recommended resistor values, input impedances, and output noise density for both
balanced and unbalanced input configurations.
Table 15. Differential Ground-Referenced Input, DC-Coupled, RL = 1 k? (See Figure 64)
Nominal Gain (dB) RF (?) RG (?) RIN, dm (?) Differential Output Noise Density (nV/√Hz) RTI (nV/√Hz)
0 1000 1000 2000 11.3 11.3
6 1000 500 1000 15.4 7.7
10 1000 318 636 20.0 6.8
14 1000 196 392 27.7 5.5
Table 16. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50 ?, RL = 1 k? (See Figure 65)
Nominal Gain (dB) RF (?) RG (?) RT (?) RIN, se (?) RG1 (?)
1
Differential Output Noise Density (nV/√Hz) RTI (nV/√Hz)
0 1000 1000 52.3 1333 1025 11.2 11.2
6 1000 500 53.6 750 526 15.0 7.5
10 1000 318 54.9 512 344 19.0 6.3
14 1000 196 59.0 337 223 25.3 5
1
RG1 = RG + (RS||RT)
IMPACT OF MISMATCHES IN THE FEEDBACK
NETWORKS
Even if the external feedback networks (RF/RG) are mismatched,
the internal common-mode feedback loop still forces the outputs
to remain balanced. The amplitudes of the signals at each output
remain equal and 180° out of phase. The input-to-output,
differential mode gain varies proportionately to the feedback
mismatch, but the output balance is unaffected.
As well as causing a noise contribution from VOCM, ratio-matching
errors in the external resistors result in a degradation of the ability
of the circuit to reject input common-mode signals, much the
same as for a four resistors difference amplifier made from a
conventional op amp.
In addition, if the dc levels of the input and output common-
mode voltages are different, matching errors result in a small
differential mode, output offset voltage. When G = 1, with a
ground-referenced input signal and the output common-mode
level set to 2.5 V, an output offset of as much as 25 mV (1% of
the difference in common-mode levels) can result if 1% tolerance
resistors are used. Resistors of 1% tolerance result in a worst-
case input CMRR of about 40 dB, a worst-case differential mode
output offset of 25 mV due to the 2.5 V level-shift, and no
significant degradation in output balance error.
CALCULATING THE INPUT IMPEDANCE OF AN
APPLICATION CIRCUIT
The effective input impedance of a circuit depends on whether
the amplifier is being driven by a single-ended or differential
signal source. For balanced differential input signals, as shown
in Figure 64, the input impedance (RIN, dm) between the inputs
(+DIN and ?DIN) is simply RIN, dm = 2 × RG.
For an unbalanced, single-ended input signal (see Figure 65),
the input impedance is
( )
?
?
?
?
?
?
?
?
?
?
?
?
+×
?
=
FG
F
G
seIN
RR
R
R
R
2
1
,
+V
S
ADA4940-1/
ADA4940-2
+IN
–IN
R
F
R
F
+D
IN
–D
IN
V
OCM
R
G
R
G
V
OUT, dm
08452-
051
Figure 64. ADA4940-1/ADA4940-2 Configured for Balanced (Differential) Inputs
R
T
R
S
ADA4940-1/
ADA4940-2
+V
S
R
F
R
GRS
R
G
R
F
V
OCM
R
T
V
OUT, dm
08452-
052
+IN
–IN
Figure 65. ADA4940-1/ADA4940-2 Configured for
Unbalanced (Single-Ended) Input
The input impedance of the circuit is effectively higher than it
would be for a conventional op amp connected as an inverter
because a fraction of the differential output voltage appears at
the inputs as a common-mode signal, partially bootstrapping
the voltage across the input resistor RG1.
Data Sheet ADA4940-1/ADA4940-2
Rev. E | Page 25 of 30
Terminating a Single-Ended Input
This section describes how to properly terminate a single-ended
input to the ADA4940-1/ADA4940-2 with a gain of 1, RF = 1 k?
and RG = 1 k?. An example using an input source with a terminated
output voltage of 1 V p-p and source resistance of 50 ? illustrates
the three steps that must be followed. Because the terminated
output voltage of the source is 1 V p-p, the open-circuit output
voltage of the source is 2 V p-p. The source shown in Figure 66
indicates this open-circuit voltage.
R
S
50?
V
S
2V p-p
R
IN, se
1.33k?
ADA4940-1
ADA4940-2
R
L
V
OUT, dm
+V
S
–V
S
R
G
1k?
R
G
1k?
R
F
1k?
R
F
1k?
V
OCM
08452-
059
Figure 66. Calculating Single-Ended Input Impedance, RIN
1. The input impedance is calculated by
Ωk.331
)10001000(2
1000
1
1000
)(2
1
,
=
?
?
?
?
?
?
?
?
?
?
?
?
+×
?
=
?
?
?
?
?
?
?
?
?
?
?
?
+×
?
=
FG
F
G
seIN
RR
R
R
R
2. To match the 50 ? source resistance, calculate the
termination resistor, RT, using RT||1.33 k? = 50 ?.
The closest standard 1% value for RT is 52.3 ?.
ADA4940-1
ADA4940-2
R
L
V
OUT, dm
+V
S
–V
S
R
S
50?
R
G
1k?
R
G
1k?
R
F
1k?
R
F
1k?
V
OCM
V
S
2V p-p
R
IN, se
50?
R
T
52.3?
08452-
060
Figure 67. Adding Termination Resistor RT
3. Figure 67 shows that the effective RG in the upper feedback
loop is now greater than the RG in the lower loop due to the
addition of the termination resistors. To compensate for the
imbalance of the gain resistors, add a correction resistor (RTS)
in series with RG in the lower loop. RTS is the Thevenin
equivalent of the source resistance, RS, and the termination
resistance, RT, and is equal to RS||RT.
R
S
50?
V
S
2V p-p
R
T
52.3?
R
TH
25.5?
V
TH
1.02V p-p
08452-
061
Figure 68. Calculating the Thevenin Equivalent
RTS = RTH = RS||RT = 25.5 ?. Note that VTH is greater than
1 V p-p, which was obtained with RT = 50 ?. The modified
circuit with the Thevenin equivalent (closest 1% value used for
RTH) of the terminated source and RTS in the lower feedback
loop is shown in Figure 69.
ADA4940-1
ADA4940-2
R
L
V
OUT, dm
+V
S
–V
S
R
TH
25.5?
R
G
1k?
R
G
1k?
R
F
1k?
R
F
1k?
V
OCM
V
TH
1.02V p-p
R
TS
25.5?
08452-
062
Figure 69. Thevenin Equivalent and Matched Gain Resistors
Figure 69 presents a tractable circuit with matched feedback
loops that can be easily evaluated.
It is useful to point out two effects that occur with a terminated
input. The first is that the value of RG is increased in both loops,
lowering the overall closed-loop gain. The second is that VTH
is a little larger than 1 V p-p, as it would be if RT = 50 ?.
These two effects have opposite impacts on the output voltage,
and for large resistor values in the feedback loops (~1 k?), the
effects essentially cancel each other out. For small RF and RG,
or high gains, however, the diminished closed-loop gain is not
cancelled completely by the increased VTH. This can be seen by
evaluating Figure 69.
The desired differential output in this example is 1 V p-p
because the terminated input signal was 1 V p-p and the
closed-loop gain = 1. The actual differential output voltage,
however, is equal to (1.02 V p-p)(1000/1025.5) = 0.996 V p-p.
This is within the tolerance of the resistors, so no change to
the feedback resistor, RF, is required.
INPUT COMMON-MODE VOLTAGE RANGE
The ADA4940-1/ADA4940-2 input common-mode range is
shifted down by approximately 1 VBE, in contrast to other ADC
drivers with centered input ranges, such as the ADA4939-1/
ADA4939-2. The downward-shifted input common-mode range
is especially suited to dc-coupled, single-ended-to-differential,
and single-supply applications.
For ±2.5 V or +5 V supply operation, the input common-mode
range at the summing nodes of the amplifier is specified as ?2.7 V
to +1.3 V or ?0.2 V to 3.8 V, and is specified as ?0.2 V to +1.8 V
with a +3 V supply.
ADA4940-1/ADA4940-2 Data Sheet
Rev. E | Page 26 of 30
INPUT AND OUTPUT CAPACITIVE AC COUPLING
Although the ADA4940-1/ADA4940-2 is best suited to dc-
coupled applications, it is nonetheless possible to use it in ac-
coupled circuits. Input ac coupling capacitors can be inserted
between the source and RG. This ac coupling blocks the flow
of the dc common-mode feedback current and causes the
ADA4940-1/ADA4940-2 dc input common-mode voltage to
equal the dc output common-mode voltage. These ac coupling
capacitors must be placed in both loops to keep the feedback
factors matched. Output ac coupling capacitors can be placed in
series between each output and its respective load.
SETTING THE OUTPUT COMMON-MODE VOLTAGE
The VOCM pin of the ADA4940-1/ADA4940-2 is internally
biased at a voltage approximately equal to the midsupply point,
[(+VS) + (?VS)]/2. Relying on this internal bias results in an
output common-mode voltage that is within approximately
100 mV of the expected value.
In cases where more accurate control of the output common-mode
level is required, it is recommended that an external source, or
resistor divider (10 k? or greater resistors), be used. The output
common-mode offset listed in the Specifications section assumes
that the VOCM input is driven by a low impedance voltage source.
It is also possible to connect the VOCM input to a common-mode
level (CML) output of an ADC. However, care must be taken to
ensure that the output has sufficient drive capability. The input
impedance of the VOCM pin is approximately 250 k?.
DISABLE PIN
The ADA4940-1/ADA4940-2 feature a DISABLE pin that can
be used to minimize the quiescent current consumed when the
device is not being used. DISABLE is asserted by applying a low
logic level to the DISABLE pin. The threshold between high and
low logic levels is nominally 1.4 V above the negative supply rail.
See Table 5 and Table 8 for the threshold limits.
The DISABLE pin features an internal pull-up network that
enables the amplifier for normal operation. The ADA4940-1/
ADA4940-2 DISABLE pin can be left floating (that is, no
external connection is required) and does not require an
external pull-up resistor to ensure normal on operation (see
Figure 70). When the ADA4940-1/ADA4940-2 is disabled, the
output is high impedance. Note that the outputs are tied to the
inputs through the feedback resistors and to the source using the
gain resistors. In addition, there are back-to-back diodes on the
input pins that limit the differential voltage to 1.2 V.
08452-
063
DISABLE
AMPLIFIER
BIAS CURRENT
–V
S
+V
S
Figure 70.
DISABLE
Pin Circuit
DRIVING A CAPACITIVE LOAD
A purely capacitive load reacts with the bond wire and pin
inductance of the ADA4940-1/ADA4940-2, resulting in high
frequency ringing in the transient response and loss of phase
margin. One way to minimize this effect is to place a resistor in
series with each output to buffer the load capacitance. The resistor
and load capacitance form a first-order, low-pass filter; therefore,
the resistor value must be as small as possible. In some cases,
the ADCs require small series resistors to be added on their inputs.
Figure 71 illustrates the capacitive load vs. the series resistance
required to maintain a minimum 45° of phase margin.
120
0
5 10010 1000
08452-
064
20
40
60
80
100
SER
I
ES
R
ESI
ST
A
N
C
E
(?
)
LOAD CAPACITANCE (pF)
+IN –OUT
+OUT
–FB
+FB
–IN
V
OCM
0.1μF
R
S
R
S
R1
C
L
C
L
R2
R4
+2.5V
–2.5V
R3
V
IN
Figure 71. Capacitive Load vs. Series Resistance (LFCSP)
Data Sheet ADA4940-1/ADA4940-2
Rev. E | Page 27 of 30
DRIVING A HIGH PRECISION ADC
The ADA4940-1/ADA4940-2 are ideally suited for broadband
dc-coupled applications. The circuit in Figure 73 shows a front-
end connection for an ADA4940-1 driving an AD7982, which is
an 18-bit, 1 MSPS successive approximation, analog-to-digital
converter (ADC) that operates from a single power supply, 3 V
to 5 V. It contains a low power, high speed, 18-bit sampling
ADC and a versatile serial interface port. The reference voltage,
REF, is applied externally and can be set independent of the
supply voltage. As shown in Figure 73, the ADA4940-1 is dc-
coupled on the input and the output, which eliminates the need
for a transformer to drive the ADC. The amplifier performs a
single-ended-to-differential conversion if needed and level
shifts the input signal to match the input common mode of the
ADC. The ADA4940-1 is configured with a dual 7 V supply
(+6 V and ?1 V) and a gain that is set by the ratio of the
feedback resistor to the gain resistor. In addition, the circuit
can be used in a single-ended-input-to-differential output or
differential-input-to-differential output configuration. If needed,
a termination resistor in parallel with the source input can be
used. Whether the input is a single-ended input or differential,
the input impedance of the amplifier can be calculated as shown in
the Terminating a Single-Ended Input section. If R1 = R2 = R3 =
R4 = 1 k?, the single-ended input impedance is approximately
1.33 kΩ, which, in parallel with a 52.3 Ω termination resistor,
provides a 50 Ω termination for the source. An additional 25.5 Ω
(1025.5 Ω total) at the inverting input balances the parallel
impedance of the 50 Ω source and the termination resistor driving
the noninverting input. However, if a differential source input is
used, the differential input impedance is 2 kΩ. In this case, two
52.3 Ω termination resistors are used to terminate the inputs.
In this example, the signal generator has a 10 V p-p symmetric,
ground-referenced bipolar output. The VOCM input is bypassed for
noise reduction and set externally with 1% resistors to 2.5 V to
maximize the output dynamic range. With an output common-
mode voltage of 2.5 V, each ADA4940-1 output swings between
0 V and 5 V, opposite in phase, providing a gain of 1 and a
10 V p-p differential signal to the ADC input. The differential RC
section between the ADA4940-1 output and the ADC provides
single-pole, low-pass filtering with a corner frequency of 1.79 MHz
and extra buffering for the current spikes that are output from the
ADC input when its sample-and-hold (SHA) capacitors are
discharged.
The total system power in Figure 73 is under 35 mW. A large
portion of that power is the current coming from supplies to the
output, which is set at 2.5 V, going back to the input through the
feedback and gain resistors. To reduce that power to 25 mW,
increase the value of the feedback and gain resistor from 1 kΩ
to 2 kΩ and set the value of the resistors R5 and R6 to 3 k?. The
ADR435 is used to regulate the +6 V supply to +5 V, which ends
up powering the ADC and setting the reference voltage for the
VOCM pin.
Figure 72 shows the FFT of a 20 kHz differential input tone
sampled at 1 MSPS. The second and third harmonics are down
at ?118 dBc and ?122 dBc.
0
–160
–140
–120
–100
–80
–60
–40
–20
0 20k 40k 60k 80k 100k
AM
P
L
I
T
UDE
(
d
B)
FREQUENCY (Hz) 08452-
069
Figure 72. Distortion Measurement of a 20 kHz Input Tone (See CN-0237)
08452-
066
33?
33?
10μF
R1
–D
IN
+2.5V
+5V
+6V
–1V
R2
R4
+6V
REF
VDD
GND
IN+
IN–
AD7982
2.7nF
2.7nF
–IN
+OUT
–OUT
+IN
R3
+D
IN
ADR435
0.1μFR6
R5
SERIAL
INTERFACE
–FB
+FB
ADA4940-1
V
OCM
Figure 73. ADA4940-1 (LFCSP) Driving the AD7982 ADC
ADA4940-1/ADA4940-2 Data Sheet
Rev. E | Page 28 of 30
LAYOUT, GROUNDING, AND BYPASSING
As a high speed device, the ADA4940-1/ADA4940-2 are
sensitive to the PCB environment in which they operate.
Realizing their superior performance requires attention to
the details of high speed PCB design.
ADA4940-1 LFCSP EXAMPLE
The first requirement is a solid ground plane that covers as
much of the board area around the ADA4940-1 as possible.
However, clear the area near the feedback resistors (RF), gain
resistors (RG), and the input summing nodes (Pin 2 and Pin 3)
of all ground and power planes (see Figure 74). Clearing the
ground and power planes minimizes any stray capacitance at
these nodes and prevents peaking of the response of the
amplifier at high frequencies.
The thermal resistance, θJA, is specified for the device, including
the exposed pad, soldered to a high thermal conductivity 4-layer
circuit board, as described in EIA/JESD 51-7.
08452-
086
Figure 74. Ground and Power Plane Voiding in Vicinity of RF and RG
Bypass the power supply pins as close to the device as possible
and directly to a nearby ground plane. Use high frequency ceramic
chip capacitors. Use two parallel bypass capacitors (1000 pF and
0.1 μF) for each supply. Place the 1000 pF capacitor closer to the
device. Further away, provide low frequency bypassing using
10 μF tantalum capacitors from each supply to ground.
Ensure that signal routing is short and direct to avoid parasitic
effects. Wherever complementary signals exist, provide a
symmetrical layout to maximize balanced performance. When
routing differential signals over a long distance, ensure that
PCB traces are close together, and twist any differential wiring
such that loop area is minimized. Doing this reduces radiated
energy and makes the circuit less susceptible to interference.
1.30
0.80
0.801.30
08452-
087
Figure 75. Recommended PCB Thermal Attach Pad Dimensions (mm)
0.30
PLATED
VIA HOLE
1.30
GROUND PLANE
POWER PLANE
BOTTOM METAL
TOP METAL
08452-
088
Figure 76. Cross-Section of 4-Layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in mm)
Data Sheet ADA4940-1/ADA4940-2
Rev. E | Page 29 of 30
OUTLINE DIMENSIONS
1.45
1.30 SQ
1.15
1
0.50
BSC
16
58
9
12
13
4
3.10
3.00 SQ
2.90
0.50
0.40
0.30
0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
0.30
0.23
0.18
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6
0.80
0.75
0.70
BOTTOM VIEWTOP VIEW
SEATING
PLANE
SIDE VIEW
EXPOSED
PAD
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
10-
1
1-
2017-
B
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
P
K
G
-
004337
Figure 77. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-21)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
0
1
2
4
0
7
-
A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8 5
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 78. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ADA4940-1/ADA4940-2 Data Sheet
Rev. E | Page 30 of 30
0.50
BSC
0.50
0.40
0.30
0.30
0.25
0.18
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.
BOTTOM VIEWTOP VIEW
SIDE VIEW
EXPOSED
PAD
4.10
4.00 SQ
3.90
0.80
0.75
0.70
0.20 REF
0.20 MIN
3.16 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
2.65
2.50 SQ
2.45
1
24
712
13
18
19
6
0.05 MAX
0.02 NOM
P
K
G
-
004462
10-
19-
2017-
B
SEATING
PLANE
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 79. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range Package Description Package Option Ordering Quantity Marking Code
ADA4940-1ACPZ-R2 ?40°C to +125°C 16-Lead LFCSP CP-16-21 250 H29
ADA4940-1ACPZ-RL ?40°C to +125°C 16-Lead LFCSP CP-16-21 5,000 H29
ADA4940-1ACPZ-R7 ?40°C to +125°C 16-Lead LFCSP CP-16-21 1,500 H29
ADA4940-1ARZ ?40°C to +125°C 8-Lead SOIC_N R-8 98
ADA4940-1ARZ-RL ?40°C to +125°C 8-Lead SOIC_N R-8 2,500
ADA4940-1ARZ-R7 ?40°C to +125°C 8-Lead SOIC_N R-8 1,000
ADA4940-2ACPZ-R2 ?40°C to +125°C 24-Lead LFCSP CP-24-7 250
ADA4940-2ACPZ-RL ?40°C to +125°C 24-Lead LFCSP CP-24-7 5,000
ADA4940-2ACPZ-R7 ?40°C to +125°C 24-Lead LFCSP CP-24-7 1,500
1
Z = RoHS Compliant Part.
?2011–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08452-0-4/18(E)
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