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| CS5523 MIPI转eDP芯片规格说明书 |
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Page 5 of 16
1 Introduction
The ASL CS5523 is a MIPI DSI input, DP/eDP output convert chip. The MIPI DSI supports up to 4lanes and each
lane operates at 1.5Gbps maximum. For DP1.2 output, it consists of 4 data lanes, supporting 1.62Gbps and
2.7Gbps link rate. It supports the highest resolutions of 25601440@60Hz. It can use only single 1.8V power
supply for saves cost and optimizes board space.
The CS5523 is suitable for multiple market segments and display applications, such as handheld device,
motherboard, dual panel display and car display etc.
4lanes
DP/eDP TX
lanes 4
MIPI
PWM
DP/eDP TX
FRC
MCU
BIST
Line BufferRC OSC
DSI RX
PLL
Figure 1-1 CS5523 Block Diagram
CS5523 Datasheet
MIPI DSI to DP/eDP Convertor
Page 6 of 16
CS5523
Datasheet
2 Features
General
? MIPI DSI input and DP/eDP output
? Support Dithering and 6 bits + FRC.
? Integrate PWM Generator with GPIO output PWM to control backlight
? Internal power-on-reset (POR)
? Embedded EDID
? Embedded MCU with SPI flash controller
MIPI Input
? Supports MIPI? D-PHY Version 1.2 and MIPI? DSI Version 1.3
? Support 1-to-4 Data lanes, 1 Clock Lane
? Bi-directional Lane 0 (Reverse only LP)
? Support ULPS (Ultra Low Power State)
? Support Packed Pixel Format RGB at 18/24/30/36 bits
? Support Loosely Packed Pixel Format RGB at 18 bits
? Support RGB565 16-bits input
? DSI host can access local register in ESCAPE mode
? Support Sync Event/Sync Pulse mode
? Support Low Power Mode entry in all lines during V-blanking
? Support Lane/Polarity swap
? Support continuous clock and/or non-continuous clock
eDP/DP Output
? VESA DisplayPortTM (DP) v1.2 compliant transmitter
? VESA embedded DisplayPortTM (eDP) v1.2 compliant transmitter
? Support 4-lane up to HBR (2.7Gbps) output
? Support 6, 8bpc, RGB output
? Support eDP ASSR function
? Support data lane and polarity swapping
? Support 1Mbps AUX channel
? Support up to 2560x1440@60Hz
Misc.
? Single 1.8V power supply mode.
? Internal 1.2V LDO power supply
? QFN48 7x7 package
? HBM 4-KV for all pins
ASL Confidential Page 7 of 16
CS5523
Datasheet
3 Pin Definition
3.1 Pin Assignments
CS5523
MLRX_3N
MLRX_3P
NC
MLRX_2N
MLRX_2P
42
41
40
39
38
37
ePad must be grounded
MLRX_CKP
MLRX_1N
MLRX_1P
NC
MLRX_0N
MLRX_0P
S_
SC
L
48
47
46
45
44
S_
SD
A
G
PI
O
5
G
PI
O
0
G
PI
O
1
G
PI
O
6
H
P
D
/G
PI
O
7
V
D
D
1 2 3 4 5 6 7 8
A
U
X
N
A
U
X
P
V
CC
18
DPTX_D3N
MLRX_CKN
43
13
14
15
16
17
18
19
20
21
22
23
24
DPTX_D3P
NC
DPTX_D2N
DPTX_D2P
NC
DPTX_D1N
TE
ST
_E
N
DPTX_D0P
VCC18
DPTX_D1P
NC
DPTX_D0N
NCV
CC
18
VC
C
18
XT
AL
O
XT
A
LI
V
D
D
18
S_
AD
R
G
P
IO
4
G
P
IO
8
G
P
IO
9
ES
E
T_
N
VC
C
18
Figure 3-1 CS5523 Pin Layout
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CS5523
Datasheet
3.2 Pin Description
Table 3-1 CS5523 Pin Definitions
Pin # Name Type Direction Note
1 VCC18 P Analog 1.8V Power
2 S_SCL LVCMOS 1V8 IO I2C slave CLOCK pin for debug
3 S_SDA LVCMOS 1V8 IO I2C slave DATA pin for debug
4 GPIO5 LVCMOS 1V8 IO General-purpose input/output, 3.3V tolerant pin
5 GPIO0 LVCMOS 1V8 IO General-purpose input/output, 3.3V tolerant pin
6 GPIO1 LVCMOS 1V8 IO General-purpose input/output, 3.3V tolerant pin
7 GPIO6 LVCMOS 1V8 IO General-purpose input/output, 3.3V tolerant pin
8 HPD/GPIO7 LVCMOS 1V8 IO General-purpose input/output, 3.3V tolerant pin Default use as DPTX HPD input
9 VDD P Digital 1.8V Power
10 AUXN Analog IO DP Tx AUX Channel Negative Output
11 AUXP Analog IO DP Tx AUX Channel Positive Output
12 VCC18 P Analog 1.8V Power
13 DPTX_D3N Analog O DP Tx PHY Port-A Data Lane-3 Negative Output DP Tx output data up to 2.7Gb/s.
14 DPTX_D3P Analog O DP Tx PHY Port-A Data Lane-3 Positive Output DP Tx output data up to 2.7Gb/s.
15 NC No used
16 DPTX_D2N Analog O DP Tx PHY Port-A Data Lane-2 Negative Output DP Tx output data up to 2.7 Gb/s.
17 DPTX_D2P Analog O DP Tx PHY Port-A Data Lane-2 Positive Output DP Tx output data up to 2.7Gb/s.
18 NC -- -- No used
19 DPTX_D1N Analog O DP Tx PHY Port-A Data Lane-1 Negative Output DP Tx output data up to 2.7Gb/s.
20 DPTX_D1P Analog O DP Tx PHY Port-A Data Lane-1 Positive Output DP Tx output data up to 2.7Gb/s.
21 NC -- -- No used
22 DPTX_D0N Analog O DP Tx PHY Port-A Data Lane-0 Negative Output DP Tx output data up to 2.7Gb/s.
23 DPTX_D0P Analog O DP Tx PHY Port-A Data Lane-0 Positive Output DP Tx output data up to 2.7Gb/s.
24 VCC18 Analog 1.8V Power
25 TEST_EN LVCMOS 1V8 IO 1: Test mode. 0: Normal mode Internal Pull Down
ASL Confidential Page 9 of 16
CS5523
Datasheet
Pin # Name Type Direction Note
26 NC -- -- No used
27 VCC18 P Analog 1.8V Power
28 XTALO LVCMOS 1V8 O
Crystal Clock Output.
A crystal oscillator should be attached between this pin and
XTALI. If XTALI is used as reference clock input, this pin must
be floating.
29 XTALI LVCMOS 1V8 IO
Crystal Clock Input.
A crystal oscillator should be attached between this pin and
XTALO. However, a CMOS 1.8V compatible clock signal can
also be connected to this pin as reference.
30 VDD P Digital 1.8V Power
31 S_ADR LVCMOS 1V8 I I2C Device Address Select. High: 0x72, Low: 0x70
32 GPIO4 LVCMOS 1V8 IO General-purpose input/output
33 GPIO8 LVCMOS 1V8 IO General-purpose input/output
34 GPIO9 LVCMOS 1V8 IO General-purpose input/output
35 RESET_N LVCMOS 1V8 I Hardware Reset Input Chip reset signal. Active LOW.
36 VCC18 P Analog 1.8V Power
37 MPRX_3N Analog I MIPI D-PHY Data Lane-3 Negative Input
38 MPRX_3P Analog I MIPI D-PHY Data Lane-3 Positive Input
39 NC -- -- No used
40 MPRX_2N Analog I MIPI D-PHY Data Lane-2 Negative Input
41 MPRX_2P Analog I MIPI D-PHY Data Lane-2 Positive Input
42 MPRX_CKN Analog I MIPI D-PHY Clock Lane Negative Input
43 MPRX_CKP Analog I MIPI D-PHY Clock Lane Positive Input
44 MPRX_1N Analog I MIPI D-PHY Data Lane-1 Negative Input
45 MPRX_1P Analog I MIPI D-PHY Data Lane-1 Positive Input
46 NC -- -- No used
47 MPRX_0N Analog I MIPI D-PHY Data Lane-0 Negative Input
48 MPRX_0P Analog I MIPI D-PHY Data Lane-0 Positive Input
ASL Confidential Page 10 of 16
CS5523
Datasheet
4 Electrical Specifications
4.1 Absolute Maximum Conditions
Permanent damage may occur if absolute maximum conditions are violated. Refer to Section 4.2 for functional
operating limits.
Table 4-1 Absolute Maximum Conditions
Symbol Parameter Min Typ Max Unit
VDD18 1.8V power input -0.3 — 2.16 V
TJ Junction temperature -40 — 125 °C
TSTG Storage temperature -65 — 150 °C
ESDHBM ESD protection (Human body model) — — ± 4 KV
ESDCDM ESD protection (Charge Device model) — — 700 V
1. Max 260°C can be guaranteed with max 8 sec soldering time.
4.2 Operating Conditions
Table 4-2 Normal Operating Conditions
Symbol Parameter Min Typ Max Unit
VDD18 1.8V power input 1.62 1.8 1.98 V
TA Ambient temperature -10 70 °C
θJA Package thermal resistance, no air flow — 39.3 — °C/W
4.3 Electrical Specification
Table 4-3 IO DC Electrical Specification
Symbol Parameter Min Typ Max
Vil (V) Input low voltage — — 0.63
Vih (V) Input high Voltage 1.17 — —
Vol (V) Output low voltage 0 — 0.45
Voh (V) Output high voltage 1.35 — —
Iin (uA) Input leakage current -10 — +10
Ihiz (uA) Output tri-state leakage current -10 — +10
Table 4-4 MIPI RX HS DC Specification
Symbol Description Min Typ Max Unit
VCMRX(DC) Common-mode voltage HS receive mode 70 330 mV
ASL Confidential Page 11 of 16
CS5523
Datasheet
Symbol Description Min Typ Max Unit
VIDTH Differential input high threshold 70 mV
VIDTL Differential input low threshold -70 mV
VIHHS Single-ended input high voltage 460 mV
VILHS Single-ended input low voltage -40 mV
VTERM-EN Single-ended threshold for HS termination enable 450 mV
ZID Differential input impedance 80 100 125 Ω
Table 4-5 MIPI RX HS AC Specification
Symbol Description Min Typ Max Unit
ΔVCMRX(HF) Common-mode interference beyond 450 MHz 100 mV
ΔVCMRX(LF) Common-mode interference 50MHz – 450MHz -50 50 mV
CCM Common-mode termination 60 pF
Table 4-6 MIPI RX LP DC Specification
Symbol Description Min Typ Max Unit
VIH Logic 1 input voltage 880 mV
VIL Logic 0 input voltage, not in ULP State 550 mV
VIL-ULPS Logic 0 input voltage, ULP State 300 mV
VHYST Input hysteresis 25 mV
Table 4-7 MIPI RX LP AC Specification
Symbol Description Min Typ Max Unit
eSPIKE Input pulse rejection 300 V·ps
TMIN-RX Minimum pulse width response 20 ns
VINT Peak interference amplitude 200 mV
fINT Interference frequency 450 MHz
4.4 Power Consumption
Different applications would result in different power consumptions of CS5523. For example, whether to adopt
the embedded oscillator, and how fast of the video clock frequency are all definitely the key factors of the power
consumption of CS5523. The following tables show the reference power consumption of CS5523 in several
different application conditions.
ASL Confidential Page 12 of 16
CS5523
Datasheet
Table 4-8 CS5523 Typical Power Consumption
Active Resolution (Pixel clock) Min Typ Max Unit
MIPI 1 lanes, DP 1 Port, 1.62G, 640x480@60Hz(25-MHz) - 72 - mA
MIPI 2 lanes, DP 2 Port, 2.7G, 1280x720@60Hz (85-MHz) - 121 - mA
MIPI 4 lanes, DP 4 Port, 2.7G, 1920x1080@60Hz (148-
MHz)
- 175 - mA
Note:
1. In practice, the measured power consumption might be slightly different from the tables above due to the different video content
and the different measurement equipment.
ASL Confidential Page 13 of 16
CS5523
Datasheet
5 Package Specification
Figure 5-1 CS5523 Package Outline (QFN48 Leads 6x6mm)
Table 5-1 Package Dimension
Symbol
Dimension in mm Dimension in inch
Min Normal Max Min Normal Max
A 0.70 0.75 0.80 0.028 0.0295 0.031
A1 0.00 0.02 0.05 0.000 0.001 0.002
A2 — 0.55 — — 0.022 —
A3 0.203 REF 0.008 REF
b 0.2 0.25 0.3 0. 062 0. 080 0.098
D/E 6.00 BSC 0.236 BSC
D2/E2 4.5 4.6 4.7 0.178 0.181 0.185
e 0.40 BSC 0.016 BSC
L 0.30 0.40 0.50 0.012 0.016 0.020
K 0.3 REF 0.012REF 0.
ASL Confidential Page 14 of 16
CS5523
Datasheet
6 Ordering Information
The CS5523 can be ordered using the part numbers in Table 6-1. Please consult sales for further details.
Table 6-1 CS5523 Ordering Information
Part No. Description Temperature Range MSL Environment Compliance Packing Type
CS5523AN 48 Pin (QFN) Lead-free package Commercial: 0 to 70 degree C Level 3 Green 5K / T &R
CS5523AN-I 48 Pin (QFN) Lead-free package Industrial: -40 to 85 degree C Level 3 Green 5K / T &R
Table 6-2 CS5523 Commercial Marking Information
Line No. Description Temperature Range
Line1 ASL logo ASL logo
Line2 CS5523 Product Name
Line3 XXXXXX Lot #
Line4 YYWW YYWW: Date code
Line5 PIN1 indicator
Figure 6-1 CS5523 Commercial Marking
CS5523
XXXXXXXXX
YYWW
ASL Confidential Page 15 of 16
CS5523
Datasheet
Table 6-3 CS5523 Industrial Marking Information
Line No. Description Temperature Range
Line1 ASL logo ASL logo
Line2 CS5523AN-I Product Name
Line3 XXXXXX Lot #
Line4 YYWW YYWW: Date code
Line5 PIN1 indicator
Figure 6-2 CS5523 Industrial Marking
CS5523AN-I
XXXXXXXXX
YYWW
ASL Confidential Page 16 of 16
CS5523
Datasheet
7 Revision History
Table 7-1 Document Revision History
Revision Date Changes
V0.1 April. 2022 draft version
V0.2 May. 2022 Update power consumption
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