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Data Sheet, V 1.2, April 2008
TDK5100F
434 MHz ASK/FSK Transmitter in 10-pin
Package
Wireless Control
Components
Never stop thinking.Edition 2008-04-04
Published by Infineon Technologies AG,
Am Campeon 1-12,
85579 Neubiberg, Germany
? Infineon Technologies AG 2008-04-04.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or the Infineon Technologies Companies and our Infineon Technologies
Representatives worldwide (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.Data Sheet, V 1.2, April 2008
TDK5100F
434 MHz ASK/FSK Transmitter in 10-pin
Package
Wireless Control
Components
Never stop thinking.TDK5100F
Revision History: 2008-04-04 V 1.2
Previous Version: V1.1 as of November 2005
Page Subjects (major changes since last revision)
31-33, 35 Added Min.-/Max.-values of output power and supply current
31, 33, 35 Added values of frequency range and for possible extension of frequency
range
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
sensors@infineon.comTDK5100F
Table of Contents Page
1 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4 Order Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.1 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.3 Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.4 Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.4.1 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.4.2 PLL Enable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.4.3 Transmit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.4.4 Power mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.5 Recommended Timing Diagrams for ASK- and FSK-Modulation . . . . . 17
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 50 Ohm-Output Testboard Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 50 Ohm-Output Testboard Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3 Bill of Material (50 Ohm-Output Evalboard) . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4 Stripline-Antenna Testboard Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5 Stripline-Antenna Testboard Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6 Bill of Material (Antenna board) FSK modulation . . . . . . . . . . . . . . . . . . . . 24
3.7 Application Hints on the Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.8 Design Hints on the Clock Output (CLKOUT) . . . . . . . . . . . . . . . . . . . . . . 27
3.9 Application Hints on the Power-Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2 Operating Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3.1 AC/DC Characteristic at 3V, 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3.2 AC/DC Characteristic at 2.1V ...4.0 V, -40°C ...+125°C . . . . . . . . . . . . 33
5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Data Sheet 5 V 1.2, 2008-04-04TDK5100F
Product Description
1 Product Description
1.1 Overview
The TDK 5100 F is a single chip ASK/FSK transmitter for operation in the frequency band
433-435 MHz. The IC offers a high level of integration and needs only a few external
components. The device contains a fully integrated PLL synthesizer and a high efficiency
power amplifier to drive a loop antenna. A special circuit design and an unique power
amplifier design are used to save current consumption and therefore to save battery life.
Additional features are a power down mode and a divided clock output.
1.2 Features
? fully integrated frequency synthesizer
? VCO without external components
? ASK and FSK modulation
? frequency range 433-435 MHz
? high efficiency power amplifier (typically 5 dBm)
? low supply current
? voltage supply range 2.1 ... 4 V
? temperature range ?40 ... +125°C
? power down mode
? crystal oscillator 13.56 MHz
? FSK-switch
? divided clock output for μC
? low external component count
1.3 Application
? Tire pressure monitoring systems
? Keyless entry systems
? Remote control systems
? Alarm systems
? Communication systems
1.4 Order Information
Table 1 Order Information
Type Ordering Code Package
TDK5100F SP000014745 PG-TSSOP-10
available on tape and reel
Data Sheet 6 V 1.2, 2008-04-04TDK5100F
Functional Description
2 Functional Description
2.1 Pin Configuration
CLKOUT 1 10 PDWN
VS 2 9 PAOUT
GND 3 8 PAGND
TDK 5100F
FSKOUT 4 7 FSKDTA
COSC 5 6 ASKDTA
Figure 1 IC Pin Configuration
2.2 Pin Definition and Functions
Table 2 Pin Definition and Functions - Overview
Pin Symbol Function
No.
1 CLKOUT Clock Driver Output (847.5 kHz)
2 VS Voltage Supply
3 GND Ground
4 FSKOUT Frequency Shift Keying Switch Output
5 COSC Crystal Oscillator Input (13.56 MHz)
6 ASKDTA Amplitude Shift Keying Data Input
7 FSKDTA Frequency Shift Keying Data Input
8 PAGND Power Amplifier Ground
9 PAOUT Power Amplifier Output (434 MHz)
10 PDWN Power Down Mode Control
Data Sheet 7 V 1.2, 2008-04-04TDK5100F
Functional Description
1)
Table 3 Pin Definition and Function
Pin Symbol Interface Schematic Function
No.
1 CLKOUT Clock output to supply an external
device.
V
S
An external pull-up resistor has to
be added in accordance to the
1
driving requirements of the
300 ? external device.
The clock frequency is 847.5 kHz.
2 VS This pin is the positive supply of
the transmitter electronics.
An RF bypass capacitor should be
connected directly to this pin and
returned to GND (pin 3) as short
as possible.
3 GND General ground connection.
4 FSKOUT This pin is connected to a switch to
GND (pin 3).
V
V
S S
The switch is closed when the
signal at FSKDTA (pin 7) is in a
logic low state.
200 μA
4
The switch is open when the signal
at FSKDTA (pin 7) is in a logic high
120 k? 200 k?
state.
FSKOUT can switch an additional
capacitor to the reference crystal
network to pull the crystal
frequency by an amount resulting
in the desired FSK frequency shift
of the transmitter output
frequency.
Data Sheet 8 V 1.2, 2008-04-04TDK5100F
Functional Description
Pin Symbol Interface Schematic Function
No.
5 COSC This pin is connected to the
reference oscillator circuit.
V V
S S
The reference oscillator is working
as a negative impedance
6 k?
converter. It presents a negative
resistance in series to an
5
inductance at the COSC pin.
100 μA
6 ASKDTA Digital amplitude modulation can
be imparted to the Power Amplifier
V +1.2 V
S
through this pin.
60 k?
A logic high (ASKDTA > 1.5 V or
6
+1.1 V
open) enables the Power
90 k?
Amplifier.
50 pF 30 μA
A logic low (ASKDTA < 0.5 V)
disables the Power Amplifier.
Data Sheet 9 V 1.2, 2008-04-04TDK5100F
Functional Description
Pin Symbol Interface Schematic Function
No.
7 FSKDTA Digital frequency modulation can
be imparted to the Xtal Oscillator
V +1.2 V
S
by this pin. The VCO-frequency
varies in accordance to the
60 k?
frequency of the reference
7
oscillator.
+1.1 V
90 k?
A logic high (FSKDTA > 1.5V or
30 μA
open) sets the FSK switch to a
high impedance state.
A logic low (FSKDTA < 0.5 V)
closes the FSK switch from
FSKOUT (pin 4) to GND (pin 3).
A capacitor can be switched to the
reference crystal network this way.
The Xtal Oscillator frequency will
be shifted giving the designed FSK
frequency deviation.
Data Sheet 10 V 1.2, 2008-04-04TDK5100F
Functional Description
Pin Symbol Interface Schematic Function
No.
8 PAGND Ground connection of the power
amplifier.
9
The RF ground return path of the
power amplifier output PAOUT
(pin 9) has to be concentrated to
this pin.
9 PAOUT RF output pin of the transmitter.
8
A DC path to the positive supply
VS has to be supplied by the
antenna matching network.
10 PDWN Disable pin for the complete
V transmitter circuit.
S
40 μA ? (ASKDTA+FSKDTA)
A logic low (PDWN < 0.7 V) turns
off all transmitter functions.
5 k?
10
A logic high (PDWN > 1.5 V) gives
"ON"
access to all transmitter functions.
150 k?
PDWN input will be pulled up by
40 μA internally by either setting
250 k?
FSKDTA or ASKDTA to a logic
high-state.
1) Indicated voltages and currents apply for PLL Enable Mode and Transmit Mode.
In Power Down Mode, the values are zero or high-ohmic.
Data Sheet 11 V 1.2, 2008-04-04TDK5100F
Functional Description
2.3 Functional Block Diagram
Figure 2 Functional Block Diagram
Data Sheet 12 V 1.2, 2008-04-04
FSK ASK Power Power
Data Data Down Supply
Input Input Control VS
7 6 10 2
Power
OR
Supply
FSK
4
Switch
On
Power
9
XTAL Power
PFD :64 VCO :2 Amplifier
Osc AMP
5 Output
Crystal
13.56 MHz
Power
8
Amplifier
Ground
LF
:16
1 3
Clock
Ground
OutputTDK5100F
Functional Description
2.4 Functional Block Description
2.4.1 PLL Synthesizer
The Phase Locked Loop synthesizer consists of a Voltage Controlled Oscillator (VCO),
an asynchronous divider chain, a phase detector, a charge pump and a loop filter. It is
fully implemented on chip. The tuning circuit of the VCO consisting of spiral inductors
and varactor diodes is on chip, too. Therefore no additional external components are
necessary. The nominal center frequency of the VCO is 868 MHz. The oscillator signal
is fed both, to the synthesizer divider chain and to the power amplifier. The overall
division ratio of the asynchronous divider chain is 64. The phase detector is a Type IV
PD with charge pump. The passive loop filter is implemented on chip.
2.4.2 Crystal Oscillator
The crystal oscillator operates at 13.56 MHz.
The crystal frequency is divided by 16. The resulting 847.5 kHz are available at the clock
output CLKOUT (pin1) to drive the clock input of a micro controller.
To achieve FSK transmission, the oscillator frequency can be detuned by a fixed amount
by switching an external capacitor via FSKOUT (pin 4).
The state of the switch is controlled by the signal at FSKDTA (pin 7).
Table 4 FSKDTA - FSK Switch
FSKDTA (pin7) FSK Switch
1)
Low CLOSED
2) 3)
Open , High OPEN
1) Low: Voltage at pin < 0.5V
2) Open: Pin open
3) High: Voltage at pin > 1.5V
2.4.3 Power Amplifier
The VCO frequency is divided by 2 and fed to the Power Amplifier.
The Power Amplifier can be switched on and off
by the signal at ASKDTA (pin 6).
Data Sheet 13 V 1.2, 2008-04-04TDK5100F
Functional Description
Table 5 ASKDTA - Power Amplifier
ASKDTA (pin6) Power Amplifier
1)
Low OFF
2) 3)
Open , High ON
1) Low: Voltage at pin < 0.5V
2) Open: Pin open
3) High: Voltage at pin > 1.5V
The Power Amplifier has an Open Collector output at PAOUT (pin 9) and requires an
external pull-up coil to provide bias. The coil is part of the tuning and matching LC
circuitry to get best performance with the external loop antenna. To achieve the best
power amplifier efficiency, the high frequency voltage swing at PAOUT (pin 9) should be
twice the supply voltage.
The power amplifier has its own ground pin PAGND (pin 8) in order to reduce the amount
of coupling to the other circuits.
2.4.4 Power Modes
The IC provides three power modes, the POWER DOWN MODE, the PLL ENABLE
MODE and the TRANSMIT MODE.
2.4.4.1 Power Down Mode
In the POWER DOWN MODE the complete chip is switched off.
The current consumption is typically 0.3 nA at 3 V 25°C.
This current doubles every 8°C. The values for higher temperatures are
typically 14 nA at 85°C and typically 600 nA at 125°C.
2.4.4.2 PLL Enable Mode
In the PLL ENABLE MODE the PLL is switched on but the power amplifier is turned off
to avoid undesired power radiation during the time the PLL needs to settle. The turn on
time of the PLL is determined mainly by the turn on time of the crystal oscillator and is
less than 1 ms when the specified crystal is used.
The current consumption is typically 3.5 mA (in PLL Enable Mode).
Data Sheet 14 V 1.2, 2008-04-04TDK5100F
Functional Description
2.4.4.3 Transmit Mode
In the TRANSMIT MODE the PLL is switched on and the power amplifier is turned on too.
The current consumption of the IC is typically 7 mA when using a proper transforming
network at PAOUT, see Figure 8.
2.4.4.4 Power mode control
The bias circuitry is powered up via a voltage V > 1.5 V at the pin PDWN (pin10).
When the bias circuitry is powered up, the pins ASKDTA and FSKDTA are pulled up
internally.
Forcing the voltage at the pins low overrides the internally set state.
Alternatively, if the voltage at ASKDTA or FSKDTA is forced high externally, the PDWN
pin is pulled up internally via a current source. In this case, it is not necessary to connect
the PDWN pin, it is recommended to leave it open.
The principle schematic of the power mode control circuitry is shown in Figure 3
PDWN
ASKDTA
OR
FSKDTA
On
Bias
Source
120 k?
FSKOUT
120 k?
FSK
On
434
PA
PLL PAOUT
MHz
IC
Figure 3 Power mode control circuitry
Data Sheet 15 V 1.2, 2008-04-04
Bias VoltageTDK5100F
Functional Description
Table 6 provides a listing of how to get into the different power modes
Table 6 Power Modes
PDWN FSKDTA ASKDTA MODE
1)
Low Low, Open Low, Open POWER DOWN
2)
Open Low Low
3)
High Low, Open, High Low PLL ENABLE
Open High Low
High Low, Open, High Open, High TRANSMIT
Open High Open, High
Open Low, Open, High High
1) Low: Voltage at pin < 0.7V (PDWN)
Voltage at pin < 0.5V (FSKDTA, ASKDTA)
2) Open: Pin open
3) High: Voltage at pin > 1.5V
Other combinations of the control pins PDWN, FSKDTA and ASKDTA are not
recommended.
Data Sheet 16 V 1.2, 2008-04-04TDK5100F
Functional Description
2.4.5 Recommended Timing Diagrams for ASK- and FSK-Modulation
ASK Modulation using FSKDTA and ASKDTA, PDWN not connected
Modes: Power Down PLL Enable Transmit
High
FSKDTA
Low
to t
DATA
Open, High
ASKDTA
Low
to t
min. 1 msec.
Figure 4 ASK Modulation
FSK Modulation using FSKDTA and ASKDTA, PDWN not connected.
Modes: Power Down PLL Enable Transmit
DATA
High
FSKDTA
Low
to t
High
ASKDTA
Low
to
t
min. 1 msec.
Figure 5 FSK Modulation
Data Sheet 17 V 1.2, 2008-04-04TDK5100F
Functional Description
Alternative ASK Modulation, FSKDTA not connected.
Modes: Power Down PLL Enable Transmit
High
PDWN
Low
to t
DATA
Open, High
ASKDTA
Low
to t
min. 1 msec.
Figure 6 Alternative ASK Modulation
Alternative FSK Modulation
Modes: Power Down PLL Enable Transmit
High
PDWN
Low
to t
Open, High
ASKDTA
Low
to t
DATA
Open, High
FSKDTA
Low
to t
min. 1 msec.
Figure 7 Alternative FSK Modulation
Data Sheet 18 V 1.2, 2008-04-04TDK5100F
Applications
3 Applications
3.1 50 Ohm-Output Testboard Schematic
Figure 8 50 Ohm-output testboard schematic
Data Sheet 19 V 1.2, 2008-04-04TDK5100F
Applications
3.2 50 Ohm-Output Testboard Layout
Figure 9 Top Side of TDK5100 F-Testboard with 50 Ohm-Output
Figure 10 Bottom Side of TDK5100 F-Testboard with 50 Ohm-Output
Data Sheet 20 V 1.2, 2008-04-04TDK5100F
Applications
3.3 Bill of Material (50 Ohm-Output Evalboard)
Reference Value Specification
R1 open
R2 open
R3 4k7 0603, +/-5%
R4 12k 0603, +/-5%
R5 open
R6 15k 0603, +/-5%
R7 open
C1 10p 0603, C0G, +/-1%
C2 6p8 0603, C0G, +/-0,1p
C3 open
C4 open
C5 100p 0603, X7R, +/-10%
C6 12p 0603, C0G, +/-1%
C7 39p 0603, C0G, +/-1%
C8 330p 0603, C0G, +/-5%
C9 3p3 0603, C0G, +/-0,1p
C10 47n 0603, X7R, +/-10%
L1 47n EPCOS SIMID 0603-C, +/-2%
L2 120n EPCOS SIMID 0603-C, +/-2%
X1 n.e.
X2 n.e.
X3 Pin single-pole connector, 2,54mm
X4 Pin single-pole connector, 2,54mm
X5 SMA-connector
X6 SMA-connector
X7 n.e.
JP1 solder bridge in position "XTAL"
JP2 solder bridge in position "FSK"
Q1 13,56875 MHz, Tokyo Denpa TSS-3B 13,56875 MHz Spec.No. 10-50205
IC1 TDK5100F
Please note:
If R2 is placed (Clk Out is activated) a 47nF capacitor has to be used for C4.
Data Sheet 21 V 1.2, 2008-04-04TDK5100F
Applications
3.4 Stripline-Antenna Testboard Schematic
Figure 11 Stripline-antenna testboard schematic
Data Sheet 22 V 1.2, 2008-04-04TDK5100F
Applications
3.5 Stripline-Antenna Testboard Layout
Figure 12 Top Side of TDK5100 F-Testboard with Stripline-Antenna
Figure 13 Bottom Side of TDK5100 F-Testboard with Stripline-Antenna
Please note that this board layout may be used for both high- and low-power
applications, see also the bill of materials on the subsequent pages.
In case of ASK operation the solder bridge JP2 has to be shortened in the “ASK”-
position, in case of FSK modulation in the“FSK” position.
Solder bridge JP1between C1, C2 and C3) gives a choice of operating the board with
the on-board crystal as reference (“XTAL” shortened, i.e. close to C1 and C2) or with an
external clock generator (solder bridge shorts pads between C3 and C2).
Data Sheet 23 V 1.2, 2008-04-04TDK5100F
Applications
3.6 Bill of Material (Antenna board) FSK modulation
Reference Value Specification
R1 open
R2 0R 0603, SMD-Jumper
R3 0R 0603, SMD-Jumper
R4 82k 0603, +/-5%
R5 open
R6 open
R7 100n 0603, X7R, +/-10%
R8 39R 0603, +/-1%
R9 15k 0603, +/-5%
C1 10p 0603, C0G, +/-1%
C2 6p8 0603, C0G, +/-0,1p
C3 open
C4 open
C5 open
C6 10n 0603, X7R, +/-10%
C7 5p6 0603, C0G, +/-0,1p
C8 open
C9 4p7 0603, C0G, +/-0,1p
C10 47n 0603, X7R, +/-10%
L1 100n 0603, EPCOS SIMID, +/-2%
L2 0R 0603, SMD-Jumper
X1 n.e.
X3 n.e.
X4 n.e.
S1 push-button STTSKHMPW, ALPS
JP1 solder bridge in position "XTAL"
JP2 solder bridge in position "FSK"
Q1 13,56875 MHz, Tokyo Denpa TSS-3B 13,56875 MHz Spec.No. 10-
IC1 TDK5100F P-TSSOP-10
IC2 HCS360 SO8
BAT1 battery holder HU2031-1, Renata
battery CR2032, Renata
Data Sheet 24 V 1.2, 2008-04-04TDK5100F
Applications
3.7 Application Hints on the Crystal Oscillator
Application Hints on the crystal oscillator
The crystal oscillator achieves a turn on time less than 1 msec when the specified crystal
is used. To achieve this, a NIC oscillator type is implemented in the TDK 5100 F. The
input impedance of this oscillator is a negative resistance in series to an inductance.
Therefore the load capacitance of the crystal CL (specified by the crystal supplier) is
transformed to the capacitance Cv.
-R L f, CL Cv
IC
Figure 14 Application Hints
Formula 1:
1
Cv =
1
2
+ω L
CL
CL: crystal load capacitance for nominal frequency
ω: angular frequency
L: inductance of the crystal oscillator
Example for the ASK-Mode:
Referring to the application circuit, in ASK-Mode the capacitance C2 is replaced by a
short to ground. Assume a crystal frequency of 13.56MHz and a crystal load capacitance
of CL = 12 pF. The inductance L at 13.56MHz is about 4.6 μH. Therefore C1 is calculated
to 10 pF.
1
Cv = =C1
1
2
+ω L
CL
Data Sheet 25 V 1.2, 2008-04-04TDK5100F
Applications
Example for the FSK-Mode:
FSK modulation is achieved by switching the load capacitance of the crystal as shown
below.
FSKDTA
FSKOUT
Csw
-R L f, CL Cv1 Cv2
COSC
IC
Figure 15 FSK Mode
The frequency deviation of the crystal oscillator is multiplied with the divider factor N of
the Phase Locked Loop to the output of the power amplifier. In case of small frequency
deviations (up to +/- 1000 ppm), the two desired load capacitances can be calculated
with the formula below.
?f 2(C0 +CL)
CL mC0 (1+ )
N f1 C1
CL± =
?f 2(C0 +CL)
1 ± (1+ )
N f1 C1
C : crystal load capacitance for nominal frequency
L
C : shunt capacitance of the crystal
0
f: frequency
ω: ω = 2πf: angular frequency
N: division ratio of the PLL
df: peak frequency deviation
Because of the inductive part of the TDK 5100 F, these values must be corrected by
Formula 1 on the preceding page.
Data Sheet 26 V 1.2, 2008-04-04TDK5100F
Applications
The value of Cv± can be calculated as
1
Cv± =
1
2
+ω L
CL ±
If the FSK switch is closed, Cv- is equal to Cv1 (C1 in the application diagram). If the
FSK switch is open, Cv2 (C2 in the application diagram) can be calculated.
Csw ?Cv1 ?(Cv +) ?(Cv1 +Csw)
Cv2 = C2 =
(Cv +) ?Cv1
Csw: parallel capacitance of the FSK switch (3 pF incl. layout parasitics)
Remark: These calculations are only approximations. The necessary values depend
on the layout also and must be adapted for the specific application board.
3.8 Design Hints on the Clock Output (CLKOUT)
The CLKOUT pin is an open collector output. An external pull up resistor (RL) should be
connected between this pin and the positive supply voltage. The value of RL is
depending on the clock frequency and the load capacitance CLD (PCB board plus input
capacitance of the microcontroller). RL can be calculated to:
1
RL =
fCLKOUT8CLD
Table 7 Clock Output
fCLKOUT=847.5 kHz
CL[pF] RL[kOhm]
527
10 12
20 6.8
Remark: To achieve a low current consumption and a low
spurious radiation, the largest possible RL should be chosen.
Data Sheet 27 V 1.2, 2008-04-04TDK5100F
Applications
Even harmonics of the signal at CLKOUT can interact with the crystal oscillator input
COSC preventing the start-up of oscillation. Care must be taken in layout by sufficient
separation of the signal lines to ensure sufficiently small coupling.
3.9 Application Hints on the Power-Amplifier
The power amplifier operates in a high efficient class C mode. This mode is
characterized by a pulsed operation of the power amplifier transistor at a current flow
angle of θ<<π. A frequency selective network at the amplifier output passes the
fundamental frequency component of the pulse spectrum of the collector current to the
load. The load and its resonance transformation to the collector of the power amplifier
can be generalized by the equivalent circuit of Figure 16. The tank circuit L//C//RL in
parallel to the output impedance of the transistor should be in resonance at the
operating frequency of the transmitter.
V
S
L C R
L
Figure 16 Equivalent power amplifier tank circuit
The optimum load at the collector of the power amplifier for “critical” operation under
idealized conditions at resonance is:
2
V
S
R =
LC
2P
O
The theoretical value of R for an RF output power of P = 5 dBm (3.16 mW) is:
LC o
2
3
R = =1423 ?
LC
20.00316
“Critical” operation is characterized by the RF peak voltage swing at the collector of the
PA transistor to just reach the supply voltage V .
S
The high degree of efficiency under “critical” operating conditions can be explained by
the low power losses at the transistor. During the conducting phase of the transistor, its
collector voltage is very small. This way the power loss of the transistor, equal to i u
C CE
is minimized. This is particularly true for small current flow angles of θ<<π.
Data Sheet 28 V 1.2, 2008-04-04TDK5100F
Applications
In practice the RF-saturation voltage of the PA transistor and other parasitics reduce the
“critical” R .
LC
The output power P is reduced by operating in an “overcritical” mode characterised by
o
R > R .
L LC
The power efficiency (and the bandwidth) increase when operating at a slightly higher
R , as shown in Figure 17.
L
The collector efficiency E is defined as
P
O
E =
V I
S C
The diagram of Figure 17 was measured directly at the PA-output at V = 3 V. Losses in
S
the matching circuitry decrease the output power by about 1.5 dB. As can be seen from
the diagram, 550 ? is the optimum impedance for operation at 3 V. For an approximation
of R and P at other supply voltages those two formulas can be used:
OPT OUT
R ~VS
OPT
and
P ~ R
OUT OPT
10E
Po [mW]
7
6
5
4
3
10E
2
Po
1
0
0 1000 2000 3000
RL [Ohm]
Figure 17 Output power P (mW) and collector efficiency E vs. load resistor R .
o L
The DC collector current I of the power amplifier and the RF output power P vary with
c o
the load resistor R . This is typical for overcritical operation of class C amplifiers. The
L
collector current will show a characteristic dip at the resonance frequency for this type of
“overcritical” operation. The depth of this dip will increase with higher values of R .
L
Data Sheet 29 V 1.2, 2008-04-04TDK5100F
Reference
4 Reference
4.1 Electrical Data
4.1.1 Absolute Maximum Ratings
Attention: The maximum ratings must not be exceeded under any circumstances,
not even momentarily and individually, as permanent damage to the IC
will result.
Table 8 Absolute Maximum Ratings, T = -40 °C … +125 °C
amb
Parameter Symbol Limit Values Unit Remarks
min. max.
Junction Temperature T ?40 +150 °C
J
Storage Temperature T ?40 +125 °C
s
Thermal Resistance R 220 K/W
thJA
Supply voltage V ?0.3 +4.0 V
S
Voltage at any pin V -0.3 V + 0.3 V
pins S
excluding pin 9
Voltage at pin 9 V -0.3 2 V V No ESD-Diode to V
pin9 S S
ESD integrity, all pins V -1 +1 kV JEDEC Standard
ESD
JESD22-A114-B
ESD integrity, all pins V -2 +2 kV JEDEC Standard
ESD
excluding pin 9 JESD22-A114-B
Ambient Temperature under bias: T = ?40°C to +125°C
A
Note: All voltages referred to ground (pins) unless stated otherwise.
Pins 3 and 8 are grounded.
Data Sheet 30 V 1.2, 2008-04-04TDK5100F
Reference
4.2 Operating Ratings
Within the operational range the IC operates as described in the circuit description.
Table 9 Operating Ratings
Parameter Symbol Limit Values Unit Test Conditions
min. max.
Supply voltage V 2.1 4.0 V
S
Ambient temperature T -40 125 °C
A
4.3 AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the specified
supply voltage and ambient temperature. Typical charcateristics are the median of the
production.
4.3.1 AC/DC Characteristic at 3V, 25°C
Table 10 Supply Voltage V =3V, Ambient temperature T =25°C
S amb
Parameter Symbol Limit Values Unit Test
Conditions
min. typ. max.
Current consumption
Power Down mode I 0.3 100 nA V (Pins 10, 6
S PDWN
and 7)
< 0.2 V
PLL Enable mode I 3.5 4.2 mA
S PLL_EN
Transmit mode I 7.7 10.4 mA
S TRANSM
434 MHz
Output frequency
Output frequency f 427 434.5 442 MHz f = 32 f
OUT OUT COSC
Clock Driver Output (Pin 1)
Output current (High) I 5μAV = V
CLKOUT CLKOUT S
Saturation Voltage V 0.56 V I = 1 mA
SATL CLKOUT
1)
(Low)
Data Sheet 31 V 1.2, 2008-04-04TDK5100F
Reference
Table 10 Supply Voltage V =3V, Ambient temperature T =25°C (cont’d)
S amb
Parameter Symbol Limit Values Unit Test
Conditions
min. typ. max.
FSK Switch Output (Pin 4)
On resistance R 250 ? V = 0 V
FSKOUT FSKDTA
On capacitance C 6pFV = 0 V
FSKOUT FSKDTA
Off resistance R 10 k? V = V
FSKOUT FSKDTA S
Off capacitance C 1.5 pF V = V
FSKOUT FSKDTA S
Crystal Oscillator Input (Pin 5)
Load capacitance C 5pF
COSCmax
Serial Resistance of 100 ? f = 13.56 MHz
the crystal
Input inductance of the 4.6 μH f = 13.56 MHz
COSC pin
ASK Modulation Data Input (Pin 6)
ASK Transmit disabled V00.5V
ASKDTA
ASK Transmit enabled V 1.5 V V
ASKDTA S
Input bias current I 30 μA V = V
ASKDTA ASKDTA S
ASKDTA
Input bias current I -20 μA V = 0 V
ASKDTA ASKDTA
ASKDTA
ASK data rate f 20 kHz
ASKDTA
FSK Modulation Data Input (Pin 7)
FSK Switch on V00.5V
FSKDTA
FSK Switch off V 1.5 V V
FSKDTA S
Input bias current I 30 μA V = V
FSKDTA FSKDTA
S
FSKDTA
Input bias current I -20 μA V = 0 V
FSKDTA FSKDTA
FSKDTA
FSK data rate f 20 kHz
FSKDTA
Power Amplifier Output (Pin 9)
2)
Output Power at 434 P 3.0 5.2 7.4 dBm
OUT434
MHz transformed to
50 Ohm
Data Sheet 32 V 1.2, 2008-04-04TDK5100F
Reference
Table 10 Supply Voltage V =3V, Ambient temperature T =25°C (cont’d)
S amb
Parameter Symbol Limit Values Unit Test
Conditions
min. typ. max.
Power Down Mode Control (Pin 10)
Power Down mode V00.7VV < 0.2 V
PDWN ASKDTA
V < 0.2 V
FSKDTA
PLL Enable mode V 1.5 V VV < 0.5 V
PDWN S ASKDTA
Transmit mode V 1.5 V VV > 1.5 V
PDWN S ASKDTA
Input bias current I 30 μA V = V
PDWN PDWN
S
PDWN
1) Derating linearly to a saturation voltage of max. 140 mV at I = 0 mA
CLKOUT
2) Power amplifier in overcritical C-operation
Matching circuitry as used in the 50 Ohm-Output Testboard at the specified frequency.
Tolerances of the passive elements not taken into account.
4.3.2 AC/DC Characteristic at 2.1V ...4.0 V, -40°C ...+125°C
Table 11 Supply Voltage V =2.1V ... 4.0V, T =-40°C ... +125°C
S amb
Parameter Symbol Limit Values Unit Test
Conditions
min. typ. max.
Current consumption
Power Down mode I 4 μA V (Pins 10, 6
S PDWN
and 7) < 0.2 V
PLL Enable mode I 3.5 4.6 mA
S PLL_EN
Transmit mode I 7 10.2 mA V = 2.1 V
S S
TRANSMIT
7.7 10.9 mA V = 3 V
S
8.1 11.4 mA V = 4 V
S
Output frequency
1)
Output frequency f 434 MHz f = 32 f
OUT OUT COSC
Clock Driver Output (Pin 1)
Output current (High) I 5μAV = V
CLKOUT CLKOUT
S
Saturation Voltage V 0.5 V I = 0.6
SATL CLKOUT
2)
(Low) mA
Data Sheet 33 V 1.2, 2008-04-04TDK5100F
Reference
Table 11 Supply Voltage V =2.1V ... 4.0V, T =-40°C ... +125°C (cont’d)
S amb
Parameter Symbol Limit Values Unit Test
Conditions
min. typ. max.
FSK Switch Output (Pin 4)
On resistance R 280 ? V = 0 V
FSKOUT FSKDTA
On capacitance C 6pFV = 0 V
FSKOUT FSKDTA
Off resistance R 10 k? V = V
FSKOUT FSKDTA S
Off capacitance C 1.5 pF V = V
FSKOUT FSKDTA S
Crystal Oscillator Input (Pin 5)
Load capacitance C 5pF
COSCmax
Serial Resistance of 100 ? f = 13.56 MHz
the crystal
Input inductance of the 4.6 μH f = 13.56 MHz
COSC pin
ASK Modulation Data Input (Pin 6)
ASK Transmit disabled V00.5V
ASKDTA
ASK Transmit enabled V 1.5 V V
ASKDTA S
Input bias current I 33 μA V = V
ASKDTA ASKDTA
S
ASKDTA
Input bias current I -20 μA V = 0 V
ASKDTA ASKDTA
ASKDTA
ASK data rate f 20 kHz
ASKDTA
FSK Modulation Data Input (Pin 7)
FSK Switch on V00.5V
FSKDTA
FSK Switch off V 1.5 V V
FSKDTA S
Input bias current I 33 μA V = V
FSKDTA FSKDTA S
FSKDTA
Input bias current I -20 μA V = 0 V
FSKDTA FSKDTA
FSKDTA
FSK data rate f 20 kHz
FSKDTA
Data Sheet 34 V 1.2, 2008-04-04TDK5100F
Reference
Table 11 Supply Voltage V =2.1V ... 4.0V, T =-40°C ... +125°C (cont’d)
S amb
Parameter Symbol Limit Values Unit Test
Conditions
min. typ. max.
Power Amplifier Output (Pin 9)
3)
Output Power at 434 P -0.8 2.4 4.8 dBm V = 2.1 V
OUT, 434 S
MHz
P 0.0 5.2 7.7 dBm V = 3.0 V
OUT, 434
S
transformed to 50
P 0.5 6.9 10.6 dBm V = 4.0 V
OUT, 434 S
Ohm.
Power Down Mode Control (Pin 10)
Power Down mode V00.5VV < 0.2 V
PDWN ASKDTA
V < 0.2 V
FSKDTA
PLL Enable mode V 1.5 V VV < 0.5 V
PDWN S ASKDTA
Transmit mode V 1.5 V VV > 1.5 V
PDWN S ASKDTA
Input bias current I 38 μA V = V
PDWN PDWN
S
PDWN
1) a) When the minimum T is increased by 5°C, the minimum f decreases by 1 MHz.
A VCO
b) When the maximum T is decreased by 5°C, the maximum f increases by 1 MHz.
A VCO
c) When the minimum V is increased by 25 mV, the maximum f increases by 1 MHz.
S VCO
Restriction of c): The maximum f must not be increased by more than 40 MHz
VCO
by increasing V .
S
All three measures can be taken independently and additive.
2) Derating linearly to a saturation voltage of max. 140 mV at I = 0 mA
CLKOUT
3) Matching circuitry as used in the 50 Ohm-Output Testboard.
Tolerances of the passive elements not taken into account.
Range @ 2.1 V, +25°C: dBm +/- 2.0 dBm
Typ. temperature dependency at 2.1 V: + 0.4 dBm@-40°C and - 1.3 dBm@+125°C, reference +25°C
Range @ 3.0 V, +25°C: 5.0 dBm +/- 2.2 dBm
Typ. temperature dependency at 3.0 V: + 0.4 dBm@-40°C and - 2.4 dBm@+125°C, reference +25°C
Range @ 4.0 V, +25°C: dBm +/- 3.0 dBm
Typ. temperature dependency at 4.0 V: + 0.8 dBm@-40°C and - 3.3 dBm@+125°C, reference +25°C
Data Sheet 35 V 1.2, 2008-04-04TDK5100F
Package Outlines
5 Package Outlines
3 ±0.1
C
H
0.5
0.1 A
A
+0.15
0.42
0.22 ±0.05
-0.1
M
0.08 A B C
4.9
0.25 M
A B C
±0.1
3
B
Index Marking
Figure 18 PG-TSSOP-10
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet 36 V 1.2, 2008-04-04
+0.08
0.125
-0.05
0.15 max.
0.85 ±0.1
1.1 max.
0.09
6 max.TDK5100F
List of Figures Page
Figure 1 IC Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 3 Power mode control circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 4 ASK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5 FSK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6 Alternative ASK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7 Alternative FSK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8 50 Ohm-output testboard schematic . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9 Top Side of TDK5100 F-Testboard with 50 Ohm-Output. . . . . . . . . . . 20
Figure 10 Bottom Side of TDK5100 F-Testboard with 50 Ohm-Output . . . . . . . . 20
Figure 11 Stripline-antenna testboard schematic. . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12 Top Side of TDK5100 F-Testboard with Stripline-Antenna . . . . . . . . . 23
Figure 13 Bottom Side of TDK5100 F-Testboard with Stripline-Antenna. . . . . . . 23
Figure 14 Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15 FSK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 16 Equivalent power amplifier tank circuit. . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 17 Output power Po (mW) and collector efficiency E vs. load resistor RL. 29
Figure 18 PG-TSSOP-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Data Sheet 37 V 1.2, 2008-04-04TDK5100F
List of Tables Page
Table 1 Order Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2 Pin Definition and Functions - Overview . . . . . . . . . . . . . . . . . . . . . . . . 7
1)
Table 3 Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4 FSKDTA - FSK Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5 ASKDTA - Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6 Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7 Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 8 Absolute Maximum Ratings, T = -40 °C … +125 °C . . . . . . . . . . . . 30
amb
Table 9 Operating Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 10 Supply Voltage V =3V, Ambient temperature T =25°C . . . . . . . . . . 31
S amb
Table 11 Supply Voltage V =2.1V ... 4.0V, T =-40°C ... +125°C. . . . . . . . . . . 33
S amb
Data Sheet 38 V 1.2, 2008-04-04www.infineon.com
Published by Infineon Technologies AG |
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