磁阻 RAM (MRAM)似乎在最先进的节点上获得了关注,部分原因是存储器本身最近的改进,部分原因是新市场需要 MRAM 可能唯一合格的解决方案。磁阻 RAM (MRAM) 似乎处于最先进的 对于MRAM仍然存在很多怀疑者,并且存在很多潜在的竞争对手。这限制了 MRAM 的应用范围过去几十年来,受到阻碍成本高、密度低、耐用性低。但支持者的数量正在不断增长。 图 1:2022-2033 年独立存储器年出货量(按tes 计算)。资料来源:Objective Analysis/Coughlin Associates, 2023 如今,MRAM 有两种主要类型,独立式和嵌入式,以及三个主要应用领域:现在
“帧缓冲型 MRAM 用于摄影或视频,并针对耐力和速度进行了调整,”西门子 EDA的 Tessent 高级工程总监 Martin Keim 说道。“代价是波动性仅下降到几秒钟。但如果您只是拍摄一张照片,则需要将其在硅片内部存储一秒钟,然后将其移动到永久存储中。最终,不同 MRAM 的优势实际上取决于您想要构建的内容。” 代工厂提供不同的 MRAM 变体,每种变体都有不同的 PPA 指标。Synopsys产品经理 Bhavana Chaurasia 表示:“市场空间需要不同的 eMRAM 变体来提供某些 PPA 指标。” “例如也就是说,与非易失性 eMRAM 相比,其中一种可能更像 SRAM,速度更高,面积更小,但保留期较短,而非易失性 eMRAM 则具有较高的保留期,但速度较慢,面积稍大。因此,现在您可以灵活地根据应用和目标市场,决定为您的 SoC 使用哪种类型的 eMRAM。” MRAM 并不是前沿节点上的完美解决方案,而且它肯定不会取代 DRAM(这是我们最初的目标)。Rambus Labs高级副总裁 Gary Bronner 解释说:“几种新兴内存技术已经发展到可以生产 Mb 到 Gb 密度的水平。” “其中包括相变存储器,例如 PCM 或 3D Xpoint、MRAM 和 ReRAM。然而,为了取代 DRAM,这些存储器需要具有与 DRAM 相似的性能,但成本要更高。目前还没有一种新兴存储器能够证明取代 DRAM 所需的成本和性能。MRAM 和 ReRAM 正在寻找嵌入式闪存的替代品,其中 MRAM 是性能更高、成本更高的选择,而 ReRAM 是经济高效的替代方案。” 尽管如此,MRAM 的足迹似乎仍在扩大。新的发展有助于克服其历史局限性。同时,闪存在前沿节点受到限制,而MRAM特别适合汽车应用。尽管如此, IMEC磁学项目总监 Sebastien Couet 表示:“MRAM 对微电子行业变得非常重要,因为在先进逻辑节点上缺乏替代闪存的解决方案。” “过去两到三年,大多数主要代工厂基本上都在生产 STT MRAM。这是重要的第一步,因为在业界引入新的内存技术非常罕见。SRAM、DRAM 和闪存在过去 50 年中取得了长足的发展,但从根本上来说,它们是相同的技术。我们达到了 [MRAM] 的大批量制造能力,这是一个非常重要的里程碑。预计未来5到10年将大幅增长。” 磁共振血管造影MRAM应用磁随机存储器应用 MRAM 也在企业界找到了用武之地ise存储,如 IBM 的闪存核心模块(图 3,第 1 栏),其中 Everspin 的 MRAM 用作意外断电时的缓冲区。 Objective Analysis 首席分析师 Jim Handy 指出,此外,MRAM 还用于工业应用。作为一个例子,他引用了如何保持精心设计的工业机器人通过保持正确的手臂位置,在断电后重新启动时可以避免相互碰撞。 “其中一些应用程序需要具有非常快的写入能力,并且需要是非易失性的,”Handy 解释道。“如今大容量的非易失性存储器是 NAND 闪存、NOR 闪存和 EEPROM,这是一个非常小的市场。这三者的写入速度都非常慢,并且消耗大量能量,这使得它们对于某些需要快速存储数据的应用程序来说并不受欢迎。另一种选择是 SRAM,带有电池来支持它,但这并不受欢迎,因为电池需要每隔几年更换一次。” eMRAM 在汽车领域的应用 eMRAM 在汽车领域的应用 “在 32nm 节点以下,成本将闪存与 CPU 结合在一起的技术正在飞速发展,因为制造它的方法与逻辑不同,”imec 的 Couvet 说。“您需要在晶圆厂中制定特定步骤来仅制造闪存。在某种程度上,闪存制造成本比其他制造成本更高,这确实变得疯狂,因此业界正在寻找解决方案。” 解决方案是 eMRAM。2022 年,瑞萨电子在 2002 年 VLSI 研讨会上宣布推出STT-MRAM 测试芯片时解决了这个问题,“与采用 FEOL 制造的闪存相比,在 22 nm 以下工艺中,采用 BEOL 制造的 MRAM 具有优势,因为它与现有 CMOS 兼容该公司当时表示,解决方案 IBM 的态度更加乐观。IBM杰出研究人员兼高级经理 Daniel W orledge表示:“大约三年后,您将能够指着街上的每辆新车并说该车内有 eMRAM。” “先进节点中不再有嵌入式闪存,所有代工厂都已停止开发它。过渡期为 22 纳米和 28 纳米,具体取决于代工厂。” IBM 的态度更加乐观。 IBM 杰出研究人员兼高级经理 Daniel W orledge 表示:“差不多三年后,你将能够指着街上的每辆新车并说该车内有 eMRAM。” “先进性节点中不再有有嵌入式边框,所有代工厂都已停止开发。过渡期为 22 纳米和 28 纳米,具体取决于代工厂。” 嵌入式 MRAM 本质上也是可扩展的。Chaurasia 表示:“eFlash 已达到 28 纳米以下的规模极限,而使用 eMRAM,您可以设计支持较低技术节点的嵌入式非易失性存储器。” “这样做的好处是实现了核心和内存的可扩展性。内存可以保留为同一芯片的一部分,与其他选项相比,这有助于实现更小的面积以及更好的性能和功耗,而将内存保留在单独的芯片中,这会导致接口的性能和功耗损失并增加安全问题。eMRAM 具有更小的面积、更低的泄漏、更高的容量和更好的抗辐射能力。与 PCRAM 和 ReRAM 相比,eMRAM 具有更低的温度敏感性,提供更好的生产级良率,并提供更长的耐用性(在多年的多个读/写周期中保留数据)。它允许字级擦除和编程操作,使其成为高能效的 NVM 解决方案。所有这些优势使 eMRAM 成为出色的 eNVM。” 所有这些优势都可能使 eMRAM 成为汽车存储器的未来,至少其支持者如此认为。然而,并非所有人都同意。 “当我们与汽车客户交谈时,他们更喜欢 ReRAM 而不是 MRAM,”Keim 说。“我们听到的争论是温度稳定性以及汽车环境中的磁场影响 MRAM 中存储的数据的担忧。对于前者,现在的 MRAM 类型确实具有汽车市场所需的温度稳定性(-40C 至 +150C)。这表明 MRAM 技术正在迅速扩展到应用领域的各个角落。他们的产品化已经发展到什么程度,以便汽车用户可以选择市场上现成的产品,这是一个不同的问题。” 另一方面,MRAM 的合法读取值 0 和 1 之间的差距非常窄(请参阅下面的调整讨论)。这个小间隙随着温度的升高而变窄和变化,使得安全地解释读取值变得更加困难。ReRAM 中 0 和 1 之间的电阻间隙要宽得多,因此更容易读取,即更容易在较高温度下操作。相反,MRAM 即便如此,今年 5 月,恩智浦和台积电宣布推出首款用于汽车的16 纳米 finFET eMRAM,与闪存的 1 分钟相比,它可以在大约 3 秒内更新 20MB 的代码,提供高达 100 万次更新周期,耐用性水平是闪存的 10 倍甚至 新旧内存类型之间的竞争不仅仅是技术和财务方面的竞争。想象一下,如果救护车必须暂停一分钟才能启动。 技术进步技术进步 这种新的物理原理催生了更有效的 MRAM。STT MRAM 核心的 MTJ 由两个磁性电极和其间的一个介电隧道势垒组成。“基本上,MJT 负责检测两个电极之一的磁性状态,”Couet 解释道。“在 MRAM 中,你有一个固定磁铁,然后是隧道势垒,然后是一个自由磁铁,你可以将其编程为指向上或指向下,例如。然后你比较一下。之后,结的电阻取决于电极的排列。如果两个电极在其磁铁方面以平行配置对齐ic 状态,则它们具有低电阻。如果它们是反平行的,则它们具有高电阻。这提供了一种区分磁铁朝上和朝下的方法,因此您可以通过这种方式存储信息。正如硬盘驱动器所知道的那样,磁铁可以长时间保持稳定。”这种新的物理原理催生了更有效的 MRAM。STT MRAM 核心的 MTJ 由两个磁性电极和其间的一个电介质隧道组成。“基本上,MJT负责检测两个电极之一的磁性状态,”Couet解释道。“在MRAM中,你有一个固定磁铁,然后是隧道势垒,然后可以是一个自由磁铁,你将其电位器指向上方或指向下方。然后你比较一下。之后,结的电阻依靠电极的排列。如果两个电极在其差分状态方面以平行配置水平,则它们具有低电阻。如果它们是反的的平行,则它们具有高电阻。这提供了一种具有区分磁性朝上和朝下的方法,因此您可以通过这种方式存储信息。正如硬盘驱动器所知道的那样,磁性可以长期保持稳定。” STT MRAM 目前占主导地位。现场切换 MRAM(现称为切换 MRAM)是一种早期形式,由摩托罗拉飞思卡尔于 2006 年首次推向市场,飞思卡尔后来被分拆并合并为 Everspin Technologies。Everspin 以切换和 STT 形式提供当今市场上的大部分独立 MRAM。 “In toggle MRAM, the polarity is changed by applying a magnetic field across the MTJ,” explained Joe O’Hare, senior director of marketing at Everspin. “By contrast, STT MRAM technology uses the spin-transfer torque property, or the manipulation of the spin of electrons with a polarizing current.” Fig. 2: Toggle field-switched and spin-transfer torque magnetic tunnel junction operation. Source: Everspin In 2010, Worledge and his IBM colleagues, and the Ohno lab at Tohoku University in Japan, both published papers showing perpendicular STT MRAM, which inspired the current interest. “Before then, MRAM was kind of a laboratory curiosity,” said Worledge. “You could make some bits but they didn’t switch reliably. The reason was all the magnetization was in-plane, but that’s very inefficient. What you want is to have magnetization perpendicular to the plane of the wafer.” Although the answer had been known theoretically since 1996, it would take over a decade to craft the right combination of physics and materials to achieve optimal switching. “Perpendicular bits solve the write problem,” Worledge explained. “And that’s what kicked off all of this excitement. All the big companies jumped in and started to work on STT RAM.” There’s also a new variation called spin-orbit torque (SOT)-MRAM, which imec has been refining. As Couet explained in a blog, “The main difference between STT- and SOT-MRAM resides in the current injection geometry used for the write process. While in STT-MRAM, the current is injected perpendicularly into the MTJ, current injection in SOT-MRAM happens in-plane, in an adjacent SOT layer.” Learning Curve 学习曲线 “When you buy a SRAM or DRAM off the market, they’re all more or less the same,” Keim said. “With the MRAMs, with all the different underlying physics and properties, you can run into trouble if you choose the wrong one.” MRAMs have probabilistic behaviors, so they also come with a lot of error correction. “Normally, you have an ECC that has maybe one bit of error correction and two bits of error detection. MRAM is one level up, at least two-bit correction and three-bit detection,” Keim said. “And then, the ECC is going to correct the improbability of the MRAM. So together, you gain the behavior of a deterministic, just like an SRAM, but it costs you.” There’s an additional issue, as well. “When you turn on an SRAM and you’re writing and reading, it just works. With MRAM, you first have to train your reading and writing circuitry on the actual properties of the cell, in what’s called 'trimming,’ he said. “Trimming means you have to find your comparison value, your resistive value, that makes you decide if what you have just read should be interpreted as a 0 or a 1. So there is an entire cycle of trim learning that the MRAM needs for both reads and writes.” It doesn’t end there. “Different sections of the memory need different trim values. There is a whole process involved to get that thing actually working,” he said. “Once you have accomplished that, you have your beefed up ECC, you have done your trim circuitry, which needs to be on-chip. It’s too much data to be done off-chip, it would be too time-consuming and expensive. So you have to invest additional hardware just for that trim learning. The only viable solution is to do all of this on-chip, fully automated and self-contained. To further reduce the area costs, you want to take advantage of the DFT you already have, namely a memory built-in self-test (MBiST) engine.” The good news is that after all that additional time and money have been invested, the memory works quite well. MRAM’s thermal advantages By contrast, one of the important reasons for eMRAM’s success is that it stays stable at high temperatures — so much so that it can retain data through solder reflow. However, its thermal advantage also explains its relative lack of endurance. “Because you need to have really good data retention in order to withstand solder reflow, you have to make the magnetic bit really difficult to switch, because you don’t want it to switch during thermal fluctuations,” IBM’s Worledge said. “That means it’s also difficult to switch when you write it, so you have to apply a larger voltage to write it. That larger voltage will damage the MgO tunnel barrier over time.” MRAM magnetic field disadvantages “Like any magnetic component, eMRAM should maintain a distance from other magnetic components,” said Chaurasia. “For example, there can be inductor coils within an SoC or die. A certain distance between such devices reduces the magnetic effect. Hence, it must be maintained when designing a chip. For off-chip magnetic immunity, advanced packaging can provide shielding. Air gaps above the eMRAM block or the device can also provide immunity from magnetic sensitivity.” Unlike being near MRI machines, which is a definite no-no, IBM’s Worledge said proximity to small motors and small inductor coils should not be an issue. Nevertheless, he did suggest one nightmare scenario — an attacker using a neodymium iron boron magnet potentially could disable eMRAM chips, so it would be best to put such chips at least a centimeter away from the surface of devices, especially cars. The future of MRAM MRAM 的未来 Fig. 3: Standalone MRAM and embedded non-volatile MRAM are already in the market. Mobile cache MRAM and last-level cache MRAM are in development. Source: IBM Worledge is confident there’s a killer app in eMRAM’s future. “Let’s say you had an IoT device that’s powered by solar power. Maybe it’s part of a security system. It’s normally off, maybe it has a little sensor on it to pick up some audio. When the audio gets loud enough, it wakes up and tries to determine with some AI algorithm whether or not there’s an intruder. Without eMRAM, it would wake up, load the weights for the AI program from flash into SRAM, then run the AI program. If the weights were updated, they’d have to write back to flash, which is incredibly power-intensive. But with eMRAM alone, when the device wakes up, it just starts operating because all the weights are already inside the eMRAM.” Such a scheme would be slower than SRAM, but the advantage is lower power compared to writing data back and forth between the flash and SRAM, and its endurance would make it ideal for field operations, he said. IBM’s “holy grail,” which the company has been working on for nearly a quarter of a century, is last-level cache. Current cache schemes depend on SRAM for working memory and can have a hiccup called a “cache miss,” in which the data isn’t in SRAM. That forces the SRAM to go all the way out to DRAM to get the data. “It’s a very slow, like 35 nanoseconds or 50 nanoseconds round-trip,” said Worledge. “You’d really like to have a bigger SRAM cache if you could. If the MRAM was twice as dense as SRAM, you’d have twice as many bits in there. It would be a little slower than the SRAM, but you more than make up for the slower speed with having twice as many bits.” Worledge believes they’re finally within striking distance. “It’s a very challenging application because you need the MRAM to be very dense and very fast and high endurance,” he said. “We still need to lower the switching current. We published on a new device we invented called the double spin torque magnetic tunnel junction that does lower the switching current by a factor of two. We even showed 250-picosecond switching, which is incredibly fast compared to all other MRAM publications. There’s a lot of promise there, but we’re still in research mode on that.” |
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