Challenges Grow For Creating Smaller Bumps For Flip Chips

New bump structures are being developed to enable higher interconnect densities in flip-chip packaging, but they are complex, expensive, and increasingly difficult to manufacture.
人们正在开发新的凸块结构，以在倒装芯片封装中实现更高的互连密度，但它们复杂、昂贵且制造越来越困难。

For products with high pin counts, flip-chip [1] packages have long been a popular choice because they utilize the whole die area for interconnect. The technology has been in use since the 1970s, starting with IBM’s C4 (controlled collapse chip connection), but it really came into widespread use in the 1990s.
对于高引脚数的产品，倒装芯片 [1] 封装长期以来一直是一种流行的选择，因为它们利用整个芯片区域进行互连。该技术从 20 世纪 70 年代就开始使用，从 IBM 的 C4（受控塌陷芯片连接）开始，但真正广泛使用是在 90 年代。

Since then, bump technology has evolved to handle increasing power and signal connection density required by memory, high-performance computing, and mobile computing devices. Meeting that demand requires new interconnect technology that enables smaller bump pitches, which currently is in production.
从那时起，凸点技术不断发展，以应对存储器、高性能计算和移动计算设备所需的不断增加的功率和信号连接密度。满足这一需求需要新的互连技术来实现更小的凸点间距，目前该技术正在生产中。

Viewed over time, the roadmap for flip-chip interconnect progresses from lead-free bumps to copper pillars, and then to copper microbumps. Pitch sizes continue to shrink, which in turn has created manufacturing challenges for bumping and bonding.
随着时间的推移，倒装芯片互连的路线图从无铅凸块发展到铜柱，然后发展到铜微凸块。间距尺寸不断缩小，这反过来又给凸块和粘合带来了制造挑战。

Fig. 1: Flip-chip technology pitch ranges. Source: A. Meixner/Semiconductor Engineering
图 1：倒装芯片技术的音高范围。来源：A. Meixner/半导体工程

Fig. 2: Flip-chip components. Source: Wikipedia
图 2：倒装芯片元件。资料来源：维基百科

“In the flip-chip arena­ — 250-micron pitch and below — it originally was tin-lead bumps, and one of the big moves was to lead-free. But when you start reaching 100 microns or below, you start seeing more of a copper pillar, though there’s an overlap as we see copper pillars up to 250 microns,” said Jeff Schaefer, senior process engineer at Promex Industries. “With the 250-micron pitch, we see 130-micron bump sizes or copper pillar diameters. Once we get around the 100 micron pitch, it’s 80-micron diameter. The smallest I’ve seen is a 62.5 micron pitch with a 40 micron pillar. I expect to start seeing 50-micron pitch soon.”
“在倒装芯片领域 - 250 微米间距及以下 - 最初是锡铅凸块，而重大举措之一是无铅化。但当你开始达到 100 微米或以下时，你开始看到更多的铜柱，尽管当我们看到高达 250 微米的铜柱时存在重叠，”Promex Industries 的高级工艺工程师 Jeff Schaefer 说道。 “在 250 微米的间距下，我们看到了 130 微米的凸块尺寸或铜柱直径。一旦我们达到 100 微米的间距，它的直径就是 80 微米。我见过的最小的间距是 62.5 微米，柱子直径是 40 微米。我预计很快就会开始看到 50 微米的间距。”

The basic flip-chip process begins after circuit fabrication, when metal pads are created on the die surface to connect to the I/Os. Next comes wafer bumping, where a solder ball is deposited on each pad. The wafer is then diced, and those dies are flipped and positioned so the solder balls align with the substrate pads. The solder balls are then melted/reflowed, typically using hot air, and a mounted die is underfilled with an electrically insulating adhesive, usually using capillary action. [1]
基本的倒装芯片工艺在电路制造之后开始，此时在芯片表面创建金属焊盘以连接到 I/O。接下来是晶圆凸点，其中焊球沉积在每个焊盘上。然后将晶圆切割，并将这些芯片翻转并定位，使焊球与基板焊盘对齐。然后，通常使用热空气将焊球熔化/回流，并且通常使用毛细管作用用电绝缘粘合剂对安装的芯片进行底部填充。 [1]

Fig. 3: Flip-chip manufacturing process. Source: Wikipedia
图 3：倒装芯片制造工艺。资料来源：维基百科

Moving to a copper pillar or microbump requires lithography to create these structures.
转向铜柱或微凸块需要光刻来创建这些结构。

“Copper pillar is generally used below 130µm pitch, because instead of being a circular solder bump, the copper pillar is mostly a Cu post with solder on top,” said Doug Scott, senior vice president of wafer level packaging at Amkor Technology. “This allows for the copper pillar bumps to be placed closer together without risk of the solder connecting together during assembly reflow — generally, ~40 µm Cu + ~25 µm.”
“铜柱通常使用在 130μm 节距以下，因为铜柱不是圆形焊料凸点，而是主要是顶部有焊料的铜柱，”Amkor Technology 晶圆级封装高级副总裁 Doug Scott 说道。 “这使得铜柱凸块可以更靠近地放置在一起，而不会在组装回流期间出现焊料连接在一起的风险 - 通常，〜40 µm Cu +〜25 µm。”

There are variations on the theme, as well. “Microbump, which is a common term used where you have an interconnect between silicon-to-silicon, is slightly different because the CTE (coefficient of thermal expansion) is generally the same,” said Mark Gerber, senior director for engineering/technical marketing at ASE Group. “Some of the general design rules used for copper pillar are the same, but the flat surface topography and low stress joints allow for flexibility of the underfill being used. This can also drive the individual bump pitch. Today, a 35µm bump full-array pitch is possible, due to the routing considerations mentioned before, for the wafer-level or fab-level routing that is used.”
主题也有不同的变化。 “微凸块是硅与硅之间互连的常用术语，它略有不同，因为 CTE（热膨胀系数）通常是相同的，”工程/技术营销高级总监 Mark Gerber 说道在日月光集团。 “铜柱使用的一些通用设计规则是相同的，但平坦的表面形貌和低应力接头允许使用底部填充的灵活性。这也可以驱动各个凸点间距。如今，由于前面提到的布线考虑因素，对于所使用的晶圆级或晶圆厂级布线，35μm 凸块全阵列间距是可能的。”

The Heterogeneous Integration Roadmap [2] describes all aspects of packaging, including die-to-substrate interconnects ranging from wire-bonds to through-silicon vias. With flip-chip packages die-to-substrate interconnects, substrate redistribution areas, and substrate-to-board interconnects all play a role in the manufacturing limits.
异构集成路线图 [2] 描述了封装的各个方面，包括从焊线到硅通孔的芯片到基板互连。对于倒装芯片封装，芯片到基板互连、基板重新分布区域以及基板到板互连都在制造限制中发挥着作用。

Fig. 4: Conceptual diagram of flip-chip packaging. Source: A. Meixner/Semiconductor Engineering
图 4：倒装芯片封装的概念图。来源：A. Meixner/半导体工程

Chapter 8 of the Heterogeneous Integration Roadmap [3] documents the landscape of current and projected packaging technology pitches. The minimum pitch of each flip-chip interconnect technology is captured in Table 1 of subsection 8.7 (page 41).
异构集成路线图 [3] 第 8 章记录了当前和预计的封装技术发展前景。每种倒装芯片互连技术的最小间距见第 8.7 小节（第 41 页）的表 1。

The corresponding table for substrate interconnect (the part that connects package to board) is found in subsection 8.8 (page 43).
基板互连（将封装连接到电路板的部分）的相应表可在第 8.8 小节（第 43 页）中找到。

With each change in interconnect technology comes new processes and their limits, which drive innovation, yield management, and defect inspection.
随着互连技术的每一次变化，都会出现新的工艺及其限制，从而推动创新、良率管理和缺陷检查。

Bumping technology limits
突破技术限制
Bumping technology is measured by pitch, size, height, and electrical and mechanical properties. Thermal considerations vary depending upon the CTE mismatch of material. Warpage is a concern for larger die and wafers, which is exacerbated by back grinding of a wafer prior to die attach.
凸点技术通过间距、尺寸、高度以及电气和机械特性来衡量。热考虑因素因材料的 CTE 不匹配而异。对于较大的芯片和晶圆来说，翘曲是一个令人担忧的问题，在芯片贴装之前对晶圆进行背面研磨会加剧翘曲。

“There are a number of drivers for pitch limitations for each type of interconnect,” said ASE’s Gerber. “Starting with traditional solder bump flip chip interconnect, the pitch capability is determined by collapse height for underfill, capture pad pitch for trace routing, capture pad pitch for bump-to-bump short risk and several other pitch related sensitivities. The pre-mounted bump height has a defined height, but as IBM defined the C4 term — Controlled Collapse Chip Connection — the diameter of the solder bump and the capture pad size will determine the 'collapse or final height’ of the interconnect. This is the main pitch-limiting factor for using solder bumps related to pitch.”
ASE 的 Gerber 表示：“每种互连类型的间距限制都有许多驱动因素。” “从传统焊料凸块倒装芯片互连开始，间距能力由底部填充的塌陷高度、走线布线的捕获焊盘间距、凸块到凸块短路风险的捕获焊盘间距以及其他几个与间距相关的敏感性决定。预安装凸块高度具有定义的高度，但正如 IBM 定义的 C4 术语——受控塌陷芯片连接——焊料凸块的直径和定位焊盘尺寸将决定互连的“塌陷或最终高度”。这是使用与间距相关的焊料凸块的主要间距限制因素。”

Bump height is determined by design, but also processing choices.
凸块高度由设计决定，也由加工选择决定。 

“For standard plated solder bumps and copper pillar bumps, pre-assembly bump heights are generally around 70µm to 75 µm, with collapsed bump heights after assembly of ~50 µm to allow for x,y,z space for underfill flow between the bumps. Microbumps will have much lower bump heights and involve plating much less solder. Specifically, microbumps can be less than 10µm tall with reduced Cu and solder heights depending on pitch and end need,” said Amkor’s Scott. “Standard plated solder bumps are generally used on pitches ranging from 130µm to 250µm. Below 130µm, there is not enough x-y space between bumps when starting with a 70µm pre-assembly bump height.”
“对于标准电镀焊料凸块和铜柱凸块，预组装凸块高度通常约为 70μm 至 75μm，组装后塌陷的凸块高度约为 50μm，以便为凸块之间的底部填充流动留出 x、y、z 空间。微凸块的凸块高度要低得多，并且需要电镀更少的焊料。具体来说，微凸块的高度可以低于 10μm，并且根据间距和最终需求降低铜和焊料高度，”Amkor 的 Scott 说道。 “标准电镀焊料凸块通常用于 130μm 至 250μm 的间距。当预组装凸块高度低于 130μm 时，凸块之间没有足够的 x-y 空间。”

Creating copper pillars requires more processing steps than solder bumps.
创建铜柱比焊料凸块需要更多的处理步骤。

“When we transitioned to the die-to-die world the technology is different because now you’re dealing with a wafer and the planerites are so good compared to die to substrate. First you create the copper pillar, on the initial wafer that’s going to get the solder or the copper pillar there is first an under bump metal (UBM). It’s a little cap over the opening that goes down into the silicon. Then we build a copper core from that and then put a tin cap on it. So then the receiving wafer, they look like they have a UBM pad there and it’s usually has some nickel gold type plating on it so that it’s nice and pristine,” explained Promex Industries’ Schaefer. So instead of having a slight indentation like a laminate substrate, you have a slight extrusion. We’ve found that we’re able to actually solder them wet without 'solder on pad.’ It’s how they’re designed and built. It almost acts like a solder and pad because it’s a little dome as opposed to trying to get down inside of a hole.”
“当我们过渡到芯片到芯片的世界时，技术就不同了，因为现在你处理的是晶圆，与芯片到基板相比，平面晶石非常好。首先，您创建铜柱，在将要获得焊料或铜柱的初始晶圆上，首先有凸块下金属 (UBM)。它是一个小盖子，盖在向下进入硅的开口上。然后我们用它制作一个铜芯，然后在上面放一个锡帽。那么接收晶圆，它们看起来就像有一个 UBM 焊盘，上面通常有一些镍金类型的电镀，所以它很漂亮而且原始，”Promex Industries 的 Schaefer 解释道。因此，您不会像层压基板那样有轻微的压痕，而是会轻微挤压。我们发现我们能够实际湿焊它们，而无需“焊盘上的焊料”。这就是它们的设计和制造方式。它的作用几乎就像焊料和焊盘，因为它是一个小圆顶，而不是试图进入孔内。”

“For copper pillar, which consists of a copper post and a solder cap at the tip, the copper post height can be defined to the limitation of one or more photo-resist layer thicknesses and as you reduce the pitch, the aspect ratio of the cu post height to pitch becomes the limitation along with the photo resist material and imaging tool capabilities,” said Gerber. “A secondary limitation for the copper pillar interconnect is the substrate design rules used. For fine pitch >110um pitch, 2 primary methods are used- BOT (Bond on Trace) or ET – Embedded Trace, where the solder cap of the copper pillar is placed on top of the trace instead of a traditional capture pad. Copper pillar size and shape, including the limitations above, can provide a limit to the capabilities and roadmap for continuing to shrink the pitches. Many of these limitations are due to the ability to route traces in-between the pillars on the substrate side. As new technologies are available, such as wafer-level RDL, the interconnect roadmaps will be pushed further, but still with limitations around the height/aspect ratio for manufacturing processes such as underfill.”
“对于由铜柱和尖端处的焊帽组成的铜柱，铜柱高度可以定义为一层或多层光刻胶层厚度的限制，并且当减小间距时，铜柱的纵横比会受到限制。铜柱高度与间距以及光刻胶材料和成像工具功能都成为限制，”Gerber 说。 “铜柱互连的第二个限制是所使用的基板设计规则。对于 >110um 间距的细间距，使用两种主要方法 - BOT（迹线焊接）或 ET - 嵌入式迹线，其中铜柱的焊帽放置在迹线顶部，而不是传统的捕获焊盘。铜柱的尺寸和形状，包括上述限制，可能会限制继续缩小间距的能力和路线图。其中许多限制是由于在基板侧的柱之间布线的能力造成的。随着晶圆级 RDL 等新技术的出现，互连路线图将进一步推进，但仍存在底部填充等制造工艺的高度/纵横比方面的限制。”

Others agree that underfill process comes with challenges. “As you get finer pitch smaller bumps, they get shorter. It’s now getting hard to find underfills to get underneath. The underfills have historically been designed to get under a 5-mil gap, and now they come down to 3 mils, which is 75 microns,” said Schaefer. “Now we’re starting to see 60 and 25 micron gaps. I’m sure people are working on new underfills. But there’s a lot of things to work on. For one, as you get finer particulates, it becomes more like a sludge, which makes it harder to flow. This is a roadblock that needs to be removed.”
其他人也认为底部填充工艺面临着挑战。 “当你得到更细间距的更小的凸块时，它们就会变得更短。现在很难找到底部填充材料。以往，底部填充胶的间隙被设计为小于 5 密耳，现在已降至 3 密耳，即 75 微米。”Schaefer 说道。 “现在我们开始看到 60 和 25 微米的间隙。我确信人们正在研究新的底部填充材料。但还有很多事情需要努力。其一，当颗粒变得更细时，它会变得更像污泥，从而更难流动。这是一个需要消除的障碍。”

Managing yield 管理产量
As bumping technology gets smaller, additional processing steps — for example, lithography for creating copper pillars — open up new opportunities for yield detectors. For a successful bonding process, particulates, surface contaminants, and solder bump voiding are problematic for yield. These require process controls, metrology, and inspection.
随着凸块技术变得越来越小，额外的处理步骤（例如，用于创建铜柱的光刻）为良率检测器带来了新的机会。对于成功的键合工艺来说，颗粒物、表面污染物和焊料凸块空洞都会影响良率。这些需要过程控制、计量和检查。

Naturally controlling contamination is required. “Tier 1 OSATs invest to reduce the level of factory contamination sources, and therefore reduce defectivity percentages,” said Amkor’s Scott. “Pitch does not contribute to defectivity. Similar levels of defectivity exist regardless of pitch.”
自然需要控制污染。 “一级 OSAT 投资是为了降低工厂污染源的水平，从而降低缺陷率，”Amkor 的 Scott 说。 “沥青不会导致缺陷。无论音高如何，都存在类似水平的缺陷。”

But pitch adds some of its own challenges. “As pitch becomes smaller and the bump size is reduced, particle contamination management is very important. For other types of interconnects such as hybrid bonding, where pitches are reduced below 30µm and the surface-to-surface contact is important, wafer-based clean room environment is critical to yields,” said ASE’s Gerber.
但推销本身也带来了一些挑战。 “随着节距变小和凸块尺寸减小，颗粒污染管理非常重要。对于其他类型的互连，例如混合键合，其间距减小到 30μm 以下，并且表面到表面的接触很重要，基于晶圆的洁净室环境对于良率至关重要，”ASE 的 Gerber 说道。

Preparing for the underfill process should not be underestimated either.
底部填充工艺的准备工作也不可低估。

“Generally with a laminate, you’re going to do an underfill after you do the flip chip,” said Promex’s Schaefer. “We determine where we will place it and how to reflow it. We clean it to get out any flux material under the gap between the die and substrate. Then we’ll underfill with an epoxy that flows. It’s designed to wet in and not leave voids and things of that nature. But there is a challenge as we get to finer pitches. Bumps get a little shorter, and as they get shorter the gap between the chip and the substrate gets smaller, so it’s harder to clean. Imagine sticking two glass slides together to try and get the dirt out between them.”
“一般来说，对于层压板，在进行倒装芯片之后，您需要进行底部填充，”Promex 的 Schaefer 说道。 “我们决定将其放置在哪里以及如何对其进行回流焊。我们对其进行清洁，以清除芯片和基板之间间隙下的任何助焊剂材料。然后我们将用流动的环氧树脂进行底部填充。它的设计目的是润湿而不留下空隙和类似性质的东西。但当我们达到更精细的音调时，就会遇到挑战。凸块变得更短，并且随着它们变短，芯片和基板之间的间隙变得更小，因此更难以清洁。想象一下，将两个载玻片粘在一起，试图清除它们之间的污垢。”

Metrology and inspection needs
计量和检验需求
For managing process control and yield, metrology and inspection tools play an important role. “There are tools available in the market that can help provide guidance on interconnect integrity, in addition to in-process cross-sectional analysis used at setup and at defined production intervals,” said ASE’s Gerber.
对于管理过程控制和产量，计量和检测工具发挥着重要作用。 ASE 的 Gerber 表示：“市场上有一些工具可以帮助提供有关互连完整性的指导，此外还可以在设置和规定的生产间隔内使用过程中横截面分析。”

The bumping process and the bonding processes each have specific characteristics that need to be monitored. For bumps, metrology focuses on diameter, height, and co-planarity. Smaller pitches require more stringent control of bump diameter and height control. Similarly, as bump height shrinks, the window of co-planarity becomes smaller. Typically, 10% variation is allowed. For example, a 30µm bump height results in a permissible variation of ±3µm. Exceeding this contributes to unsuccessful or poor bonding.
凸块工艺和键合工艺各自具有需要监控的特定特性。对于凸块，计量重点关注直径、高度和共面性。较小的间距需要更严格地控​​制凸块直径和高度。类似地，随着凸块高度缩小，共面性窗口变得更小。通常，允许 10% 的变化。例如，30μm 的凸块高度导致 ±3μm 的允许偏差。超过此值会导致粘合不成功或不良。

Photolithography steps needed for Cu pillar formation comes with limits as well as the substrate design rules.
铜柱形成所需的光刻步骤以及基板设计规则都受到限制。

“Bonding is usually done with mass-reflow ovens,” said Mike Kelly vice president of advanced package and technology integration at Amkor. “The initial characterization of the reflow process is established using shadow-moire for quantifying the warpage during reflow, and temperature mapping of the ovens to ensure consistent temperature control of the flip-chip part itself. During setup, mechanical die lift and inspection to ensure good solder wetting is done. Also, flux is usually applied with a 'dip flux,’ wherein the die bumps are 'dunked’ into thin, tightly controlled flux reservoirs. Visual inspection of these items is done on a sampling basis.”
“键合通常是通过大规模回流焊炉完成的，”Amkor 先进封装和技术集成副总裁 Mike Kelly 说道。 “回流工艺的初始特征是使用阴影云纹来量化回流期间的翘曲，并使用烤箱的温度图来确保倒装芯片部件本身的温度控制一致。在设置过程中，机械芯片提升和检查以确保良好的焊料润湿。此外，助焊剂通常与“浸入助焊剂”一起使用，其中芯片凸块被“浸入”薄的、严格控制的助焊剂储存器中。这些物品的目视检查是在抽样的基础上进行的。”

A variety of inspection and metrology tools are available to support package manufacturing.
有多种检测和计量工具可支持封装制造。

Increasing automation of visual inspection reduces the reliance on operators to view an image and make a decision. The exponential increase in the bump connections is one driver. Changes to bonding processes provide another. A self-aligned solder reflow process is a mature technology. With the thermal compression bonding commonly used in advanced packaging, there are reliability mechanisms that pass electrical testing. That, in turn, prompts the use of X-ray inspection and metrology tools to view the bumps after bonding.
目视检查自动化程度的提高减少了对操作员查看图像和做出决策的依赖。凸块连接的指数增长是驱动因素之一。粘合工艺的改变提供了另一个原因。自对准回流焊工艺是一项成熟的技术。先进封装中常用的热压接合，具有通过电气测试的可靠性机制。这反过来又促使人们使用 X 射线检查和计量工具来查看键合后的凸块。

“For low-complexity packaging, manufacturers could get away with manual X-ray inspection by an operator. While feasible for parts with 100 bumps, scaling beyond 1,000 bumps is a challenge and requires new methods,” noted Frank Chen, director of applications and product management at Bruker. “As complexity increases, achieving sufficient quality and reliability requires investments in both process and metrology tools. Bump height variation is an important indicator of bonding quality. Upgrading to an automated in-line X-ray inspection that can monitor this metric for 100% of the products provides invaluable feedback for process control.”
“对于低复杂性的包装，制造商可以不用操作员进行手动 X 射线检查。虽然对于具有 100 个凸点的零件来说是可行的，但扩展到超过 1,000 个凸点是一个挑战，需要新的方法，”布鲁克应用和产品管理总监 Frank Chen 指出。 “随着复杂性的增加，要实现足够的质量和可靠性就需要对工艺和计量工具进行投资。凸块高度变化是键合质量的重要指标。升级到自动化在线 X 射线检测可以监控 100% 产品的这一指标，为过程控制提供了宝贵的反馈。”

Fig. 5: Bump height monitor from automated in-line X-ray inspection shows high correlation to bonding quality (validated by physical cross-section). Source: Bruker
图 5：自动在线 X 射线检测的凸块高度监视器显示与粘合质量高度相关（通过物理横截面验证）。资料来源：布鲁克

“There are several methods that can or should be used to achieve process control. First, traditional 2D inspection (AOI) for 100% surface defect inspection per process flow (i.e., IQC, OQA, photo, clean, plating, etc.),” said Nathan Peng, product marketing manager at Onto Innovation. “Next, 2D metrology (AOI) can be used to control bump size and diameter sizing control. Furthermore, 3D metrology (AOI) can be used for a sampling bump height/co-planarity metrology information acquisition (this is typically done with a laser triangulation-based technology). Further, 3D metrology can target individual bump height characteristics, typically collected with white light interferometer technology. Also, there are methods to enable detection of organic residues on the bump top that can lead to failure with bump to pad connection.”
“有几种方法可以或应该用于实现过程控制。首先，传统的 2D 检测 (AOI) 对每个工艺流程（即 IQC、OQA、照片、清洁、电镀等）进行 100% 表面缺陷检测，”Onto Innovation 产品营销经理 Nathan Peng 说道。 “接下来，二维计量 (AOI) 可用于控制凸块尺寸和直径尺寸控制。此外，3D 计量 (AOI) 可用于采样凸块高度/共面计量信息采集（这通常通过基于激光三角测量的技术来完成）。此外，3D 计量可以针对单个凸块高度特征，通常使用白光干涉仪技术收集。此外，还有一些方法可以检测凸块顶部的有机残留物，这些残留物可能导致凸块到焊盘的连接失败。”

Conclusion 结论
Products that demand higher interconnect counts continue to drive the interconnect roadmap. Each flip-chip technology has manufacturing limits that involve material properties, shrinking sizes that challenge underfill technologies, and increased use of lithography to create the interconnect structures. Any change in bonding processes results in an increase in metrology and inspection steps to meet yield and quality objectives.
需要更高互连数量的产品继续推动互连路线图的发展。每种倒装芯片技术都存在制造限制，包括材料特性、挑战底部填充技术的尺寸缩小以及增加使用光刻来创建互连结构。键合工艺的任何变化都会导致计量和检测步骤的增加，以满足产量和质量目标。

References 参考

1. https://en./wiki/Flip_chip
2. https://eps./technology/heterogeneous-integration-roadmap/2021-edition.html
3. HIR Chapter 8 Single Chip and Multi Chip Integration, https://eps./images/files/HIR_2021/ch08_smcfinal.pdf
   HIR 第 8 章单芯片和多芯片集成，https://eps./images/files/HIR_2021/ch08_smcfinal.pdf