JEDECStandardNo.21-C
Page4.1.2.11–1
AnnexK:SerialPresenceDetect(SPD)forDDR3SDRAMModules
SPDRevision1.0
1.0Introduction
Thisannexdescribestheserialpresencedetect(SPD)valuesforallDDR3modules.Differencesbetweenmoduletypes
areencapsulatedinsubsectionsofthisannex.ThesepresencedetectvaluesarethosereferencedintheSPDstandard
documentfor‘SpecificFeatures’.ThefollowingSPDfieldswillbedocumentedintheorderpresentedinsection1.1with
theexceptionofbytes60~116whicharedocumentedinseparateannexes,oneforeachfamilyofmoduletypes.Fur-
therdescriptionofByte2isfoundinAnnexAoftheSPDstandard.Allunusedentrieswillbecodedas0x00.Allunused
bitsindefinedbyteswillbecodedas0exceptwherenoted.
Toallowformaximumflexibilityasdevicesevolve,SPDfieldsdescribedinthisdocumentmaysupportdeviceconfigura-
tionandtimingoptionsthatarenotincludedintheJEDECDDR3SDRAMdatasheet(JESD79-3).PleaserefertoDRAM
supplierdatasheetsorJESD79-3todeterminethecompatibilityofcomponents.
1.1Addressmap
ThefollowingistheSPDaddressmapforallDDR3modules.Itdescribeswheretheindividuallookuptableentrieswillbe
heldintheserialEEPROM.
ByteNumber
FunctionDescribed
Notes
0NumberofSerialPDBytesWritten/SPDDeviceSize/CRCCoverage1,2
1SPDRevision
2KeyByte/DRAMDeviceType
3KeyByte/ModuleType
4SDRAMDensityandBanks3
5SDRAMAddressing3
6ModuleNominalVoltage,VDD
7ModuleOrganization3
8ModuleMemoryBusWidth
9FineTimebase(FTB)Dividend/Divisor
10MediumTimebase(MTB)Dividend
11MediumTimebase(MTB)Divisor
12SDRAMMinimumCycleTime(tCKmin)3
13Reserved
14CASLatenciesSupported,LeastSignificantByte3
15CASLatenciesSupported,MostSignificantByte3
16MinimumCASLatencyTime(tAAmin)3
17MinimumWriteRecoveryTime(tWRmin)3
18MinimumRAS#toCAS#DelayTime(tRCDmin)3
19MinimumRowActivetoRowActiveDelayTime(tRRDmin)3
20MinimumRowPrechargeDelayTime(tRPmin)3
21UpperNibblesfortRASandtRC3
22MinimumActivetoPrechargeDelayTime(tRASmin),LeastSignificantByte3
23MinimumActivetoActive/RefreshDelayTime(tRCmin),LeastSignificantByte3
1.NumberofSPDbyteswrittenwilltypicallybeprogrammedas128or176bytes.
2.SizeofSPDdevicewilltypicallybeprogrammedas256bytes.
3.FromDDR3SDRAMdatasheet.
4.Theseareoptional,inaccordancewiththeJEDECspec.
Release18
JEDECStandardNo.21-C
Page4.1.2.11–2
24MinimumRefreshRecoveryDelayTime(tRFCmin),LeastSignificantByte3
25MinimumRefreshRecoveryDelayTime(tRFCmin),MostSignificantByte3
26MinimumInternalWritetoReadCommandDelayTime(tWTRmin)3
27MinimumInternalReadtoPrechargeCommandDelayTime(tRTPmin)3
28UpperNibblefortFAW3
29MinimumFourActivateWindowDelayTime(tFAWmin)3
30SDRAMOptionalFeatures3
31SDRAMThermalandRefreshOptions3
32ModuleThermalSensor
33SDRAMDeviceType
34~59
Reserved,GeneralSection
60~116ModuleTypeSpecificSection,IndexedbyKeyByte3
117~118
ModuleID:ModuleManufacturer’sJEDECIDCode
119
ModuleID:ModuleManufacturingLocation
120~121
ModuleID:ModuleManufacturingDate
122~125
ModuleID:ModuleSerialNumber
126~127
CyclicalRedundancyCode
128~145
ModulePartNumber4
146~147ModuleRevisionCode
4
148~149DRAMManufacturer’sJEDECIDCode
4
150~175Manufacturer’sSpecificData
4
176~255Openforcustomeruse
ByteNumber
FunctionDescribed
Notes
1.NumberofSPDbyteswrittenwilltypicallybeprogrammedas128or176bytes.
2.SizeofSPDdevicewilltypicallybeprogrammedas256bytes.
3.FromDDR3SDRAMdatasheet.
4.Theseareoptional,inaccordancewiththeJEDECspec.
Release18
JEDECStandardNo.21-C
Page4.1.2.11–3
2.0Detailsofeachbyte
2.1GeneralSection:Bytes0to59
ThissectioncontainsdefinesbytesthatarecommontoallDDR3moduletypes.
Byte0:NumberofBytesUsed/NumberofBytesinSPDDevice/CRCCoverage
TheleastsignificantnibbleofthisbytedescribesthetotalnumberofbytesusedbythemodulemanufacturerfortheSPD
dataandany(optional)specificsupplierinformation.Thebytecountincludesthefieldsforallrequiredandoptionaldata.
Bits6~4describethetotalsizeoftheserialmemoryusedtoholdtheSerialPresenceDetectdata.Bit7indicates
whethertheuniquemoduleidentifier(foundinbytes117~125)iscoveredbytheCRCencodedonbytes126and127.
Byte1:SPDRevision
ThisbytedescribesthecompatibilityleveloftheencodingofthebytescontainedintheSPDEEPROM,andthecurrent
collectionofvaliddefinedbytes.Thisbytemustbecodedas0x10forSPDswithrevisionlevel1.0.Softwareshould
examinetheuppernibble(EncodingLevel)todetermineifitcancorrectlyinterpretthecontentsofthemoduleSPD.The
lowernibble(AdditionsLevel)canoptionallybeusedtodeterminewhichadditionalbytesorattributebitshavebeen
defined;however,sinceanyundefinedadditionalbytemustbeencodedas0x00orundefinedattributebitmustbe
definedas0,softwarecansafelydetectadditionalbytesandusesafedefaultsifazeroencodingisreadforthesebytes.
TheAdditionsLevelisneverreducedevenafteranincrementoftheEncodingLevel.Forexample,ifthecurrentSPD
revisionlevelwere1.2andachangeinEncodingLevelwereapproved,thenextrevisionlevelwouldbe2.2.Ifadditions
torevision2.2wereapproved,thenextrevisionwouldbe2.3.ChangesintheEncodingLevelareextremelyrare,how-
ever,sincetheycancreateincompatibilitieswitholdersystems.
TheexceptionstotheaboverulearetheSPDrevisionlevelsusedduringdevelopmentpriortotheRevision1.0release.
Revisions0.0through0.9areusedtoindicatesequentialpre-productionSPDrevisionlevels,howeverthefirstproduction
releasewillbeRevision1.0.
Bit7Bits6~4Bits3~0
CRCCoverageSPDBytesTotalSPDBytesUsed
0=CRCcoversbytes0~125
1=CRCcoversbytes0~116
Bit[6,5,4]:
000=Undefined
001=256
Allothersreserved
Bit[3,2,1,0]:
0000=Undefined
0001=128
0010=176
0011=256
Allothersreserved
ProductionStatusSPDRevision
EncodingLevelAdditionsLevel
Hex
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
Pre-production
Revison0.0000000000
Revison0.10000000101
..........
Revison0.90000100109
Production
Revison1.00001000010
Revison1.1000100011
...........
UndefinedUndefined11111111F
Release18
JEDECStandardNo.21-C
Page4.1.2.11–4
Byte2:KeyByte/DRAMDeviceType
ThisbyteisthekeybyteusedbythesystemBIOStodeterminehowtointerpretallotherbytesintheSPDEEPROM.The
BIOSmustcheckthisbytefirsttoensurethattheEEPROMdataisinterpretedcorrectly.AnyDRAMorModuletypethat
requiressignificantchangestotheSPDformat(beyonddefiningpreviouslyundefinedbytesorbits)alsorequiresanew
entryinthekeybytetablebelow.
Line#
SDRAM/ModuleType
CorrespondingtoKeyByte
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0Hex
0Resrved000000000
1StandardFPMDRAM0000000101
2EDO0000001002
3PipelinedNible0000001103
4SDRAM0000010004
5ROM0000010105
6DDRSGRAM0000011006
7DDRSDRAM0000011107
8DR2SDRAM0000100008
9DR2SDRAMFB-DIM0000100109
10
DDR2SDRAMFB-DIMM
PROBE
000010100A
1DR3SDRAM000010110B
-----------
253Resrved11111101FD
254Resrved11111110FE
25Resrved11111111F
Release18
JEDECStandardNo.21-C
Page4.1.2.11–5
Byte3:KeyByte/ModuleType
ThisbyteisaKeyByteusedtoindexthemodulespecificsectionoftheSPDfrombytes60~116.Byte3identifiesthe
SDRAMmemorymoduletypewhichimpliesthewidth(Ddimension)ofthemodule.Othermodulephysicalcharacteris-
tics,suchasheight(Adimension)orthickness(Edimension)aredocumentedinthemodulespecificsectionoftheSPD.
RefertotherelevantJEDECJC-11moduleoutline(MO)documentsfordimensiondefinitions.
Byte4:SDRAMDensityandBanks
ThisbytedefinesthetotaldensityoftheDDR3SDRAM,inbits,andthenumberofinternalbanksintowhichthememory
arrayisdivided.ThesevaluescomefromtheDDR3SDRAMdatasheet.
Bits7~4Bits3~0
ReservedModuleType
Bit[3,2,1,0]:
0000=Undefined
0001=RDIMM(width=133.35mmnom)
0010=UDIMM(width=133.35mmnom)
0011=SO-DIMM(width=67.6mmnom)
0100=Micro-DIMM(width=TBDmmnom)
0101=Mini-RDIMM(width=TBDmmnom)
0110=Mini-UDIMM(width=TBDmmnom)
Allothersreserved
Definitions:
RDIMM:RegisteredDualIn-LineMemoryModule
UDIMM:UnbufferedDualIn-LineMemoryModule
SO-DIMM:SmallOutlineDualIn-LineMemoryModule
Micro-DIMM:MicroDualIn-LineMemoryModule
Mini-RDIMM:MiniRegisteredDualIn-LineMemoryModule
Mini-UDIMM:MiniUnbufferedDualIn-LineMemoryModule
Bit7Bits6~4Bits3~0
ReservedBankAddressBitsTotalSDRAMcapacity,inmegabits
Bit[6,5,4]:
000=3(8banks)
001=4(16banks)
010=5(32banks)
011=6(64banks)
Allothersreserved
Bit[3,2,1,0]:
0000=256Mb
0001=512Mb
0010=1Gb
0011=2Gb
0100=4Gb
0101=8Gb
0110=16Gb
Allothersreserved
Release18
JEDECStandardNo.21-C
Page4.1.2.11–6
Byte5:SDRAMAddressing
ThisbytedescribestherowaddressingandthecolumnaddressingintheSDRAMdevice.Bits2~0encodethenumber
ofcolumnaddressbits,andbits5~3encodethenumberofrowaddressbits.ThesevaluescomefromtheDDR3
SDRAMdatasheet.
Byte6:ModuleNominalVoltage,VDD
ThisbytedescribestheVoltageLevelforDRAMandothercomponentsonthemodulesuchastheregisterifapplicable.
NotethatSPDsorthermalsensorcomponentsareontheVDDSPDsupplyandarenotaffectedbythisbyte.
''Operable''isdefinedastheVDDvoltageatwhichmoduleoperationisallowedusingtheperformancevalues
programmedintheSPD.
''Endurant''isdefinedastheVDDvoltageatwhichthemodulemaybepoweredwithoutadverselyaffectingthelife
expectancyorreliability.Furtherspecificationswillexisttodefinetheamountoftimethatthe‘Endurant’voltagecanbe
appliedtothemodule.Operationisnotsupportedatthisvoltage.
Examples:
Avalueonbits2~0of000impliesthatthedevicesupportsnominaloperablevoltageof1.5Vonly.
Avalueonbits2~0of010impliesthatthedevicesupportsnominaloperablevoltagesof1.35Vand1.5V.
Avalueonbits2~0of110impliesthatthedevicesupportsnominaloperablevoltagesof1.2XV,1.35V,or1.5V.
Avalueonbits2~0of111impliesthatthedevicesupportsnominaloperablevoltagesof1.2XVor1.35V.Thedeviceisfurthermore
endurantto1.5V.
Byte7:ModuleOrganization
ThisbytedescribestheorganizationoftheSDRAMmodule.Bits2~0encodethedevicewidthoftheSDRAMdevices.
Bits5~3encodethenumberofphysicalranksonthemodule.Forexample,foradouble-rankmodulewithx8DRAMs,
thisbyteisencoded00001001,or0x09.
Bits7~6Bits5~3Bits2~0
ReservedRowAddressBitsColumnAddressBits
Bit[5,4,3]:
000=12
001=13
010=14
011=15
100=16
Allothersreserved
Bit[2,1,0]:
000=9
001=10
010=11
011=12
Allothersreserved
Byte6:ModuleNominalVoltage,VDD
ReservedModuleMinimumNominalVoltage,VDD
Bit7~3Bit2Bit1Bit0
Reserved
0=NOT1.2XVoperable
1=1.2XVoperable
0=NOT1.35Voperable
1=1.35Voperable
0=1.5Voperable
1=NOT1.5Voperable
Notes:
1.35VLVDDR3devicesarerequiredtobe1.5Voperable.
AllDDR3devicesarerequiredtobe1.5Vendurant.
ThevalueonBit0usesadifferentpolarityascomparedtoBits1and2forbackwardcompatibilitywithprevious
DDR3SPDdefinitions.
Release18
JEDECStandardNo.21-C
Page4.1.2.11–7
Byte8:ModuleMemoryBusWidth
ThisbytedescribesthewidthoftheSDRAMmemorybusonthemodule.Bits2~0encodetheprimarybuswidth.Bits4
~3encodethebusextensionssuchasparityorECC.
Examples:
?64bitprimarybus,noparityorECC(64bitstotalwidth):xxx000011
?64bitprimarybus,with8bitECC(72bitstotalwidth):xxx001011
CalculatingModuleCapacity
ThetotalmemorycapacityofthemodulemaybecalculatedfromSPDvalues.Forexample,tocalculatethetotal
capacity,inmegabytesorgigabytes,ofatypicalmodule:
?SDRAMCAPACITY÷8PRIMARYBUSWIDTH÷SDRAMWIDTHRANKS
where:
?SDRAMCAPACITY=SPDbyte4bits3~0
?PRIMARYBUSWIDTH=SPDbyte8bits2~0
?SDRAMWIDTH=SPDbyte7bits2~0
?RANKS=SPDbyte7bits5~3
Example:2ranksof1GbSDRAMswithx4organizationonamodulewitha64bitprimarybus:
?1Gb÷864÷42=4GB
Example:1rankof2GbSDRAMswithx8organizationonamodulewitha64bitprimarybus:
?2Gb÷864÷81=2GB
Bits7~6Bits5~3Bits2~0
ReservedNumberofRanksSDRAMDeviceWidth
Bit[5,4,3]:
000=1Rank
001=2Ranks
010=3Ranks
011=4Ranks
Allothersreserved
Bit[2,1,0]:
000=4bits
001=8bits
010=16bits
011=32bits
Allothersreserved
Bits7~5Bits4~3Bits2~0
ReservedBuswidthextension,inbitsPrimarybuswidth,inbits
Bit[4,3]:
000=0bits(noextension)
001=8bits
Allothersreserved
Bit[2,1,0]:
000=8bits
001=16bits
010=32bits
011=64bits
Allothersreserved
Release18
JEDECStandardNo.21-C
Page4.1.2.11–8
Commonly,parityorECCarenotcountedintotalmodulecapacity,thoughtheycanalsobeincludedbyaddingthebus
widthextensioninSPDbyte8bits4~3totheprimarybuswidthinthepreviousexamples.
Byte9:FineTimebase(FTB)Dividend/Divisor
Thisbytedefinesavalueinpicosecondsthatrepresentsthefundamentaltimebaseforfinegraintimingcalculations.This
valueisusedasamultiplierforformulatingsubsequenttimingparameters.Thefinetimebase(FTB)isdefinedasthefine
timebasedividend,bits7~4,dividedbythefinetimebasedivisor,bits3~0.
Examples:
Byte10:MediumTimebase(MTB)Dividend
Byte11:MediumTimebase(MTB)Divisor
Thesebytesdefineavalueinnanosecondsthatrepresentsthefundamentaltimebaseformediumgraintimingcalcula-
tions.Thisvalueistypicallythegreatestcommondivisorfortherangeofclockfrequencies(clockperiods)supportedby
aparticularSDRAM.Thisvalueisusedasamultiplierforformulatingsubsequenttimingparameters.Themediumtime-
base(MTB)isdefinedasthemediumtimebasedividend(byte10)dividedbythemediumtimebasedivisor(byte11).
Examples:
TosimplifyBIOSimplementation,DIMMsassociatedwithagivenkeybytevaluemaydifferinMTBvalueonlybyafactor
oftwo.ForDDR3modules,thedefinedMTBvaluesare:
Bits7~4Bits3~0
FineTimebase(FTB)DividendFineTimebase(FTB)Divisor
Valuesdefinedfrom1to15Valuesdefinedfrom1to15
DividendDivisor
Timebase
(ps)
Use
515Whentimegranularityof5psisrequired
522.5Whentimegranularityof2.5psisrequired
Byte10Bits7~0Byte11Bits7~0
MediumTimebase(MTB)DividendMediumTimebase(MTB)Divisor
Valuesdefinedfrom1to255Valuesdefinedfrom1to255
DividendDivisor
Timebase
(ns)
Use
180.125Forclockfrequenciesof400,533,667,and800MHz
DividendDivisor
Timebase
(ns)
Use
180.125MTBValueforDDR3
1160.0625Reservedforfutureuse
Release18
JEDECStandardNo.21-C
Page4.1.2.11–9
Byte12:SDRAMMinimumCycleTime(t
CK
min)
ThisbytedefinestheminimumcycletimefortheSDRAMmodule,inmediumtimebase(MTB)units.Thisnumberapplies
toallapplicablecomponentsonthemodule.ThisbyteappliestoSDRAMandsupportcomponentsaswellastheoverall
capabilityoftheDIMM.ThisvaluecomesfromtheDDR3SDRAMandsupportcomponentdatasheets.
Examples:
Byte13:Reserved
Bits7~0
MinimumSDRAMCycleTime(t
CK
min)
MTBUnits
Valuesdefinedfrom1to255
tCKmin
(MTBunits)
Timebase
(ns)
tCKminResult
(ns)
Use
200.1252.5DDR3with400MHzclock
150.1251.875DDR3with533MHzclock
120.1251.5DDR3with667MHzclock
100.1251.25DDR3with800MHzclock
Release18
JEDECStandardNo.21-C
Page4.1.2.11–10
Byte14:CASLatenciesSupported,LeastSignificantByte
Byte15:CASLatenciesSupported,MostSignificantByte
ThesebytesdefinewhichCASLatency(CL)valuesaresupported.TherangeisfromCL=4throughCL=18withone
bitperpossibleCASLatency.A1inabitpositionmeansthatCLissupported,a0inthatbitpositionmeansitisnotsup-
ported.SinceCL=6isrequiredforallDDR3speedbins,bit2ofSPDbyte14isalways1.Thesevaluescomefromthe
DDR3SDRAMdatasheet.
Example:DDR3-1600K
Byte14=0xD4(=11010100)--lowbyte.
Byte15=0x00(=00000000)--highbyte.
Results:ActualCASLatenciessupported=6,8,10,and11.
Byte16:MinimumCASLatencyTime(t
AA
min)
ThisbytedefinestheminimumCASLatencyinmediumtimebase(MTB)units.Softwarecanusethisinformation,along
withtheCASLatenciessupported(foundinbytes14and15)todeterminetheoptimalcycletimeforaparticularmodule.
ThisvaluecomesfromtheDDR3SDRAMdatasheet.
Examples:
Byte14:CASLatenciesSupported,LowByte
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
CL=11CL=10CL=9CL=8CL=7CL=6CL=5CL=4
0or10or10or10or10or110or10or1
Byte15:CASLatenciesSupported,HighByte
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
ReservedCL=18CL=17CL=16CL=15CL=14CL=13CL=12
00or10or10or10or10or10or10or1
Foreachbitposition,0meansthisCASLatencyisnotsupported,1meansthisCASLatencyissupported.
CASLatenciesx18171615141312110987654
CLMask0000000011010100
Bits7~0
MinimumSDRAMCASLatencyTime(t
AA
min)
MTBUnits
Valuesdefinedfrom1to255
tAAmin
(MTBunits)
Timebase
(ns)
tAAminResult
(ns)
Use
1000.12512.5DDR3-800D
1200.12515DDR3-800E
900.12511.25DDR3-1066E
1050.12513.125DDR3-1066F
1200.12515DDR3-1066G
840.12510.5DDR3-1333F
960.12512DDR3-1333G
1080.12513.5DDR3-1333H
Release18
JEDECStandardNo.21-C
Page4.1.2.11–11
CASLatencyCalculationandExamples
CASlatencyisnotapurelyanalogvalueasDDR3SDRAMsusetheDLLtosynchronizedataandstrobeoutputswiththe
clock.Allpossiblefrequenciesmaynotbetested,thereforeanapplicationshouldusethenextsmallerJEDECstandard
tCKminvalue(2.5,1.875,1.5,or1.25nsforDDR3SDRAMs)whencalculatingCASLatency.Thissectionshowshow
theBIOSmaycalculateCASlatencybasedonBytes12~16.
Step1:DeterminethecommonsetofsupportedCASLatencyvaluesforallmodulesonthememorychannelusingthe
CASLatenciesSupportedinSPDbytes14and15.
Step2:DeterminetAAmin(all)whichisthelargesttAAminvalueforallmodulesonthememorychannel(SPDbyte16).
Step3:DeterminetCKmin(all)whichisthelargesttCKminvalueforallmodulesonthememorychannel(SPDbyte12).
Step4:ForaproposedtCKvalue(tCKproposed)betweentCKmin(all)andtCKmax,determinethedesiredCASLatency.
IftCKproposedisnotastandardJEDECvalue(2.5,1.875,1.5,or1.25ns)thentCKproposedmustbeadjustedtothe
nextlowerstandardtCKvalueforcalculatingCLdesired.
CLdesired=ceiling(tAAmin(all)/tCKproposed)
wheretAAminisdefinedinByte16.Theceilingfunctionrequiresthatthequotientberoundedupalways.
Step5:ChoseanactualCASLatency(CLactual)thatisgreaterthanorequaltoCLdesiredandissupportedbyallmod-
ulesonthememorychannelasdeterminedinstep1.Ifnosuchvalueexists,chooseahighertCKproposedvalueand
repeatsteps4and5untilasolutionisfound.
1200.12515DDR3-1333J
800.12510DDR3-1600G
900.12511.25DDR3-1600H
1000.12512.5DDR3-1600J
1100.12513.75DDR3-1600K
tAAmin
(MTBunits)
Timebase
(ns)
tAAminResult
(ns)
Use
Release18
JEDECStandardNo.21-C
Page4.1.2.11–12
Step6:OncethecalculationofCLactualiscompleted,theBIOSmustalsoverifythatthisCASLatencyvaluedoesnot
exceedtAAmax,whichis20nsforallDDR3speedgrades,bymultiplyingCLactualtimestCKproposed.Ifnot,choosea
lowerCLvalueandrepeatsteps5and6untilasolutionisfound.
Example1:Slot0=DDR3-1066E6-6-6,Slot1=DDR3-1333H9-9-9
Step1:CLinslot0=5,6,7,8;CLinslot1=6,8,9;CommonCL=6,8
Step2:tAAmininslot0=11.25ns;tAAmininslot1=13.5ns;tAAmin(all)=13.5ns
Step3:tCKmininslot0=1.875ns;tCKmininslot1=1.5ns;tCKproposed=1.875ns
Step4:CLdesired=ceiling(13.5/1.875)=8
Step5:CLactual=CLdesired
Step6:CLactualtCKproposed=81.875=15<20ns...valueisokay
Results:tCKactual=1.875ns,CLactual=8
Example2:Slot0=DDR3-800D5-5-5,Slot1=DDR3-1066G8-8-8
Step1:CLinslot0=5,6;CLinslot1=6,8;CommonCL=6
Step2:tAAmininslot0=12.5ns;tAAmininslot1=15ns;tAAmin(all)=15ns
Step3:tCKmininslot0=2.5ns;tAAmininslot1=1.875ns;tCKproposed=2.5ns
Step4:CLdesired=ceiling(15/2.5ns)=6
Step5:CLactual=CLdesired
Step6:CLactualtCKproposed=62.5=15<20ns...valueisokay
Results:tCKactual=2.5ns,CLactual=6
Example3:Slot0=DDR3-800D5-5-5,Slot1=DDR3-1066G8-8-8,SystemBringup&Debuglimitsoperatingfrequencyto333
MHz(tCK=3.3ns)
Step1:CLinslot0=5,6;CLinslot1=6,8;CommonCL=6
Step2:tAAmininslot0=12.5ns;tAAmininslot1=15ns;tAAmin(all)=15ns
Step3:tCKproposed=3.3ns
Step4:CLdesired=ceiling(15/3.3ns)=5
Step5:CLactual=6
Step6:CLactualtCKproposed=63.3=19.8<20ns...valueisokay
Results:tCKactual=3.3ns,CLactual=6
Byte17:MinimumWriteRecoveryTime(t
WR
min)
ThisbytedefinestheminimumSDRAMwriterecoverytimeinmediumtimebase(MTB)units.Thisvaluecomesfromthe
DDR3SDRAMdatasheet.
Example:
Step1:TheBIOSfirstdeterminesthecommonoperatingfrequencyofallmodulesinthesystem,ensuringthatthe
correspondingvalueoftCK(tCKactual)fallsbetweentCKmin(Byte12)andtCKmax.IftCKactualisnotaJEDEC
standardvalue,thenextsmallerstandardtCKminvalueisusedforcalculatingWriteRecovery.
Step2:TheBIOSthencalculatesthe“desired”WriteRecovery(WRdesired):
WRdesired=ceiling(tWRmin/tCKactual)
Bits7~0
MinimumWriteRecoveryTime(t
WR
)
MTBUnits
Valuesdefinedfrom1to255
tWRmin
(MTBunits)
Timebase
(ns)
tWRResult
(ns)
Use
1200.12515AllDDR3speedgrades
Release18
JEDECStandardNo.21-C
Page4.1.2.11–13
wheretWRminisdefinedinByte17.Theceilingfunctionrequiresthatthequotientberoundedupalways.
Step3:TheBIOSthendeterminesthe“actual”WriteRecovery(WRactual):
WRactual=max(WRdesired,minWRsupported)
whereminWRisthelowestWriteRecoverysupportedbytheDDR3SDRAM.NotethatnotallWRvaluessupportedby
DDR3SDRAMsaresequential,sothenexthighersupportedWRvaluemustbeusedinsomecases.
UsageexampleforDDR3-1333GoperatingatDDR3-1333:
tCKactual=1.5ns
WRdesired=15/1.5=10
WRactual=max(10,10)=10
Byte18:MinimumRAS#toCAS#DelayTime(t
RCD
min)
ThisbytedefinestheminimumSDRAMRAS#toCAS#Delayinmediumtimebase(MTB)units.Thisvaluecomesfrom
theDDR3SDRAMdatasheet.
Examples:
Byte19:MinimumRowActivetoRowActiveDelayTime(t
RRD
min)
ThisbytedefinestheminimumSDRAMRowActivetoRowActiveDelayTimeinmediumtimebaseunits.Thisvalue
comesfromtheDDR3SDRAMdatasheet.ThevalueofthisnumbermaybedependentontheSDRAMpagesize;
pleaserefertotheDDR3SDRAMdatasheetsectiononAddressingtodeterminethepagesizeforthesedevices.Con-
trollerdesignersmustalsonotethatatsomefrequencies,aminimumnumberofclocksmayberequiredresultingina
largertRRDminvaluethanindicatedintheSPD.Forexample,tRRDminforDDR3-800mustbe4clocks.
Bits7~0
MinimumRAS#toCAS#Delay(t
RCD
)
MTBUnits
Valuesdefinedfrom1to255
tRCD
(MTBunits)
Timebase
(ns)
tRCDResult
(ns)
Use
1000.12512.5DDR3-800D
1200.12515DDR3-800E
900.12511.25DDR3-1066E
1050.12513.125DDR3-1066F
1200.12515DDR3-1066G
840.12510.5DDR3-1333F
960.12512DDR3-1333G
1080.12513.5DDR3-1333H
1200.12515DDR3-1333J
800.12510DDR3-1600G
900.12511.25DDR3-1600H
1000.12512.5DDR3-1600J
1100.12513.75DDR3-1600K
Release18
JEDECStandardNo.21-C
Page4.1.2.11–14
Examples:
Byte20:MinimumRowPrechargeDelayTime(t
RP
min)
ThisbytedefinestheminimumSDRAMRowPrechargeDelayTimeinmediumtimebase(MTB)units.Thisvaluecomes
fromtheDDR3SDRAMdatasheet.
Examples:
Byte21:UpperNibblesfort
RAS
andt
RC
ThisbytedefinesthemostsignificantnibblesforthevaluesoftRAS(byte22)andtRC(byte23).Thesevaluescome
fromtheDDR3SDRAMdatasheet.
Bits7~0
MinimumRowActivetoRowActiveDelay(t
RRD
)
MTBUnits
Valuesdefinedfrom1to255
tRRD
(MTBunits)
Timebase
(ns)
tRRDResult
(ns)
Use
480.1256.0Example:DDR3-1333,1KBpagesize
600.1257.5Example:DDR3-1333,2KBpagesize
800.12510Example:DDR3-800,1KBpagesize
Note:tRRDisatleast4nCKindependentofoperatingfrequency.
Bits7~0
MinimumRowPrechargeTime(t
RP
)
MTBUnits
Valuesdefinedfrom1to255
tRP
(MTBunits)
Timebase
(ns)
tRPResult
(ns)
Use
1000.12512.5DDR3-800D
1200.12515DDR3-800E
900.12511.25DDR3-1066E
1050.12513.125DDR3-1066F
1200.12515DDR3-1066G
840.12510.5DDR3-1333F
960.12512DDR3-1333G
1080.12513.5DDR3-1333H
1200.12515DDR3-1333J
800.12510DDR3-1600G
900.12511.25DDR3-1600H
1000.12512.5DDR3-1600J
1100.12513.75DDR3-1600K
Bits7~4Bits3~0
t
RC
MostSignificantNibblet
RAS
MostSignificantNibble
SeeByte23descriptionSeeByte22description
Release18
JEDECStandardNo.21-C
Page4.1.2.11–15
Byte22:MinimumActivetoPrechargeDelayTime(t
RAS
min),LeastSignificantByte
ThelowernibbleofByte21andthecontentsofByte22combinedcreatea12-bitvaluewhichdefinestheminimum
SDRAMActivetoPrechargeDelayTimeinmediumtimebase(MTB)units.ThemostsignificantbitisBit3ofByte21,
andtheleastsignificantbitisBit0ofByte22.ThisvaluecomesfromtheDDR3SDRAMdatasheet.
Examples:
Byte23:MinimumActivetoActive/RefreshDelayTime(t
RC
min),LeastSignificantByte
TheuppernibbleofByte21andthecontentsofByte23combinedcreatea12-bitvaluewhichdefinestheminimum
SDRAMActivetoActive/RefreshDelayTimeinmediumtimebase(MTB)units.ThemostsignificantbitisBit7ofByte
21,andtheleastsignificantbitisBit0ofByte23.ThisvaluecomesfromtheDDR3SDRAMdatasheet.
Examples:
Byte21Bits3~0,Byte22Bits7~0
MinimumActivetoPrechargeTime(t
RAS
)
MTBUnits
Valuesdefinedfrom1to4095
tRAS
(MTBunits)
Timebase
(ns)
tRASResult
(ns)
Use
3000.12537.5DDR3-800D
3000.12537.5DDR3-800E
3000.12537.5DDR3-1066E
3000.12537.5DDR3-1066F
3000.12537.5DDR3-1066G
2880.12536DDR3-1333F
2880.12536DDR3-1333G
2880.12536DDR3-1333H
2880.12536DDR3-1333J
2800.12535DDR3-1600G
2800.12535DDR3-1600H
2800.12535DDR3-1600J
2800.12535DDR3-1600K
Byte21Bits7~4,Byte23Bits7~0
MinimumActivetoActive/RefreshTime(t
RC
)
MTBUnits
Valuesdefinedfrom1to4095
tRC
(MTBunits)
Timebase
(ns)
tRCResult
(ns)
Use
4000.12550DDR3-800D
4200.12552.5DDR3-800E
3900.12548.75DDR3-1066E
4050.12550.625DDR3-1066F
4200.12552.5DDR3-1066G
3720.12546.5DDR3-1333F
3840.12548DDR3-1333G
3960.12549.5DDR3-1333H
4080.12551DDR3-1333J
3600.12545DDR3-1600G
Release18
JEDECStandardNo.21-C
Page4.1.2.11–16
Byte24:MinimumRefreshRecoveryDelayTime(t
RFC
min),LeastSignificantByte
Byte25:MinimumRefreshRecoveryDelayTime(t
RFC
min),MostSignificantByte
ThecontentsofByte24andthecontentsofByte25combinedcreatea16-bitvaluewhichdefinestheminimumSDRAM
RefreshRecoveryTimeDelayinmediumtimebase(MTB)units.ThemostsignificantbitisBit7ofByte25,andtheleast
significantbitisBit0ofByte24.ThesevaluescomefromtheDDR3SDRAMdatasheet.
Examples:
Byte26:MinimumInternalWritetoReadCommandDelayTime(t
WTR
min)
ThisbytedefinestheminimumSDRAMInternalWritetoReadDelayTimeinmediumtimebase(MTB)units.Thisvalue
comesfromtheDDR3SDRAMdatasheet.ThevalueofthisnumbermaybedependentontheSDRAMpagesize;
pleaserefertotheDDR3SDRAMdatasheetsectiononAddressingtodeterminethepagesizeforthesedevices.Con-
trollerdesignersmustalsonotethatatsomefrequencies,aminimumnumberofclocksmayberequiredresultingina
largertWTRminvaluethanindicatedintheSPD.Forexample,tWTRminforDDR3-800mustbe4clocks.
Examples:
Byte27:MinimumInternalReadtoPrechargeCommandDelayTime(t
RTP
min)
ThisbytedefinestheminimumSDRAMInternalReadtoPrechargeDelayTimeinmediumtimebase(MTB)units.This
valuecomesfromtheDDR3SDRAMdatasheet.ThevalueofthisnumbermaybedependentontheSDRAMpagesize;
pleaserefertotheDDR3SDRAMdatasheetsectiononAddressingtodeterminethepagesizeforthesedevices.Con-
trollerdesignersmustalsonotethatatsomefrequencies,aminimumnumberofclocksmayberequiredresultingina
3700.12546.25DDR3-1600H
3800.12547.5DDR3-1600J
3900.12548.75DDR3-1600K
Byte25Bits7~0,Byte24Bits7~0
MinimumRefreshRecoverTimeDelay(t
RFC
)
MTBUnits
Valuesdefinedfrom1to65535
tRFC
(MTBunits)
Timebase
(ns)
tRFCResult
(ns)
Use
7200.12590512Mb
8800.1251101Gb
12800.1251602Gb
Bits7~0
InternalWritetoReadDelayTime(t
WTR
)
MTBUnits
Valuesdefinedfrom1to255
tWTR
(MTBunits)
Timebase
(ns)
tWTRResult
(ns)
Use
600.1257.5AllDDR3SDRAMspeedbins
Note:tWTRisatleast4nCKindependentofoperatingfrequency.
tRC
(MTBunits)
Timebase
(ns)
tRCResult
(ns)
Use
Release18
JEDECStandardNo.21-C
Page4.1.2.11–17
largertRTPminvaluethanindicatedintheSPD.Forexample,tRTPminforDDR3-800mustbe4clocks.
Examples:
Bits7~0
InternalReadtoPrechargeDelayTime(t
RTP
)
MTBUnits
Valuesdefinedfrom1to255
tRTP
(MTBunits)
Timebase
(ns)
tRTPResult
(ns)
Use
600.1257.5AllDDR3SDRAMspeedbins
Note:tRTPisatleast4nCKindependentofoperatingfrequency.
Release18
JEDECStandardNo.21-C
Page4.1.2.11–18
Byte28:UpperNibblefort
FAW
ThisbytedefinesthemostsignificantnibbleforthevalueoftFAW(SPDbyte29).ThisvaluecomesfromtheDDR3
SDRAMdatasheet.
Byte29:MinimumFourActivateWindowDelayTime(t
FAW
min),LeastSignificantByte
ThelowernibbleofByte28andthecontentsofByte29combinedcreatea12-bitvaluewhichdefinestheminimum
SDRAMFourActivateWindowDelayTimeinmediumtimebase(MTB)units.ThisvaluecomesfromtheDDR3SDRAM
datasheet.ThevalueofthisnumbermaybedependentontheSDRAMpagesize;pleaserefertotheDDR3SDRAM
datasheetsectiononAddressingtodeterminethepagesizeforthesedevices.
Examples:
Byte30:SDRAMOptionalFeatures
ThisbytedefinessupportforcertainSDRAMfeaturesandtheoptionaldrivestrengthssupportedbytheSDRAMsonthis
module.ThisvaluecomesfromtheDDR3SDRAMdatasheet.
Byte31:SDRAMThermalandRefreshOptions
Thisbytedescribesthemodule’ssupportedoperatingtemperaturerangesandrefreshoptions.Thesevaluescomefrom
theDDR3SDRAMdatasheet.UseofselfrefreshintheExtendedTemperatureRange,ASRorODTSrequire
appropriateSDRAMModeRegisterprogramming(MR2bitsA6,A7,andMR3bitA3).PleaserefertotheDDR3SDRAM
datasheet(JESD79-3orsupplierdatasheet)foracompletedescriptionoftheseoptions.
Bits7~4Bits3~0
Reservedt
FAW
MostSignificantNibble
ReservedSeeByte29description
Byte28Bits3~0,Byte29Bits7~0
MinimumFourActivateWindowDelayTime(t
FAW
)
MTBUnits
Valuesdefinedfrom1to4095
tFAW
(MTBunits)
Timebase
(ns)
tFAWResult
(ns)
Use
3200.12540.0Example:DDR3-800,1KBpagesize
4000.12550.0Example:DDR3-800,2KBpagesize
3000.12537.5Example:DDR3-1066,1KBpagesize
4000.12550.0Example:DDR3-1066,2KBpagesize
2400.12530.0Example:DDR3-1333,1KBpagesize
3600.12545.0Example:DDR3-1333,2KBpagesize
2400.12530.0Example:DDR3-1600,1KBpagesize
3200.12540.0Example:DDR3-1600,2KBpagesize
Bit7Bits6~2Bit1Bit0
DLL-OffModeSupportReservedRZQ/7RZQ/6
0=NotSupported
1=Supported
0=NotSupported
1=Supported
0=NotSupported
1=Supported
Release18
JEDECStandardNo.21-C
Page4.1.2.11–19
Examples:
IfSPDByte31bit0=0,theSDRAMdoesnotsupportextendedtemperaturerangeuseandtheSDRAMMR2bitA7
mustbesetto0.1Xrefreshrateacrossthenormaltemperaturerangeof0-85°Cissupported.
IfSPDByte31bit0=1,thentheextendedtemperaturerangefrom85-95°CissupportedandtheSDRAMMR2bitA7
maybesetto1.SPDbyte31bit1maybeusedtodetermineanappropriaterefreshratewhenoperatingintheextended
temperaturerange.
IfSPDByte31bit2=0,thentheSDRAMMR2bitA6mustbesetto0.SDRAMMR2bitA7mustbeprogrammedtoindi-
catethetemperaturerange(TOPER)forsubsequentselfrefreshoperation.
IfSPDByte31bit3=1,theon-diethermalsenselogiccanbeusedinconjunctionwithSPDByte31bits0and1todeter-
mineanappropriaterefreshrateand/ormonitorthemaximumoperatingtemperature.
Byte32:ModuleThermalSensor
Thisbytedescribesthemodule’ssupportedthermaloptions.
Byte33:SDRAMDeviceType
ThisbytedescribesthetypeofSDRAMDeviceonthemodule.
Bit7Bits6~4Bit3Bit2Bit1Bit0
PartialArraySelf
Refresh(PASR)
Reserved
On-dieThermal
Sensor(ODTS)
Readout
AutoSelfRefresh
(ASR)
ExtendedTempera-
tureRefreshRate
ExtendedTem-
peratureRange
1=Supported
0=Notsupported
1=On-diethermal
sensorreadoutis
supported
0=On-diethermal
sensorreadoutisnot
supported
(pendingballotof
ODTS)
1=ASRissupported
andtheSDRAMwill
determinetheproper
refreshrateforany
supported
temperature
0=ASRisnot
supported
1=Extendedoperating
temperaturerange
from85-95°C
supportedwith
standard1Xrefresh
rate
0=Useinextended
operatingtemperature
rangefrom85-95°C
requires2Xrefresh
rate
1=Normaland
extendedoperating
temperaturerange
0-95°Csupported
0=Normal
operating
temperaturerange
0-85°Csupported
Bit7Bits6~0
ThermalSensor
1
ThermalSensorAccuracy
0=Thermalsensornotincorporatedontothisassembly
1=Thermalsensorincorporatedontothisassembly
0=Undefined
Allotherssettingstobedefined.
Note1:ThermalsensorcompliantwithTSE2002specifications.
Bit7Bits6~0
SDRAMDeviceTypeNon-StandardDeviceDescription
0=StandardMonolithicDRAMDevice
1=Non-StandardDevice
1
0=Undefined
Allotherssettingstobedefined.
Note1-ThisincludesDualDie,QuadDie,Multi-DieandPhysicalstackeddevices-anythingthatisoutsidethestandard
monolithicdevice.
Release18
JEDECStandardNo.21-C
Page4.1.2.11–20
Byte34~59:Reserved,GeneralSection
Release18
JEDECStandardNo.21-C
Page4.1.2.11–21
2.2Module-SpecificSection:Bytes60~116
ThissectioncontainsSPDbyteswhicharespecifictofamiliesDDR3modulefamilies.ModuleTypeKeyByte3isused
asanindexfortheencodingofbytes60~116.Thecontentofbytes60~116aredescribedinmultipleappendices,one
foreachmemorymodulefamily.
2.3UniqueModuleID:Bytes117~125
Byte117:ModuleManufacturerIDCode,LeastSignificantByte
Byte118:ModuleManufacturerIDCode,MostSignificantByte
Thistwo-bytefieldindicatesthemanufacturerofthemodule,encodedasfollows:thefirstbyteisthenumberof
continuationbytesindicatedinJEP-106;thesecondbyteisthelastnon-zerobyteofthemanufacturer’sIDcode,againas
indicatedinJEP-106.
Byte119:ModuleManufacturingLocation
Themodulemanufacturerincludesanidentifierthatuniquelydefinesthemanufacturinglocationofthememorymodule.
WhiletheSPDspecwillnotattempttopresentadecodetableformanufacturingsites,theindividualmanufacturermay
keeptrackofmanufacturinglocationanditsappropriatedecoderepresentedinthisbyte.
Bytes120~121:ModuleManufacturingDate
Themodulemanufacturerincludesadatecodeforthemodule.TheJEDECdefinitionsforbytes120and121areyear
andweekrespectively.ThesebytesmustberepresentedinBinaryCodedDecimal(BCD).Forexample,week47inyear
2003wouldbecodedas0x03(00000011)inbyte120and0x47(01000111)inbyte121.
Bytes122~125:ModuleSerialNumber
Thesuppliermustincludeauniqueserialnumberforthemodule.Thesuppliermayusewhateverdecodemethoddesired
tomaintainauniqueserialnumberforeachmodule.
Onemethodofachievingthisisbyassigningabyteinthefieldfrom122~125asatesterIDbyteandusingtheremain-
ingbytesasasequentialserialnumber.Bytes117~125willthenresultinanine-byteuniquemoduleidentifier.Notethat
partnumberisnotincludedinthisidentifier:thesuppliermaynotgivethesamevalueforBytes119~125tomorethan
oneDIMMeveniftheDIMMshavedifferentpartnumbers.
Byte118,Bits7~0Byte117,Bit7Byte117,Bits6~0
Lastnon-zerobyte,
ModuleManufacturer
ParityforByte117,bits6~0
Numberofcontinuationcodes,
ModuleManufacturer
SeeJEP-106SeeJEP-106
Release18
JEDECStandardNo.21-C
Page4.1.2.11–22
2.4CRC:Bytes126~127
Bytes126~127:SPDCyclicalRedundancyCode(CRC)
Thistwo-bytefieldcontainsthecalculatedCRCforpreviousbytesintheSPD.Thefollowingalgorithmanddata
structures(showninC)aretobefollowedincalculatingandcheckingthecode.Bit7ofByte0indicateswhichbytesare
coveredbytheCRC.
intCrc16(charptr,intcount)
{
intcrc,i;
crc=0;
while(--count>=0){
crc=crc^(int)ptr++<<8;
for(i=0;i<8;++i)
if(crc&0x8000)
crc=crc<<1^0x1021;
else
crc=crc<<1;
}
return(crc&0xFFFF);
}
charspdBytes[]={SPD_byte_0,SPD_byte_1,...,SPD_byte_N-1};
intdata16;
data16=Crc16(spdBytes,sizeof(spdBytes));
SPD_byte_126=(char)(data16&0xFF);
SPD_byte_127=(char)(data16>>8);
Release18
JEDECStandardNo.21-C
Page4.1.2.11–23
2.5OtherManufacturerFieldsandUserSpace:Bytes128~255
Bytes128~145:ModulePartNumber
Themanufacturer’spartnumberiswritteninASCIIformatwithinthesebytes.UnuseddigitsarecodedasASCIIblanks
(0x20).
Bytes146~147:ModuleRevisionCode
Thisreferstothemodulerevisioncode.WhiletheSPDspecwillnotattempttodefinetheformatforthisinformation,the
individualmanufacturermaykeeptrackoftherevisioncodeanditsappropriatedecoderepresentedinthisbyte.
Byte148:DRAMManufacturerIDCode,LeastSignificantByte
Byte149:DRAMManufacturerIDCode,MostSignificantByte
Thistwo-bytefieldindicatesthemanufactureroftheDRAMonthemodule,encodedasfollows:thefirstbyteisthe
numberofcontinuationbytesindicatedinJEP-106;thesecondbyteisthelastnon-zerobyteofthemanufacturer’sID
code,againasindicatedinJEP-106.
Bytes150~175:Manufacturer’sSpecificData
Themodulemanufacturermayincludeanyadditionalinformationdesiredintothemodulewithintheselocations.
Bytes176~255:OpenforCustomerUse
Thesebytesareunusedbythemanufacturerandareopenforcustomeruse.
Byte149,Bits7~0Byte148,Bit7Byte148,Bits6~0
Lastnon-zerobyte,
DRAMManufacturer
ParityforByte148,bits6~0
Numberofcontinuationcodes,
DRAMManufacturer
SeeJEP-106SeeJEP-106
Release18
JEDECStandardNo.21-C
Page4.1.2.11–24
ASCIIDecodeMatrixforSPDs
ThefollowingtableisasubsetofthefullASCIIstandardwhichisusedforcodingbytesintheSerialPresenceDetect
EEPROMthatrequireASCIIcharacters:
Examples:
0x20=BlankSpace
0x34=‘4’
0x41=‘A’
SecondHexDigitinPair
FirstHex
DigitinPair
0123456789ABCDEF
2
Blank
Space
()
-
Dash
.
Period
30123456789
4ABCDEFGHIJKLMNO
5PQRSTUVWXYZ
6abcdefghijklmno
7pqrstuvwxyz
SPDBytes128~145
Manufacturer’sPNCodedinASCII
13M32734BCD-260Y31334D33323733344243442D323630592020
Release18
JEDECStandardNo.21-C
Page4.1.2.11–25
AppendixX.1:ModuleSpecificBytesforUnbufferedMemoryModuleTypes
(Bytes60~116)
ThissectiondefinestheencodingofSPDbytes60~116whenMemoryTechnologyKeyByte2containsthe
value0x0BandModuleTypeKeyByte3containsanyofthefollowing:
?0x02,UDIMM
?0x03,SO-DIMM
?0x04,Micro-DIMM
?0x06,Mini-UDIMM
ThefollowingistheSPDaddressmapforthemodulespecificsection,bytes60~116,oftheSPDfor
UnbufferedModuleTypes.
Byte60(Unbuffered):ModuleNominalHeight
Thisbytedefinesthenominalheight(Adimension)inmillimetersofthefullyassembledmoduleincludingheatspreaders
orotheraddedcomponents.RefertotherelevantJEDECJC-11moduleoutline(MO)documentsfordimensiondefini-
tions.
Byte61(Unbuffered):ModuleMaximumThickness
Thisbytedefinesthemaximumthickness(Edimension)inmillimetersofthefullyassembledmoduleincludingheat
spreadersorotheraddedcomponentsabovethemodulecircuitboardsurface.Thicknessofthefrontofthemoduleis
calculatedastheE1dimensionminusthePCBthickness.ThicknessofthebackofthemoduleiscalculatedastheE
ModuleSpecificSPDBytesforUnbufferedModuleTypes
ByteNumber
FunctionDescribed
Notes
60ModuleNominalHeight
61ModuleMaximumThickness
62ReferenceRawCardUsed
63AddressMappingfromEdgeConnectortoDRAM
64~116Reserved
Bits7~5Bits4~0
Reserved
ModuleNominalHeightmax,inmm
(baselineheight=15mm)
Reserved00000=height≤15mm
00001=15
00010=16
00011=17
00100=18
...
01010=24
01011=25
...
01111=29
10000=30
...
11111=45mm
Release18
JEDECStandardNo.21-C
Page4.1.2.11–26
dimensionminustheE1dimension.RefertotherelevantJEDECJC-11moduleoutline(MO)documentsfordimension
definitions.
Bits7~4Bits3~0
ModuleMaximumThicknessmax,Back,inmm
(baselinethickness=1mm)
ModuleMaximumThicknessmax,Front,inmm
(baselinethickness=1mm)
0000=thickness≤1mm
0001=1
0010=2
0011=3
...
1110=14
1111=15
0000=thickness≤1mm
0001=1
0010=2
0011=3
...
1110=14
1111=15
Note:Thickness=E-E1Note:Thickness=E1-PCB
Release18
JEDECStandardNo.21-C
Page4.1.2.11–27
Byte62(Unbuffered):ReferenceRawCardUsed
ThisbyteindicateswhichJEDECreferencedesignrawcardwasusedasthebasisforthemoduleassembly,ifany.Bits
4~0describetherawcardandbits6~5describetherevisionlevelofthatrawcard.Specialreferencerawcardindica-
tor,ZZ,isusedwhennoJEDECstandardrawcardreferencedesignwasusedasthebasisforthemoduledesign.Pre-
productionmodulesshouldbeencodedasrevision0inbits6~5.
Bit7Bits6~5Bits4~0
ReferenceRawCardExtensionReferenceRawCardRevisionReferenceRawCard
0=ReferencerawcardsAthroughAL00=revision0
01=revision1
10=revision2
11=revision3
Whenbit7=0,
00000=ReferencerawcardA
00001=ReferencerawcardB
00010=ReferencerawcardC
00011=ReferencerawcardD
00100=ReferencerawcardE
00101=ReferencerawcardF
00110=ReferencerawcardG
00111=ReferencerawcardH
01000=ReferencerawcardJ
01001=ReferencerawcardK
01010=ReferencerawcardL
01011=ReferencerawcardM
01100=ReferencerawcardN
01101=ReferencerawcardP
01110=ReferencerawcardR
01111=ReferencerawcardT
10000=ReferencerawcardU
10001=ReferencerawcardV
10010=ReferencerawcardW
10011=ReferencerawcardY
10100=ReferencerawcardAA
10101=ReferencerawcardAB
10110=ReferencerawcardAC
10111=ReferencerawcardAD
11000=ReferencerawcardAE
11001=ReferencerawcardAF
11010=ReferencerawcardAG
11011=ReferencerawcardAH
11100=ReferencerawcardAJ
11101=ReferencerawcardAK
11110=ReferencerawcardAL
11111=ZZ(noJEDECreferenceraw
carddesignused)
Release18
JEDECStandardNo.21-C
Page4.1.2.11–28
Byte63:AddressMappingfromEdgeConnectortoDRAM
ThisbytedescribestheconnectionofedgeconnectorpinsforaddressbitstothecorrespondinginputpinsoftheDDR3
SDRAMsforrank1only;rank0isalwaysassumedtousestandardmapping.Onlytwoconnectiontypesaresupported,
standardormirrored,asdescribedinthemappingtablebelow.Systemsoftwaremustcompensateforthismapping
whenissuingmoderegistersetcommandstotheranksofDDR3SDRAMsonthismodule.
Thedefinitionofstandardandmirroredaddressconnectionmappingisdetailedbelow;highlightedrowsinthetableindi-
catewhichsignalschangebetweenmappings.
Bit7Bits6~5Bits4~0
ReferenceRawCardExtensionReferenceRawCardRevisionReferenceRawCard
1=ReferencerawcardsAMthroughCB00=revision0
01=revision1
10=revision2
11=revision3
Whenbit7=1,
00000=ReferencerawcardAM
00001=ReferencerawcardAN
00010=ReferencerawcardAP
00011=ReferencerawcardAR
00100=ReferencerawcardAT
00101=ReferencerawcardAU
00110=ReferencerawcardAV
00111=ReferencerawcardAW
01000=ReferencerawcardAY
01001=ReferencerawcardBA
01010=ReferencerawcardBB
01011=ReferencerawcardBC
01100=ReferencerawcardBD
01101=ReferencerawcardBE
01110=ReferencerawcardBF
01111=ReferencerawcardBG
10000=ReferencerawcardBH
10001=ReferencerawcardBJ
10010=ReferencerawcardBK
10011=ReferencerawcardBL
10100=ReferencerawcardBM
10101=ReferencerawcardBN
10110=ReferencerawcardBP
10111=ReferencerawcardBR
11000=ReferencerawcardBT
11001=ReferencerawcardBU
11010=ReferencerawcardBV
11011=ReferencerawcardBW
11100=ReferencerawcardBY
11101=ReferencerawcardCA
11110=ReferencerawcardCB
11111=ZZ(noJEDECreferenceraw
carddesignused)
Bits7~1Bit0
ReservedRank1Mapping
Reserved
0=standard
1=mirrored
EdgeConnector
Signal
DRAMPin,
Standard
DRAMPin,
Mirrored
A0A0A0
A1A1A1
A2A2A2
Release18
JEDECStandardNo.21-C
Page4.1.2.11–29
Bytes64~116(Unbuffered):Reserved
A3A3A4
A4A4A3
A5A5A6
A6A6A5
A7A7A8
A8A8A7
A9A9A9
A10/APA10/APA10/AP
A11A11A11
A12/BCA12/BCA12/BC
A13A13A13
A14A14A14
A15/BA3A15/BA3A15/BA3
BA0BA0BA1
BA1BA1BA0
BA2BA2BA2
EdgeConnector
Signal
DRAMPin,
Standard
DRAMPin,
Mirrored
Release18
JEDECStandardNo.21-C
Page4.1.2.11–30
AppendixX.2:ModuleSpecificBytesforRegisteredMemoryModuleTypes
(Bytes60~116)
ThissectiondefinestheencodingofSPDbytes60~116whenMemoryTechnologyKeyByte2containsthe
value0x0BandModuleTypeKeyByte3containsanyofthefollowing:
?0x01,RDIMM
?0x05,Mini-RDIMM
ThefollowingistheSPDaddressmapforthemodulespecificsection,bytes60~116,oftheSPDfor
RegisteredModuleTypes.
ModuleSpecificSPDBytesforRegisteredModuleTypes
ByteNumber
FunctionDescribed
Notes
60ModuleNominalHeight
61ModuleMaximumThickness
62ReferenceRawCardUsed
63DIMMModuleAttributes
64RDIMMThermalHeatSpreaderSolution
65RegisterManufacturerIDCode,LeastSignificantByte
66RegisterManufacturerIDCode,MostSignificantByte
67RegisterRevisionNumber
68RegisterType
69RC1(MSNibble)/RC0(LSNibble)
70RC3(MSNibble)/RC2(LSNibble)-DriveStrength,Command/Address
71RC5(MSNibble)/RC4(LSNibble)-DriveStrength,ControlandClock
72RC7(MSNibble)/RC6(LSNibble)
73RC9(MSNibble)/RC8(LSNibble)
74RC11(MSNibble)/RC10(LSNibble)
75RC13(MSNibble)/RC12(LSNibble)
76RC15(MSNibble)/RC14(LSNibble)
77~116Reserved
Release18
JEDECStandardNo.21-C
Page4.1.2.11–31
Byte60(Registered):ModuleNominalHeight
Thisbytedefinesthenominalheight(Adimension)inmillimetersofthefullyassembledmoduleincludingheatspreaders
orotheraddedcomponents.RefertotherelevantJEDECJC-11moduleoutline(MO)documentsfordimensiondefini-
tions.
Byte61(Registered):ModuleMaximumThickness
Thisbytedefinesthemaximumthickness(Edimension)inmillimetersofthefullyassembledmoduleincludingheat
spreadersorotheraddedcomponentsabovethemodulecircuitboardsurface.Thicknessofthefrontofthemoduleis
calculatedastheE1dimensionminusthePCBthickness.ThicknessofthebackofthemoduleiscalculatedastheE
dimensionminustheE1dimension.RefertotherelevantJEDECJC-11moduleoutline(MO)documentsfordimension
definitions.
Bits7~5Bits4~0
Reserved
ModuleNominalHeightmax,inmm
(baselineheight=15mm)
Reserved00000=height≤15mm
00001=15
00010=16
00011=17
00100=18
...
01010=24
01011=25
...
01111=29
10000=30
...
11111=45mm
Bits7~4Bits3~0
ModuleMaximumThicknessmax,Back,inmm
(baselinethickness=1mm)
ModuleMaximumThicknessmax,Front,inmm
(baselinethickness=1mm)
0000=thickness≤1mm
0001=1
0010=2
0011=3
...
1110=14
1111=15
0000=thickness≤1mm
0001=1
0010=2
0011=3
...
1110=14
1111=15
Note:Thickness=E-E1Note:Thickness=E1-PCB
Release18
JEDECStandardNo.21-C
Page4.1.2.11–32
Byte62(Registered):ReferenceRawCardUsed
ThisbyteindicateswhichJEDECreferencedesignrawcardwasusedasthebasisforthemoduleassembly,ifany.Bits
4~0describetherawcardandbits6~5describetherevisionlevelofthatrawcard.Specialrawcardindicator,ZZ,is
usedwhennoJEDECstandardrawcardwasusedasthebasisforthedesign.Pre-productionmodulesshouldbe
encodedasrevision0inbits6~5.
Bit7Bits6~5Bits4~0
ReferenceRawCardExtensionReferenceRawCardRevisionReferenceRawCard
0=ReferencerawcardsAthroughAL00=revision0
01=revision1
10=revision2
11=revision3
Whenbit7=0,
00000=ReferencerawcardA
00001=ReferencerawcardB
00010=ReferencerawcardC
00011=ReferencerawcardD
00100=ReferencerawcardE
00101=ReferencerawcardF
00110=ReferencerawcardG
00111=ReferencerawcardH
01000=ReferencerawcardJ
01001=ReferencerawcardK
01010=ReferencerawcardL
01011=ReferencerawcardM
01100=ReferencerawcardN
01101=ReferencerawcardP
01110=ReferencerawcardR
01111=ReferencerawcardT
10000=ReferencerawcardU
10001=ReferencerawcardV
10010=ReferencerawcardW
10011=ReferencerawcardY
10100=ReferencerawcardAA
10101=ReferencerawcardAB
10110=ReferencerawcardAC
10111=ReferencerawcardAD
11000=ReferencerawcardAE
11001=ReferencerawcardAF
11010=ReferencerawcardAG
11011=ReferencerawcardAH
11100=ReferencerawcardAJ
11101=ReferencerawcardAK
11110=ReferencerawcardAL
11111=ZZ(noJEDECreferenceraw
carddesignused)
Release18
JEDECStandardNo.21-C
Page4.1.2.11–33
Byte63(Registered):DIMMModuleAttributes
Thisbyteindicatesnumberofregistersusedonamodule.FurtheritindicatesnumberofrowsofDRAMpackages(mono-
lithicorDDPorstacked)paralleltoedgeconnector(independentofDRAMorientation)oneachsideoftheprintedcircuit
board.
Examples:DDR3RDIMMR/CEprogramsbyte63as0x09.DDR3RDIMMR/CFprogramsbyte63as0x0A.
Byte64:RDIMMThermalHeatSpreaderSolution
Thisbytedescribesthemodule’ssupportedthermalheatspreadersolution.
Bit7Bits6~5Bits4~0
ReferenceRawCardExtensionReferenceRawCardRevisionReferenceRawCard
1=ReferencerawcardsAMthroughCB00=revision0
01=revision1
10=revision2
11=revision3
Whenbit7=1,
00000=ReferencerawcardAM
00001=ReferencerawcardAN
00010=ReferencerawcardAP
00011=ReferencerawcardAR
00100=ReferencerawcardAT
00101=ReferencerawcardAU
00110=ReferencerawcardAV
00111=ReferencerawcardAW
01000=ReferencerawcardAY
01001=ReferencerawcardBA
01010=ReferencerawcardBB
01011=ReferencerawcardBC
01100=ReferencerawcardBD
01101=ReferencerawcardBE
01110=ReferencerawcardBF
01111=ReferencerawcardBG
10000=ReferencerawcardBH
10001=ReferencerawcardBJ
10010=ReferencerawcardBK
10011=ReferencerawcardBL
10100=ReferencerawcardBM
10101=ReferencerawcardBN
10110=ReferencerawcardBP
10111=ReferencerawcardBR
11000=ReferencerawcardBT
11001=ReferencerawcardBU
11010=ReferencerawcardBV
11011=ReferencerawcardBW
11100=ReferencerawcardBY
11101=ReferencerawcardCA
11110=ReferencerawcardCB
11111=ZZ(noJEDECreferenceraw
carddesignused)
Bit7~Bit4Bit3~Bit2Bit1~Bit0
Reserved
#ofrowsofDRAMson
RDIMM
#ofRegistersusedon
RDIMM
Reserved00=undefined
01=1row
10=2rows
11=4rows
00=Undefined
01=1register
10=2registers
11=4registers
Release18
JEDECStandardNo.21-C
Page4.1.2.11–34
Byte65:RegisterManufacturerIDCode,LeastSignificantByte
Byte66:RegisterManufacturerIDCode,MostSignificantByte
Thistwo-bytefieldindicatesthemanufactureroftheregisterusedonthemodule,encodedasfollows:thefirstbyteisthe
numberofcontinuationbytesindicatedinJEP-106;thesecondbyteisthelastnon-zerobyteofthemanufacturer’sID
code,againasindicatedinJEP-106.Thesebytesareoptional.FormoduleswithouttheRegisterManufacturerIDCode
informationbothbytesshouldbeprogrammedto0x00.
Example:For“7F7F7F7F7F51”inJEP-106.
Byte65[6:0]:5continuationcodesexpressedinbinary=>0000101
Byte65[7]:Oddparityforbyte65[6:0]=>1
Byte66[7:0]:Lastnon-zerobytefromJEP-106=>0x51
Thisyields0x51and0x85forbytes66and65,respectively.
Bit7Bits6~0
HeatSpreaderSolutionHeatSpreaderThermalCharacteristics
0=Heatspreadersolutionisnotincorporatedontothisassembly
1=Heatspreadersolutionisincorporatedontothisassembly
0=Undefined
Allothersettingstobedefined
Byte66,Bits7~0Byte65,Bit7Byte65Bits6~0
Lastnon-zerobyte,
RegisterManufacturer
Oddparity
forByte65,bits6~0
Numberofcontinuationcodes,
RegisterManufacturer
SeeJEP-106SeeJEP-106
Release18
JEDECStandardNo.21-C
Page4.1.2.11–35
Byte67:RegisterRevisionNumber
Thisbytedefinesthevendordierevisionleveloftheregisteringclockdrivercomponent.Thisbyteisoptional.For
moduleswithouttheRegisterRevisionNumberinformation,thisbyteshouldbeprogrammedto0xFF.
Examples:
Byte68RegisterType
ThisbytedefinesthetypeofsupportdevicethatisusedonthisRDIMMassembly.ItisusedasanindexforSPDBytes
69~76todeterminetheinterpretationofpersonalitywordprogrammingandotherregisterorDIMMimplementation
specificfeatures.
TheprogrammingofSPDbytes69~76isrelatedtomultipledocumentsincludingtheDDR3RegisteredDIMM
Specification,theSSTE32882RegisteringClockDriverspecification,registersupplierdatasheets,andDIMMsupplier
datasheets.
ForJEDECstandardrawcards,theprogrammingoftheregistercontrolwordsisdescribedintheDDR3Registered
DIMMSpecification(intheappendicesforeachrawcard),andtheprogrammingoftheSPDbytescorrespondingtothe
registercontrolwordsisdescribedinBytes69~76below.WherecontrolwordsorcontrolbitsaredefinedasRFUinthe
SPDspecification,theSPDbytesandbitsmustbesetto0toensurefuturecompatibility.
CustomregisteredDIMMdesignsshouldusetheJEDECstandarddesignsasguidelinesasmuchaspossible,thenrefer
totheJEDECSSTE32882specificationandregistersupplierdatasheetsfordetailedinformationonprogrammingthe
devices.Simulationandtestingarerecommendedtoensureproperoperationintargetsystems.Wherecontrolwordsor
controlbitsaredefinedasRFUintheSPDspecification,usersshouldrefertotheseotherdocumentsforprogramming
details.TheSPDbytesandbitsmustbesetto0toensurefuturecompatibility,howeverthesevaluesmayormaynotbe
therequiredvaluessenttotheregisterforproperoperation.SystemBIOSwritersinparticularshouldmakethemselves
awareoftheeffectsofeachregisterprogrammingcode.
Byte69[SSTE32882]:RC1(MSNibble)/RC0(LSNibble)-Reserved
Thisbyteiscurrentlyreservedforfutureuse.
Bits7~0
RegisterRevisionNumber
ProgrammedinstraightHexformat-noconversionneeded.
00-Valid
01-Valid
..
FE-Valid
FF-Undefined(NoRevNumberProvided)
Code
Meaning
0x00Revision0
0x01Revision1
0x31Revision3.1
0xA3RevisionA3
0xB1RevisionB1
Bits7~3Bit2Bit1Bit0SupportDevice
Reserved
000SSTE32882
AllotherencodingsReserved
Release18
JEDECStandardNo.21-C
Page4.1.2.11–36
Byte70[SSTE32882]:RC3(MSNibble)/RC2(LSNibble)-DriveStrength,Command/Address.
Thisbytedefinesthedrivestrengthforaddresses,commands(RC3)appropriatefortheRDIMMdesign.LSNibbleis
RESERVEDforfutureuse.ThisbyteisreferenceddirectlyfromtheSSTE32882specification.
RC1-Reserved,RC0-Reserved
RC1RC0
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
DBA1valueDBA0valueDA4valueDA3valueDBA1valueDBA0valueDA4valueDA3value
Notes:
Reservedforfutureuse.SPDmustbeprogrammedas0x00;refertotheRDIMMandregisterspecificationsforpro-
grammingdetails.
RC2-TimingControlWord,RC3-DriveStrength:Command/Address
RC3RC2
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
DBA1valueDBA0valueDA4valueDA3valueDBA1valueDBA0valueDA4valueDA3value
Command/Address,
BOutputs
Command/Address,
AOutputs
Notes:
Reservedforfutureuse.SPDmustbeprogrammedas0000.
RefertotheRDIMMandregisterspecificationsforprogramming
details.
00=LightDrive
01=ModerateDrive
10=StrongDrive
11=Reserved
00=LightDrive
01=ModerateDrive
10=StrongDrive
11=Reserved
Notes:
StandardvaluesforRC3aredefinedintheDDR3RegisteredDIMMReferenceDesignSpecificationforJEDECstan-
dardmodulereferencedesigns.
Release18
JEDECStandardNo.21-C
Page4.1.2.11–37
Byte71[SSTE32882]:RC5(MSNibble)/RC4(LSNibble)-DriveStrength,ControlandClock
ThecontrolwordlocationforthedriverstrengthforcontrolsignalsfortheSSTE32882isRC4.Thecontrolwordlocation
fortheclockdriverstrengthfortheSSTE32882isRC5.Thisbytedefinesthedrivestrengthforclocksappropriateforthe
RDIMMdesign.ThisbyteisreferenceddirectlyfromtheSSTE32882specification.
Byte72[SSTE32882]:RC7(MSNibble)/RC6(LSNibble)-ReservedforRegisterVendor
SpecificModes
RegistercontrolwordsRC7&RC6arereservedforregistervendorspecificpurposes(forexample,registertestmodes).
ThecorrespondingSPDbyte72shouldbeprogrammedto0x00fornormaloperation.
Byte73[SSTE32882]:RC9(MSNibble)/RC8(LSNibble)-Reserved
Thisbyteiscurrentlyreservedforfutureuse.
Byte74[SSTE32882]:RC11(MSNibble)/RC10(LSNibble)-Reserved
Thisbyteiscurrentlyreservedforfutureuse.
RC5-DriveStrengthClock,RC4-DriveStrength:Control
RC5RC4
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
DBA1valueDBA0valueDA4valueDA3valueDBA1valueDBA0valueDA4valueDA3value
Y0/Y0#andY2/Y2#
ClockOutputs
Y1/Y1#andY3/Y3#
ClockOutputs
ControlSignals,
BOutputs
ControlSignals,
AOutputs
00=LightDrive
01=ModerateDrive
10=StrongDrive
11=Reserved
00=LightDrive
01=ModerateDrive
10=StrongDrive
11=Reserved
00=LightDrive
01=ModerateDrive
10=Reserved
11=Reserved
00=LightDrive
01=ModerateDrive
10=Reserved
11=Reserved
Notes:
StandardvaluesforRC5andRC4aredefinedintheDDR3RegisteredDIMMReferenceDesignSpecificationfor
JEDECstandardmodulereferencedesigns.
RC7-RegisterVendorDefined,RC6-RegisterVendorDefined
RC7RC6
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
DBA1valueDBA0valueDA4valueDA3valueDBA1valueDBA0valueDA4valueDA3value
Notes:
Reservedforfutureuse.SPDmustbeprogrammedas0x00;refertotheRDIMMandregisterspecificationsforpro-
grammingdetails.
RC9-Reserved,RC8-Reserved
RC9RC8
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
DBA1valueDBA0valueDA4valueDA3valueDBA1valueDBA0valueDA4valueDA3value
Notes:
Reservedforfutureuse.SPDmustbeprogrammedas0x00;refertotheRDIMMandregisterspecificationsforpro-
grammingdetails.
Release18
JEDECStandardNo.21-C
Page4.1.2.11–38
Byte75[SSTE32882]:RC13(MSNibble)/RC12(LSNibble)-Reserved
Thisbyteiscurrentlyreservedforfutureuse.
Byte76[SSTE32882]:RC15(MSNibble)/RC14(LSNibble)-Reserved
Thisbyteiscurrentlyreservedforfutureuse.
Bytes77~116(Registered):Reserved
RC11-Reserved,RC10-Reserved
RC11RC10
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
DBA1valueDBA0valueDA4valueDA3valueDBA1valueDBA0valueDA4valueDA3value
Notes:
Reservedforfutureuse.SPDmustbeprogrammedas0x00;refertotheRDIMMandregisterspecificationsforpro-
grammingdetails.
RC13-Reserved,RC12-Reserved
RC13RC12
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
DBA1valueDBA0valueDA4valueDA3valueDBA1valueDBA0valueDA4valueDA3value
Notes:
Reservedforfutureuse.SPDmustbeprogrammedas0x00;refertotheRDIMMandregisterspecificationsforpro-
grammingdetails.
RC15-Reserved,RC14-Reserved
RC15RC14
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
DBA1valueDBA0valueDA4valueDA3valueDBA1valueDBA0valueDA4valueDA3value
Notes:
Reservedforfutureuse.SPDmustbeprogrammedas0x00;refertotheRDIMMandregisterspecificationsforpro-
grammingdetails.
Release18
|
|
