ApplicationReport
SPRA533
DigitalSignalProcessingSolutionsApril1999
TMS320C6000EMIFtoExternalSBSRAM
Interface
KyleCastilleDigitalSignalProcessingSolutions
Abstract
InterfacingexternalsynchronousburstSRAM(SBSRAM)totheTexasInstruments(TI?)
TMS320C6000seriesofdigitalsignalprocessors(DSPs)issimplecomparedtoprevious
generationsofTIDSPsthankstotheadvancedexternalmemoryinterface(EMIF).TheEMIF
providesagluelessinterfacetoavarietyofexternalmemorydevices.
Thisdocumentdescribes:
G72EMIFcontrolregistersandSBSRAMsignals
G72Interfaceschematicofx32/36andx18SBSRAMdevices
G72SBSRAMfunctionalityandperformanceconsiderations
G72Timinganalysisoftheinterfacebetweenvarious‘C6000DSPsandMicronSBSRAM
Contents
InterfaceofEMIFWithSBSRAM.....................................................................................................................2
OverviewofEMIF.............................................................................................................................................5
’C6201/’C6701SBSRAMInterface...........................................................................................................5
’C6202SBSRAMInterface.......................................................................................................................5
’C6211/’C6711SBSRAMInterface...........................................................................................................5
EMIFSignalDescriptions..........................................................................................................................6
EMIFRegisters.......................................................................................................................................12
SBSRAMOperations.....................................................................................................................................14
Non-Burst-ModeAccessesby’C6201,’C6701,and’C6202...................................................................14
Burst-ModeAccessesby’C6211and’C6711.........................................................................................15
OptimizingSBSRAMAccesses...............................................................................................................17
TimingConstraints.........................................................................................................................................17
TMS320C6000Outputs(ED,EA,CE,BE,SSADS,SSOE,SSWE).......................................................18
TimingComparisonsforThreeSBSRAMs..............................................................................................20
CompleteExampleUsing’C6201B................................................................................................................22
Assumptions...........................................................................................................................................22
RegisterConfiguration............................................................................................................................22
CodeSegment........................................................................................................................................23
References.....................................................................................................................................................24
ApplicationReport
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TMS320C6000EMIFtoExternalSBSRAMInterface2
Figures
Figure1.EMIF—Onex36SBSRAMInterface................................................................................................3
Figure2.EMIF—Twox18SBSRAMInterface................................................................................................4
Figure3.EMIF—Onex18SBSRAMInterface................................................................................................5
Figure4.’C6201/’C6701EMIFSBSRAMInterfaceBlockDiagram.................................................................6
Figure5.’C6202EMIFSBSRAMInterfaceBlockDiagram..............................................................................7
Figure6.’C6211/’C6711EMIFSBSRAMInterfaceBlockDiagram.................................................................8
Figure7.FullSpeedInterface—’C6201rev2.1vs.’C6201B/’C6701............................................................10
Figure8.HalfSpeedInterface—’C6201rev2.1vs.’C6201B/’C6701...........................................................11
Figure9.HalfSpeedInterface—’C6202.......................................................................................................11
Figure10.ExternalClockInterface—’C6211/’C6711....................................................................................11
Figure11.ByteLaneAlignmentvs.Endiannessonthe’C6211/’C6711.......................................................12
Figure12.EMIFGlobalControlRegisterDiagram........................................................................................13
Figure13.’C6201/’C6202/’C6701EMIFCESpaceControlRegisterDiagram.............................................13
Figure14.’C6211/’C6711EMIFCESpaceControlRegisterDiagram.........................................................14
Figure15.SBSRAMWrite—HalfSpeed.......................................................................................................15
Figure16.SBSRAMRead—HalfSpeed.......................................................................................................15
Figure17.SBSRAMWriteBurstbythe’C6211/’C6711................................................................................16
Figure18.SBSRAMReadBurstbythe’C6211/’C6711................................................................................17
Figure19.OutputsFrom’C6000(WriteData[ED],Control,andAddressSignals)......................................19
Figure20.OutputsFrom’C6000(WriteData[ED],Control,andAddressSignals)......................................19
Figure21.Inputto‘C6000(ReadData)........................................................................................................20
Figure22.EMIFGlobalControlRegisterDiagram........................................................................................22
Figure23.EMIFCE2SpaceControlRegisterDiagram................................................................................23
Tables
Table1.EMIFSBSRAMPins..........................................................................................................................9
Table2.EMIFMemory-MappedRegistersforSBSRAM..............................................................................12
Table3.EMIFGlobalControlRegisterBitFieldDescriptionforSBSRAM...................................................13
Table4.EMIFCESpaceControlRegisterBitFieldDescriptionforSBSRAM..............................................14
Table5.SBSRAMBurstCounter..................................................................................................................16
Table6.SDRAMRegisters...........................................................................................................................22
InterfaceofEMIFWithSBSRAM
AsshowninFigure1,theEMIFinterfacesdirectlyto32-bit-wideindustrystandard
SBSRAMs.SBSRAMsareavailableinbothflowthroughandpipeline;however,the
‘C6000DSPsinterfaceonlytostandardwritepipelineSBSRAM(eithersingle-ordouble-
cycledeselect),whichhasthecapabilitytooperateathigherfrequencieswithsustained
throughput.
TheSBSRAMinterfaceallowsahigh-speedmemoryinterfacewithoutsomeofthe
limitationsofSDRAM.Mostnotably,becauseSBSRAMsareSRAMdevices,
consecutivereadsorconsecutivewritestoalladdresseswithintheSBSRAMcanoccur
onanycycle.TheSBSRAMinterfacetypicallyrunsathalftheCPUclockrate.Oncertain
‘C6000devices,thisinterfacemayrunateithertheCPUclockspeedorhalfofthisrate,
basedonthesettingoftheSSCRTbitintheEMIFglobalcontrolregister.Other‘C6000
devicesallowthesynchronousmemoryinterfacestorunoffanexternalclockthathasno
relationtotheoperatingfrequencyoftheDSP.
ApplicationReport
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TMS320C6000EMIFtoExternalSBSRAMInterface3
Figure1showstheconnectionsusedtointerfacetoa36-bit-wideSBSRAM.Forthis
interface,thefourparitybitsoftheSBSRAMshouldbetiedtogroundthrougharesistor
becausethe‘C6000databusisonly32bitswideandcannottakeadvantageoftheparity
bits.Thisinterfaceisalmostidenticaltotheinterfacetoa32-bit-wideSBSRAM,except
thata32-bit-wideSBSRAMhasNoConnectsinsteadofparitybits.
Figure1.EMIF—Onex36SBSRAMInterface
x36
SBSRAM
CLK
/ADSC
A[N:0]
DQ[31:0]
/BWE
/BW[4:1]
/CE
/OE
ExternalMemory
Interface(EMIF)
CLK
EA[N+2:2]
/SSADS
ED[31:0]
/SSWE
/BE[3:0]
/CEn
/SSOE
DQP[3:0]
VSS
CLK=SSCLKfor''C6201/''C6701;CLK=CLKOUT2for''C6202;CLK=ECLKOUTfor''C6211/C6711
Figure2showstheconnectionsusedtointerfacetotwo18-bit-wideSBSRAMs.Forthis
example,twoSBSRAMsareusedinparalleltointerfacetothe32-bit-widedatabusof
the‘C6000DSPs.TheadvantageofthisinterfaceisthatwithagivendensitySBSRAM,
theaddressablememoryspaceiseffectivelydoubledbyusingtwodevicesinparallel.
TheparitybitsoftheSBSRAMsaretiedtogroundthroughapull-downresister.
ApplicationReport
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TMS320C6000EMIFtoExternalSBSRAMInterface4
Figure2.EMIF—Twox18SBSRAMInterface
VSS
x18
SBSRAM
CLK
/ADSC
A[N:0]
DQ[15:0]
/BWE
/BW[1:0]
/CE
/OE
DQP[1:0]
x18
SBSRAM
CLK
/ADSC
A[N:0]
DQ[15:0]
/BWE
/BW[1:0]
/CE
/OE
DQP[1:0]
ExternalMemory
Interface(EMIF)
CLK
EA[N+2:2]
/SSADS
ED[31:16]
/SSWE
/BE[3:2]
/CEn
/SSOE
/BE[1:0]
ED[15:0]
VSS
CLK=SSCLKfor''C6201/''C6701;CLK=CLKOUT2for''C6202;CLK=ECLKOUTfor''C6211/C6711
Figure3showsaninterfacetoasinglex18SBSRAM.Thisinterfacemaybeattractive
forlow-costapplicationswheredevicecountandboardspacearecritical.Thisinterface
isonlysupportedonthe‘C6211and‘C6711devices.
ApplicationReport
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TMS320C6000EMIFtoExternalSBSRAMInterface5
Figure3.EMIF—Onex18SBSRAMInterface
VSS
x18
SBSRAM
CLK
/ADSC
A[N:0]
DQ[15:0]
/BWE
/BW[1:0]
/CE
/OE
DQP[1:0]
ExternalMemory
Interface(EMIF)
CLK
+
EA[N+2:2]
/SSADS
/SSWE
/BE[1:0]
/CEn
/SSOE
ED[15:0]
+CLK=ECLKOUTfor''C6211/C6711
OverviewofEMIF
’C6201/’C6701SBSRAMInterface
G72Canoperateateither1/2xtheCPUclockspeedor1xtheCPUclockspeed
G72SSCLKisusedastheSBSRAMclock.
G72HasdedicatedSBSRAMcontrolsignals.Anycombinationofsynchronousmemory
typesisallowed.
G72Onlysupports32-bit-wideSBSRAMinterface
’C6202SBSRAMInterface
G72Canoperateat1/2xtheCPUclockspeed
G72CLKOUT2isusedastheSBSRAMclock.
G72SBSRAMcontrolsignalsareMUXedwithSDRAMcontrolsignals.Onlyonetypeof
synchronousmemoryisallowedinthesystem.
G72Onlysupports32-bit-wideSBSRAMinterface
’C6211/’C6711SBSRAMInterface
G72ClockspeedisindependentofinternalCPUspeedandcanrunatamaximumof100
MHz.AnexternalclockcanbetiedtoECLKINformaximumflexibilityorCLKOUT2
canberoutedbacktoECLKINforsimplicity,resultinginamemoryclockspeedof
1/2xtheCPUclockspeed.
ApplicationReport
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TMS320C6000EMIFtoExternalSBSRAMInterface6
G72ECLKOUTmustbeusedasthesynchronousmemoryclockandisamirrorimageof
ECLKIN.
G72SBSRAMcontrolsignalsareMUXedwithSDRAMandAsynccontrolsignals.Any
combinationofsynchronousmemorytypesisallowed.
G728-bit-wideand16-bit-wideinterfacesareallowed.Thedatabusbytelanesused
dependontheendiannessofthesystem.
EMIFSignalDescriptions
Figure4showsablockdiagramoftheEMIF,theinterfacebetweenexternalmemoryand
theotherinternalunitsofthe‘C6000.Onthe‘C6201,‘C6701,and‘C6202,theinterface
withtheprocessorisprovidedviatheDMA(directmemoryaccess)controller,program
memorycontroller,anddatamemorycontroller.Forthe‘C6211and‘C6711,the
interfacewiththeprocessorisprovidedviatheenhancedDMA.
Figure4throughFigure6showtheblockdiagramsofthe‘C6201/’C6701,‘C6202,and
‘C6211/’C6711respectively.Notethattheclocksandthecontrolsignalsareslightly
differentforeachofthethreedifferentstyleEMIFs.ThesignalslistedinTable1describe
theSBSRAMinterfaceandthesharedinterfacesignals.
Figure4.’C6201/’C6701EMIFSBSRAMInterfaceBlockDiagram
Sharedbyall
externalinterfaces
Internalperipheralbusinterface
DMAinterface
DataAccess
ProgramAccess
ED[31:0]
EA[21:2]
/CE[3:0]
/BE[3:0]
''C6201/
''C6701
EXTERNAL
MEMORY
INTERFACE
(EMIF)
CLKOUT1
CLKOUT2
SBSRAMInterface
BusHold
Interface
/SSADS
/SSOE
/SSWE
SSCLK
/HOLD
/HOLDA
ApplicationReport
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TMS320C6000EMIFtoExternalSBSRAMInterface7
Figure5.’C6202EMIFSBSRAMInterfaceBlockDiagram
Sharedbyall
externalinterfaces
Internalperipheralbusinterface
DMAinterface
DataAccess
ProgramAccess
ED[31:0]
EA[21:2]
/CE[3:0]
/BE[3:0]
''C6202
EXTERNAL
MEMORY
INTERFACE
(EMIF)
CLKOUT1
CLKOUT2
SBSRAMInterface
BusHold
Interface
#SDCAS/#SSADS
#SDRAS/#SSOE
#SDWE/#SSWE
/HOLD
/HOLDA
ApplicationReport
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TMS320C6000EMIFtoExternalSBSRAMInterface8
Figure6.’C6211/’C6711EMIFSBSRAMInterfaceBlockDiagram
#AWE/#SDWE/#SSWE
#ARE/#SDCAS/#SSADS
Sharedbyall
externalinterfaces
EnhancedDatamemorycontroller
ED[31:0]
EA[21:2]
/CE[3:0]
/BE[3:0]
''C6211/
''C6711
EXTERNAL
MEMORY
INTERFACE
(EMIF)
CLKOUT1
CLKOUT2
SBSRAMInterface
BusHold
Interface
#AOE/#SDRAS/#SSOE
/HOLD
/HOLDA
ECLKIN
ECLKOUT
BUSREQ
Internalperipheralbusinterface
ApplicationReport
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TMS320C6000EMIFtoExternalSBSRAMInterface9
Table1.EMIFSBSRAMPins
SBSRAM
Signal
‘C6201/
’C6701
Interface
‘C6202
Signal
Interface
‘C6211/
’C6711
Interface
SBSRAMFunction
/CE/CEx/CEx/CExChipEnable./CEmustbeactive(low)fora
commandtobeclockedintotheSBSRAM.
CLKSSCLKCLKOUT2ECLKOUTSBSRAMClock.Runsateither1xor1/2xthe
CPUrate.
/ADSC/SSADS#SDCAS/
#SSADS
#ARE/
#SDCAS/
#SSADS
SynchronousAddressStrobe:Causesanew
externaladdresstoberegistered.If/CEis
active,aREADorWRITEisperformed.
/OE/SSOE#SDRAS/
#SSOE
#AOE/
#SDRAS/
#SSOE
OutputEnable.EnablesthedataI/Odrivers.
/BWE/SSWE#SSWE/
#SSWE
#AWE/
#SSWE/
#SSWE
WriteEnable.Permitswriteoperations.
/BW[4:1]/BE[3:0]/BE[3:0]/BE[3:0]ByteWriteEnables.Allowindividualbytesto
bewrittenwhen/BWEisactive.AByteWrite
EnableisLOWforaWRITEandDON’T
CAREforaREADcycle./BW1controlsByte
1,/BW2controlsByte2,/BW3controlsByte
3,and/BW4controlsByte4.
A[N:0]EA[N+2:2]EA[N+2:2]EA[N+2:2]AddressInputs.Registeredonrisingedgeof
SSCLK..
DQ[32:1]ED[31:0]ED[31:0]ED[31:0]DataI/O.Byte1isDQ[8:1],Byte2is
DQ[16:9],Byte3isDQ[24:17],andByte4is
DQ[32:25].
/ADV3.3V3.3VGND‘C6201/’C6701/’C6202:/ADVistiedto3.3Vto
disabletheburstmodeoftheSBSRAM
becauseburstingisaccomplishedbyissuing
back-to-backreadsorwrites.
‘C6211/’C6711:/ADVistiedtoGNDtoenable
theburstmodeoftheSBSRAM.
/CE2GNDGNDGNDEnable/CE2atalltimes.
MODEGNDGNDGNDSelectlinearburst.
ZZGNDGNDGNDDisablesnoozemode.
VSSGNDGNDGNDGround
VCC3.3V3.3V3.3V3.3Vsupply
CE23.3V3.3V3.3VEnableCE2atalltimes.
/ADSP3.3V3.3V3.3VDisable/ADSPatalltimes.
/GW3.3V3.3V3.3VDisableglobalwriteatalltimes.
Parity
Data
1kG57to
GND
1kG57to
GND
1kG57to
GND
TerminateParitydatabecauseitisnotused
on‘C6000interfaces.
Note:Boldtextrepresentsadeparturefromthestyleofinterfaceusedforthe''6201.
ApplicationReport
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TMS320C6000EMIFtoExternalSBSRAMInterface10
Clockingthe’C6211/’C6711EMIF
TheEMIFofthe‘C6211/’C6711requiresanexternalclocktobeprovidedviatheECLKIN
input.Forsimplicity,CLKOUT2canberoutedintotheECLKINpintoavoidtheextra
hardwarerequiredtocreateaclockexternally.Thismethodhastherestrictionofonly
allowingamemoryinterfaceat1/2xtheCPUclockspeed(or75MHzfora150-MHz
device).
Ifanexternalclockisprovided,theEMIFcanoperateupto100MHz.The‘C6211and
’C6711datasheetsspecifythattherise/falltimeoftheexternallyprovidedclockmustbe
nolongerthan3ns.Thiscanprovedifficultwithmostoff-the-shelfoscillators.Our
recommendedapproachistousetheICS501PLLMultiplierchip,whichcanproducea
widerangeoffrequencyoutputswithstandardcrystals.
Clock-to-OutputRelationshipon’C6000Devices
Tooptimizethesynchronousmemoryinterfacesofthevarious‘C6000devices,the
outputsignalsaretriggeredoffofdifferentinternalclocksofthe‘C6000DSP.Figure7
throughFigure10showtheclockrelationshipusedforthevarious‘C6000DSPs.
Becausethe‘C6211/’C6711SBSRAMinterfaceistimedinreferencetoanexternally
providedclock,the‘C6211and‘C6711datasheetsprovidetdmaxandtdminbutnot
TosuandTohparameters.ThefactthattheTosuandTohparametersuseafactorofP
intheequationsallowstheusertobeunconcernedabouttheoutputedgebeingused
internaltothe‘C6000.Inthisway,theTosuparametercanbecompareddirectlyagainst
theTisuparameterofthememoryatagivenoperatingspeed.(Formoredetails,seethe
TimingConstraintssection.)
Thetdmaxandtdminparametersreferencetheactualclockedgeofthe‘C6000from
whichdataisdrivenout.TheTosuandTohtermsarethenotationusedin‘C6000data
sheetsexceptthoseforthe‘C6211and‘C6711.TheTosutermshowsthesetuptimeto
therisingedgeoftheclock.TheTohtermshowstheholdtimefromtherisingedgeofthe
memoryclock.PreferstotheCPUclockperiod.
Noticethatthedatasheetnotationdirectlyimpliestheclockingrelationshipofthedevice.
Forexample,thedatasheetforthefullspeed‘C6201BSBSRAMinterfacestatesthat
Tosu=0.5P–1.3.ReferringtothediagraminFigure7,itcanbeseenthattdmaxis
relativetothefallingedgeofSDCLK,providingasetuptimeof0.5P–tdmax.Allother
‘C6000datasheetscanbeanalyzedinthesameway.
Figure7.FullSpeedInterface—’C6201rev2.1vs.’C6201B/’C6701
Toh=0.5P+Tdmin
tdmin
Tosu=0.5P-tdmax
tdmax
Toh=tdmin
tdmin
Tosu=P-tdmax
tdmax
PP
SSCLK(1x)
''C6201rev2.x
''C6201B/''C6701
ApplicationReport
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TMS320C6000EMIFtoExternalSBSRAMInterface11
Figure8.HalfSpeedInterface—’C6201rev2.1vs.’C6201B/’C6701
Toh=0.5P+Tdmin
tdmin
Tosu=1.5P-tdmax
tdmax
Toh=P+tdmin
tdmin
Tosu=P-tdmax
tdmax
PPP
1/2P
P
1/2P
SSCLK(1/2x)
''C6201rev2.1
''C6201B/''C6701
Figure9.HalfSpeedInterface—’C6202
Toh=tdmin
tdmin
Tosu=2P-tdmax
tdmax
PPPP
CLKOUT2
''C6202
Figure10showstheclockrelationshipusedforthe‘C6211/’C6711SBSRAMinterface.
Becausethisinterfaceistimedinreferencetoanexternallyprovidedclock,the‘C6211
and‘C6711datasheetsprovideTdmaxandTdminbutnotTosuandTohparameters.
Figure10.ExternalClockInterface—’C6211/’C6711
tdmintdmax
EE
ECLKOUT
''C6211/''C6711
ByteLaneAlignmentonthe’C6211/’C6711EMIF
The‘C6711EMIFoffersthecapabilitytointerfaceto32-bit,16-bit,and8-bitSBSRAM.
Dependingontheendiannessofthesystem,adifferentbytelaneisusedforthe
SBSRAMinterface.ThealignmentrequiredisshowninFigure11.
NotethatBE3alwayscorrespondstoED[31:24],BE2alwayscorrespondstoED[23:16],
BE1alwayscorrespondstoED[15:8],andBE0alwayscorrespondstoED[7:0],
regardlessofendianness.
ApplicationReport
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TMS320C6000EMIFtoExternalSBSRAMInterface12
Figure11.ByteLaneAlignmentvs.Endiannessonthe’C6211/’C6711
''C6211/''C6711
ED[31:24]ED[23:16]ED[15:8]ED[7:0]
8BitDevice
BigEndian
8BitDevice
LittleEndian
16BitDevice
BigEndian
16BitDevice
LittleEndian
32BitDevice
EMIFRegisters
ControloftheEMIFandthememoryinterfacesitsupportsismaintainedthroughasetof
memory-mappedregisterswithintheEMIF.AwritetoanyEMIFregistershouldnotbe
donewhileEMIFaccessesareinprogress.Thememory-mappedregistersareshownin
Table2.
Table2.EMIFMemory-MappedRegistersforSBSRAM
ByteAddressName
0x01800000EMIFGlobalControl
0x01800004EMIFCE1SpaceControl
0x01800008EMIFCE0SpaceControl
0x0180000CReserved
0x01800010EMIFCE2SpaceControl
0x01800014EMIFCE3SpaceControl
EMIFGlobalControlRegister
Figure12showstheEMIFglobalcontrolregister,whichconfiguresparameterscommon
toalloftheCEspaces.Table3onlyliststhoseparametersthatarerelevantforusewith
SBSRAM.
1
1
ForadescriptionofalloftheparametersoftheEMIFglobalcontrolregister,seetheTMS320C6000
PeripheralsReferenceGuide.
ApplicationReport
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TMS320C6000EMIFtoExternalSBSRAMInterface13
Figure12.EMIFGlobalControlRegisterDiagram
3114131211109876543210
reservedReservedBUS
REQ
2
ARDYHOLDHOLDANOHOLDSDCEN
3
SSCEN
3
CLK1ENCLK2EN
4
SSCRT
34
RBTR8
3
MAP
3
R,+0R,+1R,+0R,+xR,+xR,+0RW,+0RW,+1RW,+1RW,+1RW,+1RW,+0RW,+0R,+x
Table3.EMIFGlobalControlRegisterBitFieldDescriptionforSBSRAM
FieldDescription
SSCENSBSRAMclockenable(for‘C6201,‘C6701,and‘C6202)
‘C6201/’C6701:
SSCEN=0,SSCLKheldhigh
SSCEN=1,SSCLKenabledtoclock
‘C6201/’C6701:
SSCEN=0,CLKOUT2heldhighifMemType=SBSRAM
SSCEN=0,CLKOUT2enabledtoclockif
MemType=SBSRAM
SSCRTSBSRAMclockrateselect(‘C6201/’C6701only)
SSCRT=0,SSCLK?xCPUclockrate
SSCRT=1,SSCLK1xCPUclockrate
CESpaceControlRegisters
Figure13andFigure14showthefourCEspacecontrolregisters,whichcorrespondto
thefourCEspacessupportedbytheEMIF.TheMTYPEfieldidentifiesthememorytype
forthecorrespondingCEspace.IfMTYPEselectsSDRAMorSBSRAM,theremaining
fieldsintheregisterdonotapply.Ifanasynchronoustypeisselected(ROMor
Asynchronous),theremainingfieldsspecifytheshapingoftheaddressandcontrol
signalsforaccesstothatspace.TheonlyfieldofinterestforSBSRAMistheMTYPE
field.ModificationofaCEspacecontrolregistershouldnotbedoneuntilthatCEspace
isinactive.
Figure13.’C6201/’C6202/’C6701EMIFCESpaceControlRegisterDiagram
3128272221201916
WRITESETUPWRITESTROBEWRITEHOLDREADSETUP
RW,+1111RW,+111111RW,+11RW,+1111
15141387643210
TAREADSTROBERsvMTYPEReservedREADHOLD
RW,+11RW,+111111R,+0RW,+010R,+0RW,+11
2
FieldexistsonlyinTMS320C6211/TMS320C6711.
3
FieldsdonotexistinTMS320C6211/TMS320C6711.
4
FieldsdonotexistinTMS320C6202.
ApplicationReport
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TMS320C6000EMIFtoExternalSBSRAMInterface14
Figure14.’C6211/’C6711EMIFCESpaceControlRegisterDiagram
3128272221201916
WRITESETUPWRITESTROBEWRITEHOLDREADSETUP
RW,+1111RW,+111111RW,+11RW,+1111
1514138743210
TAREADSTROBEMTYPEWriteHold
MSB
READHOLD
RW,+11RW,+111111RW,+010RW,+0RW,+011
Table4.EMIFCESpaceControlRegisterBitFieldDescriptionforSBSRAM
FieldDescription
MTypeMemoryType
Alldevices:
MTYPE=100b:32-bit-wideSBSRAM
‘C6211/’C6711only:
MTYPE=1010b:8-bit-wideSBSRAM
MTYPE=1011b:16-bit-wideSBSRAM
SSCRTSBSRAMclockrateselect
‘C6201/’C6701only:
SSCRT=0,SSCLK?xCPUclockrate
SSCRT=1,SSCLK1xCPUclockrate
SBSRAMOperations
ThestyleofSBSRAMoperationsdependsonwhetherornotburstingisdonebydefault.
Onthe‘C6201,‘C6701,and‘C6202,theburstmodeoftheSBSRAMisnotused(/ADVis
disabledbytyingithigh).Instead,burstingisaccomplishedbyissuinganewcommand
oneveryclockcycle.
Onthe‘C6211and‘C6711,theburstmodeoftheSBSRAMisused.Whenacommandis
issued,asequentialburstoffourwordsisperformedto/fromtheSBSRAM(/ADVis
enabledbytyinglow).
Non-Burst-ModeAccessesby’C6201,’C6701,and’C6202
Forthe‘C6201,‘C6202,and‘C6701interfacetoSBSRAM,theburstmodeofthe
SBSRAMmustbedisabled.Thereisnoassociatedperformancedegradationbecause
burstscanstillbedone.Burstsareaccomplishedbyissuingcommandsonconsecutive
cyclesandcanachieveapeakthroughputequaltotheclockspeedoftheinterface.
Figure15showsafour-wordwritetoSBSRAM.Everyaccessstrobesanewaddress
intotheSBSRAM.
ApplicationReport
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TMS320C6000EMIFtoExternalSBSRAMInterface15
Figure15.SBSRAMWrite—HalfSpeed
BE1BE2BE3BE4
A1A2A3A4
D1D2D3D4
Write/D4Latched
Write/D3Latched
Write/D2Latched
Write/D1Latched
CLK
/CEx
/BE[3:0]
EA[21:2]
ED[31:0]
/SSADS
/SSOE
/SSWE
Figure16showsafour-wordreadofanSBSRAM.Everyaccessstrobesanewaddress
intotheSBSRAM,indicatedbythe/SSADSstrobelow.Thefirstaccessrequiresan
initialreadlatencyof2cycles;thereafter,allaccesseshavesinglecyclethroughput.
Figure16.SBSRAMRead—HalfSpeed
BE1BE2BE3BE4
A1A2A3A4
Q1Q2Q3Q4
Q4Latched
Q3Latched
Read/Q2Latched
Read/Q1LatchedReadRead
CLK
/CEx
/BE[3:0]
EA[21:2]
ED[31:0]
/SSADS
/SSOE
/SSWE
Burst-ModeAccessesby’C6211and’C6711
The‘C6211and‘C6711takeadvantageoftheinternalburstcounterofSBSRAMswhen
performingaccesses(/ADVisalwaysactive,tiedlow).Althoughaperformance
advantageisnotrealizedbecauseburstscantakeplacebyissuingconsecutive
commands,thisinterfacedoesoffertheadvantageofissuingfewercommandstothe
SBSRAM.Thisresultsinslightlylowerpowerconsumptioncomparedtotheother
‘C6000devices.
ApplicationReport
SPRA533
TMS320C6000EMIFtoExternalSBSRAMInterface16
TheinternalburstcounterofSBSRAMisafour-wordcounter,whichcanbeprogrammed
toincrementlinearlyorinaninterleavedfashion.Table5showstheaddressingofthe
SBSRAMinlinearmode,whichmustbeusedforthe‘C6211/’C6711interface.AsTable
5shows,the2-bitcounterautomaticallyrollsoverto00from11.Forexample,ifaddress
0111bwereissuedtotheSBSRAMinburstmode,thesubsequentaccesswouldbeto
0100b,iftheSBSRAMwereallowedtocontinuetheburst.Accessesdonebythe
‘C6211/’C6711preventthisbyissuinganewcommandtotheSBSRAMbeforetheburst
counterrollsover.So,ifanaccessto0111bisbegun,onthesubsequentcyclethe
‘C6211/’C6711willissueaddress1000btocontinuethelinearburst.
Randomordecrementingaccessescanstillbeperformedbythe‘C6211and‘C6711.
Thisisdoneinthesamemannerasthe‘C6201styleinterface.Thatis,ifrandom
accessesareperformed,anewcommandwillbeissuedoneverycycletointerruptthe
burstmodeoftheSBSRAM.
Table5.SBSRAMBurstCounter
Case1Case2Case3Case4
SBSRAMAddressA[1:0]A[1:0]A[1:0]A[1:0]
EMIFAddressEA[3:2]EA[3:2]EA[3:2]EA[3:2]
Firstaddress00011011
01101100
10110001
FourthAddress11000110
Figure17showsasix-wordwriteburstthatbeginsataddress0100b.Sincethetwo
LSBs(least-significantbits)are00,the‘C6211/’C6711allowstheinternalburstcounterto
incrementupto0111b.Onthefifthcycle,anewcommandisissuedtoaddress1000bto
continuetheburst.
Figure17.SBSRAMWriteBurstbythe’C6211/’C6711
BE1BE2BE3BE4
EA[5:2]=0100EA[5:2]=1000
D1D2D3D4D5D6
Deselect
D6Latched
Write/D5Latched
D4Latched
D3Latched
D2Latched
Write/D1Latched
ECLKOUT
/CEx
/BE[3:0]
EA[21:2]
ED[31:0]
/SSADS
/SSOE
/SSWE
Figure18showsasix-wordreadburstthatbeginsataddress010b.Becausethetwo
LSBsare10b,the‘C6211/’C6711allowstheinternalburstcountertoincrementupto
011b.Onthethirdcycle,anewcommandisissuedtoaddress100btocontinuethe
linearburst.
ApplicationReport
SPRA533
TMS320C6000EMIFtoExternalSBSRAMInterface17
Figure18.SBSRAMReadBurstbythe’C6211/’C6711
BE1BE2BE3BE4BE5BE6
EA[4:2]=010bEA[4:2]=100
Q1Q2Q3Q4Q5Q6
Deselect/Q6La
Q5Latched
Q4Latched
Q3Latched
Q2Latched
Read/Q1Latched
Read
ECLKOUT
/CEx
/BE[3:0]
EA[21:2]
ED[31:0]
/SSADS
/SSOE
/SSWE
OptimizingSBSRAMAccesses
SBSRAMsarelatentbytheirarchitecture,meaningthatreaddatafollowsaddressand
controlinformation.Consequently,theEMIFinsertscyclesbetweenreadandwrite
commandstoensurethatnoconflictexistsontheED[31:0]bus.TheEMIFkeepsthis
turnaroundpenaltytoaminimum.Theinitial3-cyclepenaltyispresentwhenchanging
directionsonthebus.
Ingeneral,theruleisthatthefirstaccessofaburstsequencewillincuratleasta3-cycle
startuppenalty.Therefore,tomaximizethroughput,attempttominimizedirection
changesonthedatabuswhenaccessingSBSRAM.
TimingConstraints
ThissectiondiscussesthetimingconstraintsusedtodetermineifanSBSRAMcan
operatewiththe‘C6000atagivenclockfrequency.
Forthefollowingconstraintcalculations,atimet
margin
iscalculatedrepresentingthe
margininthesystemaftertakingintoaccounttheworst-casenumbersfromthememory
andthe‘C6000datasheets.
Aftercalculatingthetimet
margin
,itisasystem-levelissuetodetermineiftheproper
amountofmarginhasbeenmet.Therequiredtimingmarginisextremelysystem
dependent,dependingprimarilyontracelengthandloading,butotherfactorscancome
intoplay.Therefore,thisparametershouldbedeterminedfortheparticularsystemin
question.
Ingeneral,thetimingmarginrequiredisnotthesameforthedifferentparametersofthe
read/writecycles.Foroutputsignals,therequiredtimingmarginisminimalbecausethe
outputclockandoutputcontrol/datasignalsbothpropagatefromthe‘C6000DSPtothe
SBSRAM.Therefore,thetimingmarginmustaccountforthepossibleskewbetweenthe
twosignals(clockversuscontrol/data)causedbyloadingeffectsordifferencesinroute
length.
ApplicationReport
SPRA533
TMS320C6000EMIFtoExternalSBSRAMInterface18
Forexample,signalsonaboardmanufacturedwith0.5-ouncecoppertracesinFR4
exhibitapropagationdelaytimeof~0.17nsperinch.Iftheskewbetweenclockand
outputsignalsis±3inches,therequiredboardmarginis~0.5nsforbothoutputsetup
andhold.Thisdoesnotconsidersettlingtimeeffectsorotherloadingissuesthatshould
beconsideredwhendeterminingtheamountofmarginrequired.
Thetimingmarginrequiredforreadsismorecomplicated.Theissuewithreadsisthat
thememoryisoutputtingdatarelativetoaclockthathasundergoneapropagationdelay
whentravelingfromthe‘C6000DSPtotheSBSRAM.Thememoryoutputsthedataa
timet
acc
fromthisdelayedclock.Theoutputdatafromthememoryundergoesadelay
itselfbeforearrivingatthe‘C6000DSP.Therefore,thetimingmarginforreadsetupmust
accountforthesetwopropagationdelays.Thereadholdtimeisimprovedbecauseof
thisandthemarginrequiredcanbeconsiderednegligible.
Usingthesameboardcharacteristicspreviouslyused,thisimpliesthatifboththeclock
anddatapathsareapproximately3incheslong,theroundtrippropagationdelayfor
clocktoSBSRAMandfordatabacktothe‘C6000isapproximately1ns(6inchesGB4170
ps/inch).Therefore,themarginrequiredforreadsinthisexampleisatleast1nsonthe
inputsetuptimeand<0nsontheinputholdtime.Thisdoesnotconsidersettlingtime
effectsorotherloadingissuesthatshouldbeconsideredwhendeterminingtheamountof
marginrequired.
Thesenumbersareguidelines.Theactualmarginrequiredforanysystemmightbe
different.
Inthefollowingdiscussion,misusedtodenotethememoryspecifications.Noadditional
designatorsareusedtodenotethe‘C6000DSPtimingspecifications.
TMS320C6000Outputs(ED,EA,CE,BE,SSADS,SSOE,SSWE)
’C6201/’C6701/’C6202OutputComparison
Forsimplicity,the‘C6201,‘C6701,and‘C6202datasheetsspecifytheoutputsasasetup
time(tosu)tothenextrisingedgeandaholdtime(toh)fromthepreviousrisingedge.
Thus,thecomparisonbetween‘C6000specificationsandmemoryspecificationsis
extremelystraightforward.Thisalsoallowstheusertobeunconcernedwithwhichclock
edgetriggersoutputdata.
Thefollowingequations,derivedfromFigure19,shouldbeusedtocalculatethetiming
marginbetweenthe‘C6000andthedesiredSBSRAM.
G72Setuptime:Outputsetuptime(t
osu
)frominactivetoactivemustprovideanample
setuptime(t
isu(m)
)fortheinput.Therefore,themarginavailableis:
t
margin
=t
osu
–t
isu(m)
G72Holdtime:Outputholdtime(t
oh
)fromactivetoinactivemustbegreaterthanthehold
timerequiredbytheinput(t
ih(m)
).Themarginisthen:
t
margin
=t
oh
–t
ih(m)
ApplicationReport
SPRA533
TMS320C6000EMIFtoExternalSBSRAMInterface19
Figure19.OutputsFrom’C6000(WriteData[ED],Control,andAddressSignals)
SBSRAMLatchesSignal
toh
tih(m)tisu(m)
tosu
TcycTcyc
EMIFClock
''C6000Output
’C6211/’C6711OutputComparison
The‘C6211and‘C6711datasheetsspecifytheoutputsasaminimumdelayanda
maximumdelayfromtherisingedgeofECLKOUT.Whencomparingtheseparameters
againstthespecificationforaparticularSBSRAM,themaximumdelay(t
dmax
)isusedto
verifythattheinputsetuptime(t
is(m)
)ofthememoryismet.Theminimumdelay(t
dmin
)is
usedtoverifythattheinputholdtime(t
ih(m)
)ofthememoryismet.
Thefollowingequations,derivedfromFigure20,shouldbeusedtocalculatethetiming
marginbetweenthe‘C6211/’C6711andthedesiredSBSRAM.
G72Setuptime:Themaximumdelay(t
dmax
)fromclocktooutputsignalvalidmustprovide
anamplesetuptime(t
isu(m)
)fortheinput.Therefore,themarginavailableis:
t
margin
=t
cyc
–(t
dmax
+t
isu(m)
)
G72Holdtime:Theminimumdelay(t
dmin
)fromclocktooutputsignalinvalidmustbe
greaterthantheholdtimerequiredbytheinput(t
ih(m)
).Themarginisthen:
t
margin
=t
oh
–t
ih(m)
Figure20.OutputsFrom’C6000(WriteData[ED],Control,andAddressSignals)
SBSRAMLatchesData
tdmin
tih(m)
tisu(m)
tdmax
TcycTcyc
EMIFClock
''C6000Outputs
ApplicationReport
SPRA533
TMS320C6000EMIFtoExternalSBSRAMInterface20
’C6000Inputs(OutputDataFromtheSBSRAM,ReadED)
Figure21showstheoutputdatafromtheSBSRAMasitoccursduringareadcycle.The
situationissimilartotheoutputsfromthe‘C6000exceptthattheSBSRAMmustprovide
anamplesetupandinputholdtothe‘C6000.
Theconstraintscanbeexpressedasfollows:
G72Setuptimes:Theaccesstime(t
acc(m)
)oftheSBSRAMmustprovidealargeenough
inputsetuptime(t
su
)fortheinputtothe‘C6000.
t
margin
=t
cyc
–(t
acc(m)
+t
su
)
G72Holdtimes:theoutputholdtime(t
oh(m)
)fordataoutputfromtheSBSRAM,must
provideaholdtimegreaterthantheholdtimerequiredbytheinput(t
ih
)ofthe‘C6000.
t
margin
=t
oh(m)
–t
ih
Figure21.Inputto‘C6000(ReadData)
''C6xLatchesData
toh(m)
tihtsu
tacc(m)
TcycTcyc
EMIFClock
ReadData
TimingComparisonsforThreeSBSRAMs
ThissectionsummarizesthecomparisonslistedaboveforthreedifferentSBSRAMswith
threedifferent‘C6000devices.Althoughnotevery‘C6000deviceisshowninthe
followingexamples,theapproachisthesameforallofthecurrent‘C6000devices.
Forthefollowingexamples,noticethatmoremarginisachievedwithafastermemory.
Forexample,ifa100-MHzinterfaceisdesired,a133-MHzSBSRAMwillprovidemore
marginthana100-MHzSBSRAM.Althoughthe‘C6000DSPsaredesignedtooperate
withSBSRAMsattheratedspeeds,sometimestheextramarginmaybeworththeextra
costoffastermemories.SeveralvendorshaveSBSRAMdevicesavailableat100MHz
orfaster.Thenewestdatasheetsandshouldbecomparedtothe‘C6000datasheetto
guaranteeoperationwiththedesiredmargins.
’C6201Bvs.Micron’sMT58L128L32P-7.5at100MHz
TheMT58L128L32Pdeviceisa128Kx32device,whichresultsinanaddressablespace
of512KB.
Thisexampleusesthe‘C6201B-200runningatitsmaximumclockspeedof200MHz(P
=5).Forthisexample,weassumethatSSCLKissettooperateat1/2xtheCPUspeed,
resultinginTcyc=10ns.
ThetimingparametersoftheMT58L128L32P-7.5andthe‘C6201B-200canbe
summarizedasfollows:
ApplicationReport
SPRA533
TMS320C6000EMIFtoExternalSBSRAMInterface21
‘C6201B-200@P=5nsMT58L128L32P-7.5Tmargin
Tosu=1.5P–3=4.5nsTisu(m)=1.5nsTosu–Tisu(m)=3nsG61
Outputs
Toh=0.5P–1.5=1ns
Inputs
Tih(m)=0.5nsToh–Tih(m)=0.5nsG61
Tisu=2.5Tacc(m)=4.2nsTcyc–Tacc(m)–tisu=3.3nsG61
Inputs
Tih=1.5
Outputs
Toh(m)=1.5nsToh–Tih(m)=0nsG61
’C6202vs.Micron’sMT58L512L18D-7.5at125MHz
TheMT58L512L18Disa512Kx18device.Forthe‘C6202interface,twoofthese
devicesareusedinparallel,resultinginanaddressablespaceof2MB.
Thisexampleusesthe‘C6202-250runningatitsmaximumclockspeedof250MHz(P=
4ns).Becausethe‘C6202EMIFusesCLKOUT2(whichis1/2xtheCPUspeed)for
synchronousmemoryinterfaces,Tcyc=8ns.
ThetimingparametersoftheMT58L512L18D-7.5andthe‘C6202-250canbe
summarizedasfollows:
‘C6202-250@P=4nsMT58L512L18P-7.5Tmargin
Tosu=2P–3.8=4.2nsTisu(m)=1.5nsTosu–Tisu(m)=2.7nsG61
Outputs
Toh=1ns
Inputs
Tih(m)=0.5nsToh–Tih(m)=0.5nsG61
Tisu=2Tacc(m)=4.0nsTcyc–Tacc(m)–tisu=2nsG61
Inputs
Tih=1.5
Outputs
Toh(m)=1.5nsToh–Tih(m)=0nsG61
’C6711vs.Micron’sMT58LC64K32D9-10at100MHz
TheMT58LC64K32D9isa64Kx32device,whichresultsinanaddressablespaceof
256KB.
Thisexampleusesthe‘C6711-150runningatitsmaximumclockspeedof150MHz
(P=6.67ns).BecausetheCPUspeedisindependentoftheEMIFclockspeed,weuse
anexternallyprovidedclockof100MHzforthesynchronousmemoryinterface,resulting
inTcyc=10ns.
ThetimingparametersoftheMT58LC64K32D9-10andthe‘C6711-150canbe
summarizedasfollows:
‘C6711-150MT58LC64K32D9-10Tmargin
Tdmax=6.0nsTisu(m)=2.2nsTcyc–Tdmax–Tisu(m)=1.8nsG61
Outputs
Tdmin=1.5ns
Inputs
Tih(m)=0.5nsToh–Tih(m)=1.0nsG61
Tisu=1.5Tacc(m)=5.0nsTcyc–Tacc(m)–tisu=3.5nsG61
Inputs
Tih=1.0
Outputs
Toh(m)=1.5nsToh–Tih(m)=0.5nsG61
ApplicationReport
SPRA533
TMS320C6000EMIFtoExternalSBSRAMInterface22
CompleteExampleUsing’C6201B
Thissectionwalksthroughtheregisterconfigurationforinterfacingthe‘C6201Bwith
SBSRAMathalfspeed.BecausenoSBSRAMparametersdirectlytietheEMIFsettings
toaspecificSBSRAM,thissoftwareexampleisgenerictoanySBSRAMdevice.
Ifasingle32-or36-bit-wideSBSRAMisused,theblockdiagramfortheinterface
schematicisidenticaltothatshowninFigure1.Iftwo18-bit-widedevicesareusedin
parallel,theschematicisidenticaltoFigure2.
Assumptions
G72CLKOUT1frequencyof200MHz
G72100-MHzSBSRAMclockfrequency
(SSCLK=?xCLKOUT1frequency)
G72SBSRAMtobelocatedatCE2(logicaladdress0x02000000)
G72CLKOUT1isnotusedinthesystem.
G72SDCLK,CLKOUT2isusedinthesystems.
RegisterConfiguration
Table6.SDRAMRegisters
RegisterNameFieldsRequired
EMIFGlobalControlSDCEN,SSCEN,CLK1EN,CLK2EN,
SSCRT
EMIFCE2SpaceControlMTYPE
EMIFGlobalControlRegisters
BecausetheSBSRAMisdrivenbySSCLK,wemustsetthefollowing:
Figure22.EMIFGlobalControlRegisterDiagram
311413121109876543210
ReservedReservedRsv/ARDY/HOLD/HOLDANOHOLDSDCENSSCENCLK1ENCLK2ENSSCRTRBTR8MAP
011001101101001
SDCEN=1indicatesthatSDCLKisenabledtoclock,assumingitisinusebythe
system
SSCEN=1IndicatesthatSSCLKisenabledbecauseitdrivestheSBSRAMinterface
CLK1EN=0IndicatesthatCLKOUT1isdisabled,assumingitisNOTinusebythe
system
CLK2EN=1IndicatesthatCLKOUT2isenabled,assumingitisinusebythesystem
SSCRT=0Specifiesahalf-rateSBSRAMInterface
Thus,avalidsettingfortheEMIFglobalcontrolregisteris0x00003369.
ApplicationReport
SPRA533
TMS320C6000EMIFtoExternalSBSRAMInterface23
Foradditionalinformationontheremainderofthefields,seetheTITMS320C6000
PeripheralsReferenceGuide.
EMIFCE2SpaceControlRegister
Figure23.EMIFCE2SpaceControlRegisterDiagram
3128272221201916
WRITESETUPWRITESTROBEWRITEHOLDREADSETUP
1111111111111111
15141387643210
RsvREADSTROBERsvMTYPEReservedREADHOLD
1111111101000011
MTYPE=100indicatesthat32-bit-wideSBSRAMislocatedintheCE2addressspace.
TheotherfieldsareirrelevantbecausetheyrefertoasynchronousmemoryandSBSRAM
isconfiguredforthisspace.
AvalidsettingforEMIFCE2SpaceControlis0xFFFFFF43.
CodeSegment
ThefollowingcodesegmentsetsuptheEMIFasdescribedaboveusingthe
TMS320C6000PeripheralRuntimeSupportControlLibrary.
#include
.
./OTHERUSERCODE/
.
/GetdefaultvaluesforallEMIFregisters/
unsignedintg_ctrl=GET_REG(EMIF_GCTRL);
unsignedintce0_ctrl=GET_REG(EMIF_CE0_CTRL);
unsignedintce1_ctrl=GET_REG(EMIF_CE1_CTRL);
unsignedintce2_ctrl=GET_REG(EMIF_CE2_CTRL);
unsignedintce3_ctrl=GET_REG(EMIF_CE3_CTRL);
unsignedintsdram_ctrl=GET_REG(EMIF_SDRAM_CTRL);
unsignedintsdram_ref=GET_REG(EMIF_SDRAM_REF);
/SetGlobalControl-EnableCLKOUT2,SDCLK,andSSCLK/
/-DisableCLKOUT1/
/-Setfor?xSBSRAMinterface/
RESET_BIT(&g_ctrl,SSCRT);
SET_BIT(&g_ctrl,CLK2EN);
RESET_BIT(&g_ctrl,CLK1EN);
SET_BIT(&g_ctrl,SSCEN);
SET_BIT(&g_ctrl,SDCEN);
/ConfigureCE2asSBSRAM/
LOAD_FIELD(&ce2_ctrl,MTYPE_32SBSRAM,MTYPE,MTYPE_SZ);
/StoreEMIFControlRegisters/
emif_init(g_ctrl,ce0_ctrl,ce1_ctrl,ce2_ctrl,ce3_ctrl,
sdram_ctrl,sdram_ref);
.
./OTHERUSERCODE/
.
ApplicationReport
SPRA533
TMS320C6000EMIFtoExternalSBSRAMInterface24
References
TMS320C6201/6201BDigitalSignalProcessorsDataSheet,LiteratureNumber
SPRS051,TexasInstruments.
TMS320C6202Fixed-PointDigitalSignalProcessorDataSheet,LiteratureNumber
SPRS072,TexasInstruments.
TMS320C6211Fixed-PointDigitalSignalProcessorDataSheet,LiteratureNumber
SPRS073,TexasInstruments.
TMS320C6701Floating-PointDigitalSignalProcessorDataSheet,LiteratureNumber
SPRS067,TexasInstruments.
TMS320C6711Floating-PointDigitalSignalProcessorDataSheet,LiteratureNumber
SPRS088,TexasInstruments.
TMS320C6000PeripheralsReferenceGuide,LiteraturenumberSPRU190,Texas
Instruments.
TMS320C6000PeripheralSupportLibraryProgrammersReference,Literaturenumber
SPRU273,TexasInstruments.
MT58L128L32PDataSheet,MicronTechnology,Inc.
MT58L512L18DDataSheet,MicronTechnology,Inc.
MT58LC64K32D9DataSheet,MicronTechnology,Inc.
ApplicationReport
SPRA533
TMS320C6000EMIFtoExternalSBSRAMInterface25
TIContactNumbers
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ApplicationReport
SPRA533
TMS320C6000EMIFtoExternalSBSRAMInterface26
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