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TABLEOFCONTENTS:

1.I2CInterfaceorTWI(TwoWireInterface)

2.WorkingofTWI

3.TWIDetails

I2CInterfaceorTWI(TwoWireInterface)

WorkingofTWOwiredinterface:

BothTWIlinesSDAandSDCarebi-directional

thereforeoutputsconnectedtotheTWIareopen

collectortypesoeachlineisconnectedtoavoltage

supplyviaPullupresistor.Pullingthelinestothe

groundisconsideredalogicalzerowhilelettingit

floatisconsideredaslogical‘1’.Whenidle,both

linesarehigh.Tostartatransaction,SDAispulledlowwhileSCLremainshigh.ReleasingSDAtofloathigh

againwouldbeastopmarker,signalingtheendofabustransaction.

Theonlyexternalhardwareneededtoimplementthebusisasinglepull-upresistorforeachoftheTWIbuslines.

Alldevicesconnectedtothebushaveuniqueaddress.TheTWIbusisamulti-masterbuswhereoneormore

devices,capableoftakingcontrolofthebus,canbeconnected.Themastersuppliestheclock;itinitiatesand

terminatestransactionsandtheintendedslave(basedupontheaddressprovidedbythemaster)acknowledges

themasterbydrivingorreleasingthebus.Theslavecannotterminatethetransactionbutcanindicateadesireto

stoporterminatebya“NAK”ornot-acknowledge.Addressingopensthelinesofcommunicationbetweenthe

masteranditsintendedslavedeviceandthemasterkeepstheconnectionopenuntilitwishestoterminatethe

connection(whenthemasterisfinishedwiththeslave).

ThemodeofoperationwhetheradevicewillactasamasterorasaslaveisdistinguishedbytheTWIstatus

codesintheTWIStatusRegister(TWSR)andbytheuseofcertainbitsintheTWIControlRegister(TWCR).The

statuscodesaredividedinMasterandSlavecodesandfurtherinreceiveandtransmitrelatedcodes.Status

codesforBusErrorandIdlealsoexist.Thestatuscodesaredividedintofourgroups:MasterTransmitterMode

(MT),MasterReceiverMode(MR),SlaveTransmitterMode(ST)andSlaveReceiverMode(SR).

Oncedecidedwhichdevicewillactasmasterthedatatransmissiontakesplace.OnlyMasterdevicescandrive

boththeSCLandSDAlineswhileaSlavedeviceisonlyallowedtoissuedataontheSDAline.Datatransferis

alwaysinitiatedbyaBusMasterdevice.

AhightolowtransitionontheSDAlinewhileSCLishighisdefinedtobeaSTARTconditionorarepeatedstart

condition.

ASTARTconditionisalwaysfollowedbythe(unique)7-bitslaveaddressesandthenbyaDataDirectionbit.TheSlave

deviceaddressednowacknowledgestotheMasterbyholdingSDAlowforoneclockcycle.IftheMasterdoesnotreceive

TUT007

anyacknowledgementthetransferisterminated.DependingoftheDataDirectionbit,theMasterorSlavenowtransmits

8-bitofdataontheSDAline.Thereceivingdevicethenacknowledgesthedata.Multiplebytescanbetransferredinone

directionbeforearepeatedSTARToraSTOPconditionisissuedbytheMaster.Thetransferisterminatedwhenthe

MasterissuesaSTOPcondition.ASTOPconditionisdefinedbyalowtohightransitionontheSDAlinewhiletheSCLis

high.IfaSlavedevicecannothandleincomingdatauntilithasperformedsomeotherfunction,itcanholdSCLlowto

forcetheMasterintoawait-state.AlldatapacketstransmittedontheTWIbusare9bitslong,consistingofonedatabyte

andanacknowledgebit.Themasterorthecontrolunitincludestheclock,Data/AddressRegister,aSTARTandSTOP

controllerandarbitrationdetectionwhilethereceiverisresponsibleforacknowledgingthereception.TheAddressMatch

unitisonlyusedinslavemode,andchecksifthereceivedaddressbytesmatchthe7-bitaddressintheTWIAddress

Register(TWAR).Uponanaddressmatch,theControlUnitisinformed,allowingcorrectactiontobetaken.An

Acknowledge(ACK)issignaledbythereceiverpullingtheSDAlinelowduringtheSCLcycle.Ifthereceiverleavesthe

SDAlinehigh,aNACKissignaled.Duringdatatransferthetwowiredataregistercontainstheaddressordatabytesto

betransmittedorreceived.InadditionitalsocontainsaregistercontainingtheACK/NON-ACKbittobetransmittedor

received.



TheSTART/STOPControllerisresponsibleforgenerationanddetectionofSTART,REPEATEDSTART,and

STOPconditions.TheSTART/STOPcontrollerisabletodetectSTARTandSTOPconditionsevenwhentheMCU

isinoneofthesleepmodes,enablingtheMCUtowakeupifaddressedbyaMaster.IftheTWIhasinitiateda

transmissionasMaster,theArbitrationDetectionhardwarecontinuouslymonitorsthetransmissiontryingto

determineifarbitrationisinprocessbysynchronizingwithAddressmatchunit.Arbitrationisatechniquewhich

allowstoensurethatnotwomicrocontrollerstriestosenddataatthesametime.IftheTWIhaslostarbitration,

theControlUnitisinformed.Correctactioncanthenbetakenandappropriatestatuscodesgenerated.

AstheTWIbusisamultimasterbus,it’spossiblethattwodevicesinitiateatransferattheexactsametime.

Arbitrationiscarriedoutthroughthenextstagesofthetransaction,andthefirstdeviceattemptingtotransmita

logical‘1’whileanotherdevicetransmits‘0’willlosearbitration.Thiscanduetothephysicalcharacteristicsofthe

buseasilybedetected.Ifonedevicepullsalinelow,theotherscannottransmithigh.Whenadevicehaslost

arbitration,itmuststoptransmittingandwaituntilthenextSTOPconditionbeforetryingtotakecontrolofthebus

again.

TIMINGDIAGRAM

DatatransferisinitiatedwiththeSTARTbit(S)whenSDAispulledlowwhileSCLstayshigh.Then,SDAsets

thetransferredbitwhileSCLislow(blue)andthedataissampled(received)whenSCLrises(green).Whenthe

transferiscomplete,aSTOPbit(P)issentbyreleasingthedatalinetoallowittobepulledupwhileSCLis

constantlyhigh.Inordertoavoidfalsemarkerdetection,thelevelonSDAischangedonthenegativeedgeandis

capturedonthepositiveedgeofSCL.