Verilog-2001BehavioralandSynthesisEnhancements
CliffordE.Cummings
cliffc@sunburst-design.com/www.sunburst-design.com
SunburstDesign,Inc.
14314SWAllenBlvd.
PMB501
Beaverton,OR97005
ABSTRACT
TheVerilog-2001Standardincludesanumberofenhancementsthataretargetedatsimplifying
designs,improvingdesignsandreducingdesignerrors.
ThispaperdetailsimportantenhancementsthatwereaddedtotheVerilog-2001Standardthatare
intendedtosimplifybehavioralmodelingandtoimprovesynthesisaccuracyandefficiency.
InformationisprovidedtoexplainthereasonsbehindtheVerilog-2001Standardenhancement
implementations..
Revised-April2002
ImportantcorrectiontoANSI
styleparameterlistsaddedto
thisrevision
HDLCON2001Verilog-2001Behavioraland
Rev1.3SynthesisEnhancements
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1.0Introduction
Forthepastfiveyears,experiencedengineersandrepresentativesofEDAvendorshavewrestled
todefineenhancementstotheVeriloglanguagethatwillofferincreaseddesignproductivity,
enhancedsynthesiscapabilityandimprovedverificationefficiency.
Theguidingprinciplesbehindproposedenhancementsincluded:
1.donotbreakexistingdesigns,
2.donotimpactsimulatorperformance,
3.makethelanguagemorepowerfulandeasiertouse.
Thispaperdetailsmanyofthebehavioralandsynthesisenhancementsthatwereaddedtothe
Verilog-2001Standard[1],includingsomeoftherationalthatwentintodefiningtheadded
enhancements.Thispaperwillalsodiscussafewerrataandcorrectionstotheyetunpublished
2001VerilogStandard.
Immediatelyaftertheheaderforeachenhancement,Imakepredictionsonwhenyouwilllikely
seeeachenhancementactuallyimplementedbyEDAvendors.
1.1GlossaryofTerms
TheVerilogStandardsGroupusedasetoftermsandabbreviationstohelpconciselydescribe
currentandproposedVerilogfunctionality.Manyofthosetermsareusedinthispaperandare
thereforedefinedbelow:
?ASIC-ApplicationSpecificIntegratedCircuit
?EDA-ElectronicDesignAutomation.
?HDLCON-InternationalHDLConference.
?IP-IntellectualProperty(notinternetprotocol).
?IVC-InternationalVerilogConference-precursortoHDLCONwhentheSpringVIUF
andIVCconferencesmerged.
?LHS-LeftHandSideofanassignment.
?LSB-LeastSignificantBit.
?MSB-MostSignificantBit.
?PLI-thestandardVerilogProgrammingLanguageInterface
?RHS-RightHandSideofanassignment.
?RTL-RegisterTransferLevelorthesynthesizablesubsetoftheVeriloglanguage.
?VHDL-VHSICHardwareDescriptionLanguage.
?VHSIC-VeryHighSpeedIntegratedCircuitsprogram,fundedbytheDepartmentof
Defenseinthelate1970''sandearly1980''s[2].
?VIUF-VHDLInternationalUsersForum-theSpringVIUFconferencewasaprecursorto
HDLCONwhentheSpringVIUFandIVCconferencesmerged.
?VSG-VerilogStandardsGroup.
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2.0WhatBrokeinVerilog-2001?
WhileproposingenhancementstotheVeriloglanguage,theprimedirectiveoftheVerilog
StandardsGroupwastonotbreakanyexistingcode.ThereareonlytwoVerilog-2001behavioral
enhancementproposalsthatpotentiallybreakexistingdesigns.Thesetwoenhancementsare
describedbelow.
2.131openfiles
Verilog-1995[3]permitteduserstoopenupto31filesforwriting.ThefilehandleforVerilog-
1995-stylefilesiscalledanMCD(Multi-ChannelDescriptor)whereeachopenfileisrepresented
byonebitsetinaninteger.Onlythe31MSBsoftheintegercouldbesetforopenfilessincebit0
representedthestandardoutput(STDOUT)terminal.Theintegeridentifier-namewasthefile
handleusedintheVerilogcode.
MCDscouldbebit-wiseor''edtogetherintoanotherintegerwithmultiplebitssettorepresent
multipleopenfiles.UsinganMCDwithmultiplevalidbitsset,adesignercanaccessmultiple
openfileswithasinglecommand.
Inrecentyears,engineershavefoundreasonstoaccessmorethan31fileswhiledoingdesign
verification.The31open-filelimitwastoorestrictive.
Atthesametime,engineersweredemandingbetterfileI/Ocapabilities,sobothproblemswere
addressedinasingleenhancement.ThefileI/Oenhancementrequirestheuseoftheinteger-MSB
toindicatethatthenewfileI/Oenhancementisinuse.Whentheinteger-MSBisa"0",thefilein
useisaVerilog-1995-stylefilewithmulti-channeldescriptorcapability.Whentheinteger-MSBis
a"1",thefileinuseisaVerilog-2001-stylefilewhereitisnowpossibletohave231openfiles
atatime,eachwithauniquebinarynumberfile-handlerepresentation(multi-channeldescriptors
arenotpossiblewiththenewfileI/O-stylefiles.
Anyexistingdesignthatcurrentlyusesexactly31openfileswillbreakusingVerilog-2001.The
fixistousethenewfileI/Ocapabilityforatleastoneofthecurrent31openfiles.Itwas
necessarytostealtheintegerMSBtoenhancethefileI/OcapabilitiesofVerilog.
2.2`bzassignment
Verilog-1995andearlierhasapeculiar,notwidelyknown"feature"(documented-bug!)that
permitsassignmentsliketheoneshownbelowinExample1toassignupto32bitsof"Z"withall
remainingMSBsbeingsetto"0".
assigndatabus=en?dout:''bz;
Example1-Simplecontinuousassignmentusing''bztodoz-expansion
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IfthedatabusinExample1is32bitswideorsmaller,thiscodingstyleworksfine.Ifthedatabus
islargerthan32bitswide,thelowerbitsaresetto"Z"whiletheupperbitsareallsetto"0".All
synthesistoolssynthesizethiscodeto32tri-statedriversandallupperbitsarereplacedwithand-
gatessothatiftheeninputislow,theand-gateoutputsalsodrive"0"s.
ThecorrectVerilog-1995parameterizedmodelforatri-statedriverofanysizeisshownExample
2:
moduletribuf(y,a,en);
parameterSIZE=64;
output[SIZE-1:0]y;
input[SIZE-1:0]a;
inputen;
assigny=en?a:{SIZE{1''bz}};
endmodule
Example2-SynthesizbleandparameterizableVerilog-1995three-statebuffermodel
InVerilog-2001,makingassignmentsof''bzor''bxwillrespectivelyz-extendorx-extendthefull
widthoftheLHSvariable.
TheVSGdeterminedthatanyengineerthatintentionallymade''bzassignments,intendingtodrive
32bitsof"Z"andallremainingMSBsto"0"deservedtohavetheircodebroken!Anengineer
couldeasilymakeanassignmentof32''bzwherevertheexistingbehaviorisdesiredandthe
assignmentwilleithertruncateunusedZ-bitsoraddleadingzerostotheMSBpositionstofilla
largerLHSvalue.
2.3Minimalrisk
TheVSGdecidedthattherewouldbeminimalimpactfromthefileI/Oenhancementthatcould
notbeeasilysolvedusingthenewVerilog-2001fileI/Oenhancement,andthe''bzassignment
enhancementisnotlikelytoappearinthecodeofanyreasonablyproficientVerilogdesigner,plus
thereisaneasywork-aroundforthe''bzfunctionalityiftheexistingsillybehaviorisactually
desired!
3.0LRMErrors
Unfortunately,addingnewfunctionalitytotheVeriloglanguagealsorequiredtheadditionofnew
anduntesteddescriptionstotheIEEEVerilogStandarddocumentation.Untiltheenhanced
functionalityisimplemented,theaddeddescriptionsareunprovenandmightbeshortonintended
enhancementfunctionalitydetail.Whatcornercasesarenotaccuratelydescribed?TheVSGcould
notcompiletheexamplessotheremightbesyntaxerrorsinthenewerexamples.
OneexampleofanerrorthatwentunnoticedinthenewIEEEVerilog-2001Standardisthe
Verilogcodeforafunctionthatcalculatesthe"ceilingofthelog-base2"ofanumber.This
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example,giveninsection10.3.5,makesuseofconstantfunctions.Theclogb2functiondescribed
intheexamplefromtheIEEEVerilogStandard,duplicatedbelow,hasafewnotableerrors:
//definetheclogb2function
functionintegerclogb2;
inputdepth;
integeri,result;
begin
for(i=0;2i
result=i+1;
clogb2=result;
end
endfunction
Example3-Verilog-2001Standardconstantfunctionexamplefromsection10witherrors
Errorsinthismodelinclude:
(1)theinput"depth"tothefunctioninthisexampleisonlyonebitwideandshouldhave
includedamulti-bitdeclaration.
(2)theresultisnotinitialized.Ifthedepthissetto"1",thefor-loopwillnotexecuteandthe
functionwillreturnanunknownvalue.
AsimpleandworkingreplacementforthismodulethatevenworkswithVerilog-1995isshownin
Example4:
functionintegerclogb2;
input[31:0]value;
for(clogb2=0;value>0;clogb2=clogb2+1)
value=value>>1;
endfunction
Example4-Workingfunctiontocalculatetheceilingofthelog-base-2ofanumber
4.0TopFiveEnhancements
Ata"BirdsOfaFeather"sessionattheInternationalVerilogConference(IVC)in1996,
IndependentConsultantKurtBatymoderatedanafter-hourspaneltosolicitenhancementideas
forfutureenhancementstotheVerilogstandard.
Panelistsandaudiencememberssubmittedenhancementideasandtheentiregroupvotedforthe
top-fiveenhancementsthattheywouldliketoseeaddedtotheVeriloglanguage.Thesetop-five
enhancementsgavefocustotheVSGtoenhancetheVeriloglanguage.
AlthoughnumerousenhancementswereconsideredandmanyenhancementsaddedtotheVerilog
2001Standard,thetop-fivereceivedthemostattentionfromthestandardsgroupandallfive
wereaddedinoneformoranother.Thetop-fiveenhancementsagreedtobytheaudienceand
panelwere:
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#1-Veriloggeneratestatement
#2-Multi-dimensionalarrays
#3-BetterVerilogfileI/O
#4-Re-entranttasks
#5-Betterconfigurationcontrol
ManyenhancementstotheVeriloglanguagewereinspiredbysimilarorequivalentcapabilities
thatalreadyexistedinVHDL.ManyVerilogdesignershaveatonetimeoranotherdoneVHDL
design.AnyVHDLcapabilitythatwepersonallyliked,wetriedaddingtoVerilog.Anythingthat
wedidnotlikeaboutVHDLwechosenottoaddtoVerilog.
4.1Multi-DimensionalArrays
Expectedtobesynthesizable?Yes.ThiscapabilityisalreadysynthesizableinVHDLandis
neededforVerilogIPdevelopment.
When?Soon!
Beforedescribingthegeneratestatement,itislogicaltodescribethemulti-dimensionalarray
enhancement,thatisessentiallyrequiredtoenablethepowerofgeneratestatements.
Multidimensionalarraysareintendedtobesynthesizableandmostvendorswilllikelyhavethis
capabilityimplementedaroundthetimethattheVerilog2001LRMbecomesanofficialIEEE
Standard.
InVerilog-1995,itwaspossibletodeclareregistervariablearrayswithtwodimensions.Two
noteworthyrestrictionswerethatnettypescouldnotbedeclaredasarraysandonlyonefull
array-wordcouldbereferenced,nottheindividualbitswithintheword.
InVerilog-2001,netandregister-variabledatatypescanbeusedtodeclarearraysandthearrays
canbemultidimensional.Accesswillalsobepossibletoeitherfullarraywordsortobitorpart
selectsofasingleword.
InVerilog-2001,itshallstillbeillegaltoreferenceagroupofarrayelementsgreaterthanasingle
word;hence,onestillcannotinitializeapartialorentirearraybyreferencingthearraybythearray
nameorbyasubsetoftheindexranges.Two-dimensionalarrayelementsmustbeaccessedby
oneortwoindexvariables,Threedimensionalarrayelementsmustbeaccessedbytwoorthree
indexvariables,etc.
InExample5,astructuralmodelofadual-pipelinemodelwithone2-bitdatainputisfannedout
intotwo2-bitby3-deeppipelinestagesandtwo2-bitdataoutputsaredrivenbythetwo
respectivepipelineoutputs.Theflip-flopsinthemodelhavebeenwiredtogetherusinga3-
dimensionalnetarraycalleddata.Thedata-word-widthislistedbeforetheidentifierdata,andthe
othertwodimensionsareplacedaftertheidentifierdata.
Theconnectionsbetweenflip-flopsaremadeusingallthreedimensionstoindicatewhich
individualnetsareattachedtotheflip-flopdatainputandoutput,whileconnectionstotheports
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aredoneusingonlytwodimensionstotiethe2-bitbusestothe2-bitdatainputandoutputports
ofthemodel.
moduledualpipe_v2k(dout1,dout0,din,en,clk,rst_n);
output[1:0]dout1,dout0;
input[1:0]din,en;
inputclk,rst_n;
wire[1:0]data[1:0][3:0];
assigndata[1][0]=din;
assigndata[0][0]=din;
dffu000(.q(data[0][1][0]),.d(data[0][0][0]),.clk(clk),.en(en[0]),.rst_n(rst_n));
dffu010(.q(data[0][2][0]),.d(data[0][1][0]),.clk(clk),.en(en[0]),.rst_n(rst_n));
dffu020(.q(data[0][3][0]),.d(data[0][2][0]),.clk(clk),.en(en[0]),.rst_n(rst_n));
dffu001(.q(data[0][1][1]),.d(data[0][0][1]),.clk(clk),.en(en[0]),.rst_n(rst_n));
dffu011(.q(data[0][2][1]),.d(data[0][1][1]),.clk(clk),.en(en[0]),.rst_n(rst_n));
dffu021(.q(data[0][3][1]),.d(data[0][2][1]),.clk(clk),.en(en[0]),.rst_n(rst_n));
dffu100(.q(data[1][1][0]),.d(data[1][0][0]),.clk(clk),.en(en[1]),.rst_n(rst_n));
dffu110(.q(data[1][2][0]),.d(data[1][1][0]),.clk(clk),.en(en[1]),.rst_n(rst_n));
dffu120(.q(data[1][3][0]),.d(data[1][2][0]),.clk(clk),.en(en[1]),.rst_n(rst_n));
dffu101(.q(data[1][1][1]),.d(data[1][0][1]),.clk(clk),.en(en[1]),.rst_n(rst_n));
dffu111(.q(data[1][2][1]),.d(data[1][1][1]),.clk(clk),.en(en[1]),.rst_n(rst_n));
dffu121(.q(data[1][3][1]),.d(data[1][2][1]),.clk(clk),.en(en[1]),.rst_n(rst_n));
assigndout1=data[1][3];
assigndout0=data[0][3];
endmodule
Example5-Verilog-2001structuraldual-pipelinemodelusingmultidimensionalwirearraysforconnections
4.2TheVerilogGenerateStatement
Expectedtobesynthesizable?Yes
When?Soon.
InspiredbytheVHDLgeneratestatement,theVeriloggeneratestatementextendsgenerate-
statementcapabilitiesbeyondthoseoftheVHDL-1993generatestatement.
InVHDLthereisafor-generate(for-loopgenerate)andanif-generatestatement.InVerilog-
2001therewillbeafor-loopgeneratestatement,anif-elsegeneratestatementandacasegenerate
statement.
4.3Thegenvarindexvariable
Aftermuchdebate,theVSGdecidedtoimplementanewindexvariabledatatypethatcanonlybe
usedwithgeneratestatements.Thekeywordforthegenerate-indexvariableis"genvar."This
variabletypeisonlyusedduringtheevaluationofgeneratedinstantiationsandshallnotbe
referencedbyotherstatementsduringsimulation.TheVSGfeltitwassafesttodefineanew
variabletypewithrestrictiveusagerequirementsasopposedtoimposingrulesonintegerswhen
usedinthecontextofageneratestatement.
3-dimensionalwire-array
Wordassignment-
twoindexvariables
Bitassignment-threeindex
variables
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PertheIEEEVerilog-2001DraftStandard,aVeriloggenvarmustadheretothefollowing
restrictions:
?Genvarsshallbedeclaredwithinthemodulewherethegenvarsareused.
?Genvarscanbedeclaredeitherinsideoroutsideofageneratescope.
?Genvarsarepositiveintegersthatarelocalto,andshallonlybeusedwithinagenerateloop
thatusesthemasindexvariables.
?Genvarsareonlydefinedduringtheevaluationofthegenerateblocks.
?GenvarsdonotexistduringsimulationofaVerilogdesign.
?Genvarvaluesshallonlybedefinedbygenerateloops.
?Twogenerateloopsusingthesamegenvarasanindexvariableshallnotbenested.
?Thevalueofagenvarcanbereferencedinanycontextwherethevalueofaparameter
couldbereferenced.
TheVeriloggeneratefor-loop,liketheVerilogproceduralfor-loop,doesnotrequirea
contiguousloop-rangeandcanthereforebeusedtogeneratesparsematricesofinstancesthat
mightproveusefultoDSPrelateddesigns.
TheVerilogif-elsegeneratestatementcanbeusedtoconditionallyinstantiatemodules,
proceduralblocks,continuousassignmentsorprimitives.
TheVerilogcasegeneratestatementwasaddedtoenhancethedevelopmentofIP.Perhapsa
modelcouldbewrittenforamultiplierIPthatchoosesanimplementationbasedonthewidthof
themultiplieroperands.Smallmultipliersmightbeimplementedbestoneortwodifferentways
butlargemultipliersmightbeimplementedbetteranotherway.Perhapsthemultipliermodel
couldchoseadifferentimplementationbasedonpower_usageparameterspassedtothemodel.
AFIFOmodelmightbecreatedthatinfersadifferentimplementationsbasedonwhetherthe
modelusessynchronousorasynchronousclocks.
4.4EnhancedFileI/O
Expectedtobesynthesizable?No
When?Soon.
Veriloghasalwayshadreasonablefile-writingcapabilitiesbutitonlyhasverylimitedbuilt-infile-
readingcapabilities.
StandardVerilog-1995filereadingcapabilitieswerelimitedtoreadingbinaryorhexdatafroma
fileintoapre-declaredVerilogarrayandthenextractingthedatafromthearrayusingVerilog
commandstomakeassignmentselsewhereinthedesignortestbench.
Verilog-1995fileI/OcanbeenhancedthroughthePLIandthemostpopularpackageusedto
enhanceVerilogfileI/OisthepackagemaintainedbyChrisSpearonhiswebsite[4].AnyVerilog
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simulatorwithbuilt-instandardPLIcanbecompiledtotakeadvantageofmostoftheVerilog-
2001fileI/Oenhancementstoday.
Chris''fileI/OPLIcodewasthestartingpointforVerilog-2001fileI/Oenhancements,andsince
ChrishasalreadydonemostoftheworkofenhancingfileI/O,itislikelythatmostVerilog
vendorswillleverageoffofChris''worktoimplementthenewfileI/Oenhancements.
4.5Re-entrantTasksandFunctions
Expectedtobesynthesizable?Maybe?
When?Probablynotsoon.
VerilogfunctionsaresynthesizabletodayandVerilogtasksaresynthesizableaslongasthereare
notimingcontrolsinthebodyofthetask,suchas@(posedgeclk).The#delayconstructis
ignoredbysynthesistools.
ThisenhancementmightbeoneofthelastenhancementstobeimplementedbymostVerilog
vendors.MostexistingVerilogvendorshavecomplainedthatthisenhancementisadeparture
fromtheall-staticvariablesthatcurrentlyareimplementedintheVeriloglanguage.Automatic
tasksandfunctionswillrequirethatvendorspushthecurrentvaluesoftaskvariablesontoastack
andpopthemoffwhenthearecursivelyexecutingtaskinvocationcompletes.Vendorsare
wrestlingwithhowtheyintendtoimplementthisfunctionality.
Thisenhancementisespeciallyimportanttoverificationengineerswhousetaskswithtiming
controlstoapplystimulustoadesign.UnknowntomanyVerilogusers,Verilog-1995tasksuse
staticvariables,whichmeansthatifaverificationtaskiscalledasecondtimebeforethefirsttask
callisstillrunning,theywillusethesamestaticvariables,mostlikelycausingproblemsinthe
testbench.Thecurrentwork-aroundistoplacethetaskintoaseparateverificationmoduleand
instantiatethemodulemultipletimesinthetestbench,eachwithauniqueinstancename,sothat
thetaskcanbecalledmultipletimesusinghierarchicalreferencestotheinstantiatedtasks.
Byaddingthekeyword"automatic"afterthekeyword"task,"Verilogcompilerswilltreatthe
variablesinsideofthetaskasuniquestackedvariables.
Whataboutsynthesis?Tektronix,Inc.ofBeavertonOregonhashadanin-housesynthesistool
thatwasfirstusedtodesignASICsstartinginthelate1980''s,andthattoolhashadthecapability
tosynthesizerecursiveblocksofcodealsosincethelate1980s.Therecursivecapabilitiesmade
certainDSPblocksveryeasytocode.Somecreativesynthesisvendormightfindsomevery
usefulabilitiesbypermittingrecursiveRTLcoding;however,itisnotlikelythatrecursivetasks
willbesynthesizableinthenearfuture.
4.6Configurations
Expectedtobesynthesizable?Yes,Synthesistoolsshouldbecapableofreading
configurationfilestoextractthefilesneedtobeincludedintoasynthesizeddesign.
When?Thiscouldbeimplementedsoon.
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Configurationfileswillmakeitpossibletocreateaseparatefilethatcanmaptheinstancesofa
sourcefiletospecificfilesaslongasthefilescanbeaccessedwithaUNIX-likepathname.This
enhancementshouldremovetheneedtoemploy`uselibdirectivesinthesourcemodeltochange
thesourcefilesthatareusedtosimulatespecificinstanceswithinadesign.
The`uselibdirectivehasneverbeenstandardizedbecauseitrequiresadesignertomodifythe
sourcemodelstoadddirectivestocallspecificfilestobecompiledforspecificinstances.
Modifyingthesourcefilestosatisfythefilemappingrequirementsofasimulationrunisabad
ideaandtheVSGhopesthatusageofthe`uselibdirectiveswilleventuallycease.The
configurationfilealsooffersanelegantreplacementforthecommoncommandlineswitches:-y,
-vand+libext+.v,etc.Thesenon-standardcommandlineswitchesshouldalsoslowlybereplaced
withthemorepowerfulVerilog-2001configurationfiles.
5.0MoreVerilogEnhancements
Inadditiontothetop-fiveenhancementrequests,theVSGconsideredandaddedotherpowerful
andusefulenhancementstotheVeriloglanguage.Manyoftheseenhancementsaredescribed
below.
5.1ANSI-Cstyleportdeclarations
Expectedtobesynthesizable?Yes.
When?Almostimmediately.
Verilog-1995requiresallmoduleheaderportstobedeclaredtwoorthreetimes,dependingon
thedatatypeusedfortheport.ConsiderthesimpleVerilog-1995compliantexampleofasimple
flip-flopwithasynchronouslow-truereset,asshowninExample6.
moduledffarn(q,d,clk,rst_n);
outputq;
inputd,clk,rst_n;
regq;
always@(posedgeclkornegedgerst_n)
if(!rst_n)q<=1''b0;
elseq<=d;
endmodule
Example6-Verilog-1995D-flip-flopmodelwithverboseportdeclarations
TheVerilog-1995modelrequiresthatthe"q"outputbedeclaredthreetimes,onceinthemodule
headerportlist,onceinanoutputportdeclarationandonceinaregdata-typedeclaration.The
Verilog-2001Standardcombinestheheaderportlistdeclaration,portdirectiondeclarationand
data-typedeclarationintoasingledeclarationasshowninExample7,patternedafterANSI-C
styleports.Declaringall1-bitinputsaswiresisstilloptional.
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moduledffarn(
outputregq,
inputd,clk,rst_n);
always@(posedgeclkornegedgerst_n)
if(!rst_n)q<=1''b0;
elseq<=d;
endmodule
Example7-Verilog2001D-flip-flopmodelwithnew-styleportdeclarations
Thisenhancementisamorecompactwayofmakingportdeclarationsandshouldbeeasyto
implementforsimulationandsynthesissoon.
5.2Parameterpassingbyname(explicit&implicit)
Expectedtobesynthesizable?Yes.
When?Almostimmediately.
Verilog-1995standardizedtwowaystochangeparametersforinstantiatedmodules,(1)
parameterredefinitionand(2)defparamstatements.
(1)Parameterredefinitionisaccomplishedbyinstantiatingamoduleandadding#(new_value1,
new_value2,...)immediatelyafterthemodulename.
Advantage:thistechniqueinsuresthatallparametersarepassedtoamoduleatthesametimethat
themoduleisreferenced.
Disadvantage:allparametersmustbeexplicitlylisted,inthecorrectorder,uptoandincludingthe
parameter(s)thatarechanged.Forexample,ifamodulecontains10parameterdefinitions,andif
themoduleistobeinstantiatedrequiresthattheseventhparameterbechanged,theinstantiation
mustincludesevenparameterswithintheparentheses,listedinthecorrectorderandincludingthe
firstsixvalueseventhoughtheydidnotchangeforthisinstantiation.Itisnotpermittedtosimply
listsixcommasfollowedbythenewseventhparametervalue.
(2)Usingdefparamredefinitionisaccomplishedbyinstantiatingamoduleandincludingaseparate
defparamstatementtochangetheinstance_name.parameter_namevaluetoitsnewvalue.
Advantage:thistechniquegivesasimpleanddirectcorrespondencebetweentheinstance-name,
parameter-namepairandthenewvalue.
Disadvantage:defparamstatementscanappearanywhereintheVerilogsourcecodeandcan
changeanyparameteronanymodule.Translation-whencompilingaVerilogdesign,noneofthe
parametersinanymodulearefixeduntilthelastVerilogsourcefileisread,becausethelastfile
mighthierarchicallychangeeverysingleparameterinthedesign!A"grand-child"modulemight
changealloftheparametersofthe"grand-parent"module,whichmightpassnewparameter
valuestothe"parent/child"module.ItgetsuglyandprobablyslowsthecompilationofaVerilog
design.
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Verilog-2001addsasuperiorwayofpassingparameterstoinstantiatedmodules,usingnamed
parameterpassing,usingthesametechniqueasnamedportinstantiation.
Advantage#1:Onlytheparametersthatchangeneedtobereferencedinnamedport
instantiations.Thesameadvantagethatexistswhenusingdefparamstatements.
Advantage#2:Allparameterinformationisavailablewhenthemoduleinstantiationisparsedand
parametersarepasseddownthehierarchy;theydonotcauseside-effectsupthehierarchy.
ThisisthebestsolutionforIPdevelopmentandusage.
ThecurrentdefparamstatementwillnotbefullyusableinsomeVerilog-2001enhancementsand
theVSGhopesthattheadditionofnamedparameterredefinitionwilleventuallycausedefparam
statementusagetodie.
VendorsmightwanttoflagdefparamstatementsasVerilog-2001compilererrorswiththe
followingmessage:
"TheVerilogcompilerfoundadefparamstatementinthesourcecodeat(file-
line#).TousedefparamstatementsintheVerilogsourcecode,youmustincludethe
switch+Iamstupidonthecommandlinewhichwilldegradecompilerperformance.
Defparamstatementscanbereplacedwithnamedparameterredefinitionasdefineby
theVerilog-2001standard"
5.3SignedArithmetic
Expectedtobesynthesizable?Couldbe(?)
When?Synthesisvendordependent.
ThesignedarithmeticenhancementremovesafrequentcomplaintaboutVerilog,thatthedesign
hastoexplicitlycodesignedarithmeticfunctionalityintothemodel.
Anyvendorthatalreadyhandlessynthesisofsignedarithmeticoperationsshouldbeabletotake
advantageofthisenhancementtofacilitatesignedarithmeticdesigntasks.
5.4`ifndef&`elsif
Expectedtobesynthesizable?Yes.
When?Thiscouldbeimplementedsoon.
The`ifdef/`else/`endifconditionally-compiled-codecompilerdirectiveshavebeenapartofthe
VeriloglanguagesincebeforetheVerilog-1995Standard.Twoadditionshavebeenaddedtohelp
generateconditionallycompilecode:`ifndefand`elsif.
The`ifdefsetofcompilerdirectiveshavebeensynthesizablebymostsynthesistoolsforalong
timeandtheybecamesynthesizablebySynopsystoolsstartingwithSynopsysversion1998.02
(fullusagewithinSynopsystoolsrequiresthattheswitchhdlin_enable_vppbesettotrue).
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The`ifndefswitchaddsasmallsimplificationtoVerilogcodewheretheintentistocompilea
blockofcodeonlywhenaspecifictextmacrohasnotbeendefined.
`ifdefSYNTHESIS
`else
initial$display("RunningRTLModel");
`endif
Example8-Verilog-1995codingstyletoreplicatetheVerilog-2001`ifndefcapability
`ifndefSYNTHESIS
initial$display("RunningRTLModel");
`endif
Example9-UsingthenewVerilog-2001`ifndefcompilerdirective
Sincethe`ifndefand`elseifstatementsareusedtosimplydeterminewhencodeshouldbe
compiled,thesecompilerdirectivescouldeasilybeimplementedinbothsimulationandsynthesis
withoutmucheffort.
5.5ExponentialOperator
Expectedtobesynthesizable?Yes,iftheoperandsareconstants.
When?Thiscouldbeimplementedsoon.
The(exponential)operatorisastraightforwardwayofdeterminingsuchthingsasmemory
depth.Ifamodelhas10addressbits,itshouldhave1024memorylocations.
Ifthetwooperandsoftheoperatorareconstantsatcompile-time,thereisnoreasona
synthesistoolcouldnotcalculatethefinalvaluetobeusedduringsynthesis.
5.6LocalParameters
Expectedtobesynthesizable?Yes.
When?Thiscouldbeimplementedsoon.
Parameters,localtoamodule,thatcannotbechangedbyparameterredefinitionduring
instantiationisanotherenhancementtotheVerilog-2001Standard.Localparametersaredeclared
usingthekeywordlocalparam.
ThisenhancementisneededbyIPdeveloperswhowanttocreateaparameterizeddesignwhere
onlycertainnon-localparameterscanbemanuallychangedwhileotherlocalparametersare
manipulatedwithinadesignbasedontheparametersthatarepassedtoaparticulardesign
instance.RestrictingaccesstosomeparametershelpstoinsurethataIPuserscannot
inadvertentlysetincompatibleparametervaluesforaparticularmodule.Thememorymodelsin
Example10andExample11bothuselocalparameterstocalculateoneofthememoryparameters
basedonothermemoryparameters.
HDLCON2001Verilog-2001Behavioraland
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5.7Commaseparatedsensitivitylist
Expectedtobesynthesizable?Yes.
When?Almostimmediately.
Verilog-1995usesthekeyword"or"asaseparatorinthesensitivitylist.NewusersoftheVerilog
languageoftenaskthequestion,"canIuseandinthesensitivitylist?"Theanswerisno.
The"or"keywordismerelyaseparatorbetweensignalsinthesensitivitylistandnothingmore.
TheVerilogsensitivitylistisoneofthefewplaceswhereVerilogismoreverbosethanVHDL.I
personallyfoundthistobeoffensive!
VHDLseparatessignalsinthesensitivitylistwithacommacharacter,whichmostVerilogusers
wouldagreeisabetterseparatortoken.Forthisreason,thecommacharacterhasbeenaddedas
analternatewayofseparatingsignalsinaVerilogsensitivitylist.
Becausethisenhancementisreallyjustaparsingchange,itshouldbeveryeasytoimplement.
ThereisnoreasonthiscapabilityshouldnotbeavailablebyallVerilogvendorsassoonasthe
Verilog-2001StandardisreleasedbytheIEEE.
TheVerilogcodeforaparameterizedrammodelinExample10usesacomma-separated
sensitivitylistinthealwaysblockjusttwolinesbeforetheendmodulestatement.
//------------------------------------------
//ram1model-Verilog-2001@(a,b,c)
//requiresADDR_SIZE&DATA_SIZEparameters
//MEM_DEPTHisautomaticallysized
//------------------------------------------
moduleram1(addr,data,en,rw_n);
parameterADDR_SIZE=10;
parameterDATA_SIZE=8;
parameterMEM_DEPTH=1<
output[DATA_SIZE-1:0]data;
input[ADDR_SIZE-1:0]addr;
inputen,rw_n;
reg[DATA_SIZE-1:0]mem[0:MEM_DEPTH-1];
assigndata=(rw_n&&en)?mem[addr]:{DATA_SIZE{1''bz}};
always@(addr,data,rw_n,en)
if(!rw_n&&en)mem[addr]=data;
endmodule
Example10-ParameterizedVerilogrammodelwithcomma-separatedsensitivitylist
5.8@combinationalsensitivitylist
Expectedtobesynthesizable?Yes.
When?Almostimmediately.
TheVerilog-2001Standardreferstothe@operatorastheimpliciteventexpressionlist;
however,membersoftheVSGcalledthealways@keyword-pair,thecombinationallogic
HDLCON2001Verilog-2001Behavioraland
Rev1.3SynthesisEnhancements
15
sensitivitylistandthatwasitsprimaryintendedpurpose,tobeusedtomodelandsynthesize
combinationallogic.
Experiencedsynthesisengineersareawareoftheproblemsthatcanoccurifcombinationalalways
blocksarecodedwithmissingsensitivitylistentries.Synthesistoolsbuildcombinationallogic
strictlyfromtheequationsinsideofanalwaysblockbutthensynthesistoolscheckthesensitivity
listtowarntheuserofapotentialmismatchbetweenpre-synthesisandpost-synthesissimulations
[4].
Thealways@proceduralblockwilleliminatetheneedtolisteverysinglealways-blockinputin
thesensitivitylist.Thisenhancementwillreducetyping,andreducedesignerrors.Theintentwas
toreduceeffortwhencodingcombinationalsensitivitylistsandtoreduceopportunitiesforcoding
errorsthatcouldleadtoapre-synthesisandpost-synthesissimulationmismatch.
The@wasreallyintendedtobeusedatthetopofanalwaysblock,buttheVSGchosenotto
restrictitsusetojustthatlocation.TheVSGcouldnotthinkofagoodreasonnottouse,nordid
theVSGthinkitwaswisetorestrict,the@operatoronlytothetopofthealwaysblock.This
enhancementwasmadeorthogonalbutitshouldbeusedwithcautionandhasthepotentialtobe
abused.
TheVerilogcodeforaparameterizedrammodelinExample11usesan@sensitivitylistinthe
alwaysblockjusttwolinesbeforetheendmodulestatement.
//------------------------------------------
//ram1model-Verilog-2001
//requiresADDR_SIZE&DATA_SIZEparameters
//MEM_DEPTHisautomaticallysized
//------------------------------------------
moduleram1#(parameterADDR_SIZE=10,
parameterDATA_SIZE=8)
(output[DATA_SIZE-1:0]data,
input[ADDR_SIZE-1:0]addr,
inputen,rw_n);
localparamMEM_DEPTH=1<
reg[DATA_SIZE-1:0]mem[0:MEM_DEPTH-1];
//--------------------------------------------------
//Memoryreadoperation
//--------------------------------------------------
assigndata=(rw_n&&en)?mem[addr]:{DATA_SIZE{1''bz}};
//--------------------------------------------------
//Memorywriteoperation-modeledasalatch-array
//--------------------------------------------------
always@
if(!rw_n&&en)mem[addr]<=data;
endmodule
Example11-ParameterizedVerilogrammodelwith@combinationalsensitivitylist
TheVerilog-2001StandardnotesthatnetsandvariableswhichappearontheRHSof
assignments,infunctionandtaskcalls,orcaseexpressionsandifexpressionsshallallbeincluded
HDLCON2001Verilog-2001Behavioraland
Rev1.3SynthesisEnhancements
16
intheimplicitsensitivitylist.MissingfromtheVerilog-2001Standardisthefactthatvariableson
theLHSofanexpressionwhenusedasanindexrangeandvariablesusedincaseitemsshould
alsobeincludedintheimplicitsensitivitylist.Inthe3-to-8decoderwithoutputenableshownin
Example12,theeninputandthea-inputsshouldincludedinthe@impliedsensitivitylist.
moduledecoder(
outputreg[7:0]y,
input[2:0]a,
inputen);
always@begin
y=8''hff;
y[a]=!en;
end
endmodule
Example12-3-to-8Decodermodelusingthe@implicitsensitivitylist
5.9Constantfunctions
Expectedtobesynthesizable?Yes.
When?Thismighttakesometimetoimplement.
PerhapsthemostcontentiousenhancementtotheVerilog-2001Standard,theenhancementthat
raisedthemostdebateandthatwasalmostremovedfromthestandardonmultipleoccasionsin
thepastfiveyears,wastheconstantfunction.EDAvendorsopposedthisenhancementbecauseof
theperceiveddifficultyinefficientlyimplementingthisenhancement,anditspotentialimpacton
compile-timeperformance.
AquotefromanEDAvendorwhorequestedthatconstantfunctionsnotbeaddedtoVerilog
summarizessomeoftheopposition:
"ConstantfunctionsareanotherexampleofhowaVHDLconceptdoesnotmapwillintoVerilog
...TheVeriloglanguageissimplytoopowerfulandunrestrictedtosupportsuchfunctionality."
TheusersontheVSGalsorecognizethatconstantfunctionsmightnotonlybedifficultto
implement,butalsoimpactcompiletimes.Despitethispotentialimpactoncompile-time
performance,usersdeemedthisfunctionalitytooimportanttoomitfromtheVerilog-2001
Standard.Vendorsmightwanttopublicizethatadesignmodeledwithoutconstantfunctionswill
compilefasterthandesignsthatincludeconstantfunctions.
ConstantfunctionsareimportanttoIPdevelopers.Theobjectiveoftheconstantfunctionisto
permitanIPdevelopertoaddlocalparameterstoamodulethatarecalculatedfromother
parametersthatcouldbepassedintothemodulewheninstantiated.
Constantfunctionswillrequirevendorstocalculatesomeparametersatcompiletime,whichwill
requirethatsomeparametersnotbeimmediatelycalculatedwhenread,butthattheywillbe
calculatedafterafunctionisusedtodeterminetheactualvalueofaparameter.
HDLCON2001Verilog-2001Behavioraland
Rev1.3SynthesisEnhancements
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ConsidertheexampleofasimpleROMmodel.TomakeaparameterizedversionofaROM
model,weneedtoknowthenumberofaddressbits,numberofmemorylocationsandnumberof
databits.Thedatabuswidthshouldbepassedtothemodel,butonlythememorysizeornumber
ofaddressbitsshouldbepassedtothemodel.Ifwearegiventhenumberofaddressbits,we
shouldcalculatethememorydepthatcompiletime.Ifwearegiventhenumberofmemory
locations,weshouldbeabletocalculatehowmanyaddressbitsarerequiredatcompiletime.
InordertomakeconstantfunctionssomewhatmoreagreeabletoEDAvendors,theywere
definedwithsignificantrestrictionsincludingsomethatdonotapplytonormalVerilogfunctions.
Significantrestrictionsthatapplytoconstantfunctionsinclude:
?Constantfunctionsshallnotcontainhierarchicalreferences.
?Constantfunctionsaredefinedandinvokedinthesamemodule.
?Constantfunctionsshallignoresystemtasks.ThispermitsaregularVerilogfunctionwith
systemtaskssuchas$displaycommandstobechangedintoaconstantfunctionwithout
requiringremovalofthesystemtasks.
?Constantfunctionsshallnotpermitsystemfunctions.
?Constantfunctionsshallhavenosideeffects(theyshallnotmakeassignmentstovariables
thataredefinedoutsideoftheconstantfunction).
?Ifaconstantfunctionusesanexternalparameterwithintheinternalcalculationsofthe
function,theexternalparametermustbedeclaredbeforetheconstantfunctioncall.
?Allvariablesusedinaconstantfunctionthatarenotparametersorfunctionsmustbe
declaredlocallyintheconstantfunction.
?Iftheconstantfunctionusesaparameterthatisdirectlyorindirectlymodifiedbya
defparamstatement,thebehavioroftheVerilogcompilerisundefined.Thecompilercan
returnanunknownvalueoritcanissueasyntaxerror.
?Constantfunctionscannotbedefinedinsideofageneratestatement.
?Constantfunctionsshallnotcallotherconstantfunctionsinanycontextthatrequiresa
constantexpression.
TheVSGanticipatedthatthetypicaluseofaconstantfunctionwouldbetoperformsimple
calculationstogeneratelocalparameterstoinsurecompatibilitywithpassedparameters.The
aboverestrictionsinsurethatconstantfunctionsdonotcauseunduecompile-timeproblems.
5.10Attributes
Expectedtobesynthesizable?Partially.
When?AssoonastheIEEEsynthesiscommitteefinishesitsworkandincludesattributes
intothesynthesisspec.
Verilog-2001willaddanewconstruct(newtoVerilog)calledanattribute.Theattributeuses(
)tokens(named"funnybraces"bymembersoftheVSG)asshowninFigure1.
HDLCON2001Verilog-2001Behavioraland
Rev1.3SynthesisEnhancements
18
(attribute_name=constant_expression)
-or-
(attribute_name)
Figure1-Legalattributedefinitionsyntaxusing()
AttributeswereprimarilyaddedtotheVeriloglanguageenableothertoolstouseVerilogasan
inputlanguageandstillpassnon-Veriloginformationtothosetools.Formanyyearsnow,vendors
havebeenaddinghooksintotheVeriloglanguagebywayofsyntheticcomments.Themost
famous(infamous)exampleisthedeadly[6]syntheticcomment:
//synopsysfull_caseparallel_case
Thebiggestproblemwiththesyntheticcommentapproachisthatattachingtool-specific
informationtoaVerilogcommentforcesthosesametoolstoparseallVerilogcommentstoseeif
thecommentcontainsatool-specificdirective.
ToassistvendorswhouseVerilogasaninputlanguage,theVSGdecidedtoaddattributestothe
VeriloglanguagethatforthemostpartwillbeignoredbyVerilogcompilersthesameasany
Verilogcomment.Theattributespermitthird-partyvendorstoaddtool-relatedinformationtothe
sourcecodewithoutimpactingsimulationandwithouthavingtoparseeveryVerilogcomment.
5.11Requirednetdeclarations
Expectedtobesynthesizable?N/A.
When?Soon.
Verilog-1995hasanoddandnon-orthogonalrequirementthatall1-bitnets,drivenbya
continuousassignment,thatarenotdeclaredtobeaports,mustbedeclared.Itistheonly1-bit
nettypethatmustbedeclaredinVerilog.Thisnon-orthogonalrestrictionisremovedinVerilog-
2001.
moduleandor1(y,a,b,c);
outputy;
inputa,b,c;
wiren1;//notrequiredinVerilog-2001
assignn1=a&b;
assigny=n1|c;
endmodule
Example13-Verilog-1995requirednetdeclarationfortheLHSofacontinuousassignmenttoaninternalnet
5.12`default_nettypenone
Expectedtobesynthesizable?N/A.
When?Soon.
IntheVerilog-1995Standard,anyundeclaredidentifier,exceptfortheoutputofacontinuous
assignmentthatdrivesanon-portnet,isbydefaulta1-bitwire.Verilogneverrequiredthese1-bit
HDLCON2001Verilog-2001Behavioraland
Rev1.3SynthesisEnhancements
19
netdeclarationsandaddingthedeclarationstoamodelyieldednoadditionalcheckingtoinsure
thatall1-bitnetsweredeclared.
TheVerilog-2001Standardaddsanewoptiontothe`defult_nettypecompilerdirectivecalled
"none."Ifthe"none"optionisselected,all1-bitnetsmustbedeclared.
Whetherornotforcingall1-bitnetstobedeclaredisagoodcodingpracticeornotisopento
debate.Someengineersbelievethatallnetsshouldbedeclaredbeforetheyareused.Other
engineersfindthatdeclaringall1-bitnetscanbebothtimeandspace-consuming.
Editorialcomment:Ipersonallyfindthepracticeofdeclaringall1-bitnetstobeawasteoftime,
effortandlinesofcode.VHDLrequiresall1-bitnets(signals)tobedeclared,andonaVHDL
ASICdesignthatIworkedonin1996,whileinstantiatingandconnectingthemajorsub-blocks
andI/Opadsatthetop-levelmodelofanASICdesign,Ispentasmuchtimedebuggingflawed
signaldeclarationsasIdiddebuggingrealhardwareproblems.TheonlydeclarationsthatI
personallyfoundusefulweremulti-bitsignals(buses),whicharealsorequiredinVerilog-1995.
Mysignaldeclarationsextendedoverthreepagesofcodeandofferednoadditionaluseful
informationaboutthedesign.Nevertheless,onecannowinflictsimilarpainandsufferingintoa
Verilogdesignusingthe`default_nettypenonecompilerdirective.
6.0ArrayofInstance
Expectedtobesynthesizable?Yes.
When?Soon.
AnoteworthyenhancementtotheVeriloglanguageistheArrayofInstancethatwasaddedtothe
1995IEEEVerilogStandard.ThisenhancementwasimplementedbyCadencemorethantwo
yearsago,buttheothersimulationvendorsandallsynthesisvendorswereslowtofollow.
Anarrayofinstanceallowsansimpleone-dimensionallineararrayofinstancestobedeclaredina
singlestatement.
MostASICdesignersbuildatop-levelmodulethatonlypermitsinstantiationofothermodules,no
RTLcodeallowed.TheRTLcodeisusedinsub-modulesbutnotinthetop-levelmodule.
Inthetop-levelmodule,allofthemajorsub-blocksareinstantiatedalongwithalloftheASICI/O
pads.ConsiderthetaskofinstantiatingtheI/Opadsfora32-bitaddressbusanda16-bitdatabus.
Verilogengineershavealwaysbeenrequiredtomake32address-padand16data-pad
instantiationsinthetop-levelmodelasshowninExample14.
moduletop_pads1(pdata,paddr,pctl1,pctl2,pctl3,pclk);
inout[15:0]pdata;//paddatabus
input[31:0]paddr;//padaddrbus
inputpctl1,pctl2,pctl3,pclk;//padsignals
wire[15:0]data;//databus
wire[31:0]addr;//addrbus
main_blku1(.data(data),.addr(addr),
.sig1(ctl1),.sig2(ctl2),.sig3(ctl3),.clk(clk));
HDLCON2001Verilog-2001Behavioraland
Rev1.3SynthesisEnhancements
20
IBUFc4(.O(ctl3),.pI(pctl3));
IBUFc3(.O(ctl2),.pI(pctl2));
IBUFc2(.O(ctl1),.pI(pctl1));
IBUFc1(.O(clk),.pI(pclk));
IBUFi15(.O(data[15]),.pI(pdata[15]));
IBUFi14(.O(data[14]),.pI(pdata[14]));
IBUFi13(.O(data[13]),.pI(pdata[13]));
IBUFi12(.O(data[12]),.pI(pdata[12]));
IBUFi11(.O(data[11]),.pI(pdata[11]));
IBUFi10(.O(data[10]),.pI(pdata[10]));
IBUFi9(.O(data[9]),.pI(pdata[9]));
IBUFi8(.O(data[8]),.pI(pdata[8]));
IBUFi7(.O(data[7]),.pI(pdata[7]));
IBUFi6(.O(data[6]),.pI(pdata[6]));
IBUFi5(.O(data[5]),.pI(pdata[5]));
IBUFi4(.O(data[4]),.pI(pdata[4]));
IBUFi3(.O(data[3]),.pI(pdata[3]));
IBUFi2(.O(data[2]),.pI(pdata[2]));
IBUFi1(.O(data[1]),.pI(pdata[1]));
IBUFi0(.O(data[0]),.pI(pdata[0]));
BIDIRb31(.N2(addr[31]),.pN1(paddr[31]),.WR(wr));
BIDIRb30(.N2(addr[30]),.pN1(paddr[30]),.WR(wr));
BIDIRb29(.N2(addr[29]),.pN1(paddr[29]),.WR(wr));
BIDIRb28(.N2(addr[28]),.pN1(paddr[28]),.WR(wr));
BIDIRb27(.N2(addr[27]),.pN1(paddr[27]),.WR(wr));
BIDIRb26(.N2(addr[26]),.pN1(paddr[26]),.WR(wr));
BIDIRb25(.N2(addr[25]),.pN1(paddr[25]),.WR(wr));
BIDIRb24(.N2(addr[24]),.pN1(paddr[24]),.WR(wr));
BIDIRb23(.N2(addr[23]),.pN1(paddr[23]),.WR(wr));
BIDIRb22(.N2(addr[22]),.pN1(paddr[22]),.WR(wr));
BIDIRb21(.N2(addr[21]),.pN1(paddr[21]),.WR(wr));
BIDIRb20(.N2(addr[20]),.pN1(paddr[20]),.WR(wr));
BIDIRb19(.N2(addr[19]),.pN1(paddr[19]),.WR(wr));
BIDIRb18(.N2(addr[18]),.pN1(paddr[18]),.WR(wr));
BIDIRb17(.N2(addr[17]),.pN1(paddr[17]),.WR(wr));
BIDIRb16(.N2(addr[16]),.pN1(paddr[16]),.WR(wr));
BIDIRb15(.N2(addr[15]),.pN1(paddr[15]),.WR(wr));
BIDIRb14(.N2(addr[14]),.pN1(paddr[14]),.WR(wr));
BIDIRb13(.N2(addr[13]),.pN1(paddr[13]),.WR(wr));
BIDIRb12(.N2(addr[12]),.pN1(paddr[12]),.WR(wr));
BIDIRb11(.N2(addr[11]),.pN1(paddr[11]),.WR(wr));
BIDIRb10(.N2(addr[10]),.pN1(paddr[10]),.WR(wr));
BIDIRb9(.N2(addr[9]),.pN1(paddr[9]),.WR(wr));
BIDIRb8(.N2(addr[8]),.pN1(paddr[8]),.WR(wr));
BIDIRb7(.N2(addr[7]),.pN1(paddr[7]),.WR(wr));
BIDIRb6(.N2(addr[6]),.pN1(paddr[6]),.WR(wr));
BIDIRb5(.N2(addr[5]),.pN1(paddr[5]),.WR(wr));
BIDIRb4(.N2(addr[4]),.pN1(paddr[4]),.WR(wr));
BIDIRb3(.N2(addr[3]),.pN1(paddr[3]),.WR(wr));
BIDIRb2(.N2(addr[2]),.pN1(paddr[2]),.WR(wr));
BIDIRb1(.N2(addr[1]),.pN1(paddr[1]),.WR(wr));
BIDIRb0(.N2(addr[0]),.pN1(paddr[0]),.WR(wr));
endmodule
Example14-Verilog-1995structuraltop-levelASICmodelwithmultipleI/Opadinstantiations
VHDLengineershavebeenabletousetwogeneratefor-loopstoinstantiatethesame32address
and16datapadmodels.WithVerilog-2001,Verilogengineerscannowusesimilarlysimple
generatefor-loopstoinstantiatethe32addressand16datapads,asshowninExample15.
HDLCON2001Verilog-2001Behavioraland
Rev1.3SynthesisEnhancements
21
moduletop_pads2(pdata,paddr,pctl1,pctl2,pctl3,pclk);
inout[15:0]pdata;//paddatabus
input[31:0]paddr;//padaddrbus
inputpctl1,pctl2,pctl3,pclk;//padsignals
wire[15:0]data;//databus
wire[31:0]addr;//addrbus
main_blku1(.data(data),.addr(addr),
.sig1(ctl1),.sig2(ctl2),.sig3(ctl3),.clk(clk));
genvari;
IBUFc4(.O(ctl3),.pI(pctl3));
IBUFc3(.O(ctl2),.pI(pctl2));
IBUFc2(.O(ctl1),.pI(pctl1));
IBUFc1(.O(clk),.pI(pclk));
generatefor(i=0;i<16;i=i+1)begin:dat
IBUFi1(.O(data[i]),.pI(pdata[i]));
generatefor(i=0;i<32;i=i+1)begin:adr
BIDIRb1(.N2(addr[i]),.pN1(paddr[i]),.WR(wr));
endmodule
Example15-Top-levelASICmodelwithaddressanddataI/Opadsinstantiatedusingageneratestatement
Forsimplecontiguousone-dimensionalarrays,thearrayofinstanceconstructiseveneasiertouse
andhasamoreintuitivesyntax.Finally,simulationandsynthesisvendorsarenowstartingto
supporttheVerilog-1995ArrayofInstanceconstructthatmakesplacementof32consecutively
namedinstancespossiblewithaneasyinstantiationbybusnamesasportsandapplyingarangeto
theinstancenameasshowninExample16.
moduletop_pads3(pdata,paddr,pctl1,pctl2,pctl3,pclk);
inout[15:0]pdata;//paddatabus
input[31:0]paddr;//padaddrbus
inputpctl1,pctl2,pctl3,pclk;//padsignals
wire[15:0]data;//databus
wire[31:0]addr;//addrbus
main_blku1(.data(data),.addr(addr),
.sig1(ctl1),.sig2(ctl2),.sig3(ctl3),.clk(clk));
IBUFc4(.O(ctl3),.pI(pctl3));
IBUFc3(.O(ctl2),.pI(pctl2));
IBUFc2(.O(ctl1),.pI(pctl1));
IBUFc1(.O(clk),.pI(pclk));
IBUFi[15:0](.O(data),.pI(pdata));
BIDIRb[31:0](.N2(addr),.pN1(paddr),.WR(wr));
endmodule
Example16-Top-levelASICmodelwithaddressanddataI/Opadsinstantiatedusingarraysofinstance
Arrayedinstance
namesi[15]toi[0]
Arrayedinstancenames
b[31]tob[0]
Generatedinstancenames
dat[0].i1todat[15].i1
Generatedinstancenames
adr[0].b1toadr[31].b1
HDLCON2001Verilog-2001Behavioraland
Rev1.3SynthesisEnhancements
22
7.0Conclusions
TheVerilog-2001enhancementsarecoming.Theseenhancementswillincreasetheefficiencyand
productivityofVerilogdesigners.
8.0HonorableMention
AlthoughtheBehavioralTaskForcebenefitedfromtheexpertiseandcontributionsofnumerous
synthesisexperts,aparticularhonorablementionmustgoouttoKurtBatyofWSFDB.
Kurthasexperiencedesigningsome50ASICsandhaswrittenasignificantnumberofDesign
WaremodelsthatareusedinSynopsyssynthesistools.Kurtcomplainsthathehadtowriteallof
themodelsusingVHDLbecauseVeriloglackedafewofthekeyfeaturesthatarerequiredto
makeparameterizedmodels.Kurt''sinsightintothe1995Veriloglimitationsleadtoenhancements
thatwillmakefutureIPmodelcreationnotonlydoable,butalsoeasiertodoinVerilogthanit
wasinVHDL.
9.0References
[1]IEEEStandardHardwareDescriptionLanguageBasedontheVerilogHardwareDescription
Language,IEEEStdP1364/D5
[2]DouglasL.Perry,VHDL,McGraw-Hill,Inc.,1994,p.1.
[3]IEEEStandardHardwareDescriptionLanguageBasedontheVerilogHardwareDescription
Language,IEEEComputerSociety,IEEEStd1364-1995
[4]www.chris.spear.net
[5]DonMillsandCliffordE.Cummings,"RTLCodingStylesThatYieldSimulationandSynthesis
Mismatches,"SNUG''99(SynopsysUsersGroupSanJose,CA,1999)Proceedings,section-TA2
(1stpaper),March1999.
[6]CliffordE.Cummings,''"full_caseparallel_case",theEvilTwinsofVerilogSynthesis,''SNUG''99
Boston(SynopsysUsersGroupBoston,MA,1999)Proceedings,section-FA1(2ndpaper),
October1999.
Revision1.2-WhatChanged?
TheANSIstyleportsinpreviousversionsofthispaperincorrectlyshowedsemi-colonsbetween
portdeclarationsandbetweentheparameterlistandtheportlist.Theseerrorswerefixedinthis
versionofthedocument.
HDLCON2001Verilog-2001Behavioraland
Rev1.3SynthesisEnhancements
23
Revision1.3(April2002)-WhatChanged?
Example11stillincorrectlyshowedANSIstyleparametersseparatedbyasemicoloninsteadofa
commaandalsoincludedanillegalcommaattheendoftheANSIstyleparameterlist.Notethat
thesecondparameterkeywordisnotrequiredintheANSIstyleparameterlistandwould
typicallyberemoved.
Example11alsoincludedalocalparamdeclarationintheANSIstyleparameterlist,whichis
illegal.ThelocalparamhasbeenmovedoutsideoftheANSIstyleheader.
Author&ContactInformation
CliffCummings,PresidentofSunburstDesign,Inc.,isanindependentEDAconsultantandtrainer
with20yearsofASIC,FPGAandsystemdesignexperienceandtenyearsofVerilog,synthesis
andmethodologytrainingexperience.
Mr.Cummings,amemberoftheIEEE1364VerilogStandardsGroup(VSG)since1994,chaired
theVSGBehavioralTaskForce,whichwaschargedwithproposingenhancementstotheVerilog
language.Mr.CummingsisalsoamemberoftheIEEEVerilogSynthesisInteroperability
WorkingGroupandtheAccelleraSystemVerilogStandardizationGroup
Mr.CummingsholdsaBSEEfromBrighamYoungUniversityandanMSEEfromOregonState
University.
E-mailAddress:cliffc@sunburst-design.com
Thispapercanbedownloadedfromthewebsite:www.sunburst-design.com/papers
(DataaccurateasofDecember17th,2001)
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