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TPD6S300AOVP & ESD
CC Analog USB PD Phy &
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V BUS
FETOVPBattery
5V
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DM
CC1
CC2
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TPD6S300AOVP & ESD
CC Analog USB PD Phy &
ControllerPower Switch Control
FETOVP, OCP V BUS
FETOVPBattery
5V
SBU1
SBU2
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DM
SBU Mux
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本文档旨在为方便起见，提供有关TI产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。English Data Sheet: SLVSEL8
TPD6S300A
ZHCSIE6 –JUNE 2018
TPD6S300A USB Type-C?端端口口保保护护器器：：VBUS短短路路过过压压和和IEC ESD保保护护
1
1特特性性
1? 4通道VBUS短路过压保护（CC1、CC2、SBU1、
SBU2或
CC1、CC2、DP、DM）：耐受24V直流电
? 6通道IEC 61000-4-2 ESD保护（CC1、CC2、
SBU1、SBU2、DP、DM）
? CC1和CC2过压保护FET可处理最高600mA的
电流，因此可支持VCONN电源电流通过
?集成CC死电池电阻器，可用于处理移动设备中的
死电池用例
?相较TPD6S300所具有的优势
–更高的死电池性能
– USB Type-C端口在IEC 61000-4-2 ESD冲击
期间保持连接
? 3mm × 3mm WQFN封装
2应应用用
?笔记本电脑
?平板电脑
?智能手机
?监视器和电视
?扩展坞
3说说明明
TPD6S300A是一种单芯片USB Type-C端口保护器
件，可提供20V VBUS短路过压保护和IEC ESD保
护。
自从USB Type-C连接器发布以来，市场上已经发布
了很多不符合USB Type-C规格的USB Type-C产品
和配件。其中的一个示例就是仅在VBUS线路上布设
20V电压的USB Type-C电力输送适配器。USB
Type-C的另一个问题是，由于此小型连接器中的各引
脚极为靠近，因此连接器的机械扭转和滑动可能使引脚
短路。这可能导致20V VBUS与CC和SBU引脚短
路。此外，由于Type-C连接器中的各引脚极为靠近，
所以存在碎屑和水气导致20V VBUS引脚与CC和
SBU引脚短路的严重问题。
这些非理想的设备和机械事件使得CC和SBU引脚必
须能够承受20V的电压，即使这些引脚仅在5V或更
低电压下工作。通过在CC和SBU引脚上提供过压保
护，TPD6S300A可以使CC和SBU引脚耐受20V的
电压，同时不会干扰正常工作。该器件将高压FET串
联放置在SBU和CC线路上。当在这些线路上检测到
高于OVP阈值的电压时，高压开关被打开，并且将系
统的其余部分与连接器上存在的高压状态隔离。
最后，大多数系统都需要为其外部引脚应用IEC
61000-4-2系统级ESD保护。TPD6S300A为CC1、
CC2、SBU1、SBU2、DP和DM引脚集成了IEC
61000-4-2 ESD保护，无需再在连接器上（外部）放
置高电压TVS二极管。
器器件件信信息息(1)
器器件件型型号号封封装装封封装装尺尺寸寸（（标标称称值值））
TPD6S300A WQFN (20) 3.00mm × 3.00mm
(1)如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
CC和和SBU过过压压保保护护
CC和和DP/DM过过压压保保护护
2
TPD6S300A
ZHCSIE6 –JUNE 2018 www.ti.com.cn
Copyright ? 2018, Texas Instruments Incorporated
目目录录
1特特性性.......................................................................... 1
2应应用用.......................................................................... 1
3说说明明.......................................................................... 1
4修修订订历历史史记记录录........................................................... 2
5 Device Comparison Table..................................... 3
6 Pin Configuration and Functions......................... 4
7 Specifications......................................................... 6
7.1 Absolute Maximum Ratings...................................... 6
7.2 ESD Ratings—JEDEC Specification......................... 6
7.3 ESD Ratings—IEC Specification .............................. 6
7.4 Recommended Operating Conditions....................... 6
7.5 Thermal Information.................................................. 7
7.6 Electrical Characteristics........................................... 7
7.7 Timing Requirements ............................................... 9
7.8 Typical Characteristics............................................ 11
8 Detailed Description............................................ 16
8.1 Overview................................................................. 16
8.2 Functional Block Diagram....................................... 16
8.3 Feature Description................................................. 17
8.4 Device Functional Modes........................................ 20
9 Application and Implementation........................ 21
9.1 Application Information............................................ 21
9.2 Typical Application ................................................. 21
10 Power Supply Recommendations..................... 26
11 Layout................................................................... 27
11.1 Layout Guidelines ................................................. 27
11.2 Layout Example .................................................... 27
12器器件件和和文文档档支支持持..................................................... 28
12.1文档支持................................................................ 28
12.2接收文档更新通知................................................. 28
12.3社区资源................................................................ 28
12.4商标....................................................................... 28
12.5静电放电警告......................................................... 28
12.6术语表................................................................... 28
13机机械械、、封封装装和和可可订订购购信信息息....................................... 28
4修修订订历历史史记记录录
日日期期修修订订版版本本说说明明
2018年6月初始发行版。
3
TPD6S300A
www.ti.com.cn ZHCSIE6 –JUNE 2018
Copyright ? 2018, Texas Instruments Incorporated
5 Device Comparison Table
Part Number Over Voltage Protected Channels IEC 61000-4-2 ESD Protected
Channels
TPD6S300A 4-Ch (CC1, CC2, SBU1, SBU2 or
CC1, CC2, DP, DM)
6-Ch (CC1, CC2, SBU1, SBU2, DP,
DM)
TPD8S300A 4-Ch (CC1, CC2, SBU1, SBU2 or
CC1, CC2, DP, DM)
8-Ch (CC1, CC2, SBU1, SBU2, DP_T,
DM_T, DP_B, DM_B)
C_CC
2
C_CC
1
C_S
BU
2
C_S
BU
1
CC2CC1SBU2SBU1
VBIA
S
GN
D
N.C.
N.C.
D1
D2
GND
RPD_G2
RPD_G1
VPWR
FLT
GND
15 11
10
6
51
20
16
Thermal Pad
4
TPD6S300A
ZHCSIE6 –JUNE 2018 www.ti.com.cn
Copyright ? 2018, Texas Instruments Incorporated
(1) I = input, O = output, I/O = input and output, GND = ground, P = power
6 Pin Configuration and Functions
RUK Package
20-Pin WQFN
Top View
Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
1 C_SBU1 I/O
Connector side of the SBU1 OVP FET. Connect to either SBU pin of the USB Type-C
connector. Alternatively, connect to either USB2.0 pin of the USB Type-C connector to
protect the USB2.0 pins instead of the SBU pins
2 C_SBU2 I/O
Connector side of the SBU2 OVP FET. Connect to either SBU pin of the USB Type-C
connector. Alternatively, connect to either USB2.0 pin of the USB Type-C connector to
protect the USB2.0 pins instead of the SBU pins
3 VBIAS P Pin for ESD support capacitor. Place a 0.1-μF capacitor on this pin to ground
4 C_CC1 I/O Connector side of the CC1 OVP FET. Connect to either CC pin of the USB Type-Cconnector
5 C_CC2 I/O Connector side of the CC2 OVP FET. Connect to either CC pin of the USB Type-Cconnector
6 RPD_G2 I/O Short to C_CC2 if dead battery resistors are needed. If dead battery resistors are notneeded, short pin to GND
7 RPD_G1 I/O Short to C_CC1 if dead battery resistors are needed. If dead battery resistors are notneeded, short pin to GND
8 GND GND Ground
9 FLT O Open drain for fault reporting
10 VPWR P 2.7-V to 4.5-V power supply
11 CC2 I/O System side of the CC2 OVP FET. Connect to either CC pin of the CC/PD controller
12 CC1 I/O System side of the CC1 OVP FET. Connect to either CC pin of the CC/PD controller
13 GND GND Ground
14 SBU2 I/O
System side of the SBU2 OVP FET. Connect to either SBU pin of the SBU MUX.
Alternatively, connect to either USB2.0 pin of the USB2.0 Phy when protecting the
USB2.0 pins instead of protecting the SBU pins
15 SBU1 I/O
System side of the SBU1 OVP FET. Connect to either SBU pin of the SBU MUX.
Alternatively, connect to either USB2.0 pin of the USB2.0 Phy when protecting the
USB2.0 pins instead of protecting the SBU pins
5
TPD6S300A
www.ti.com.cn ZHCSIE6 –JUNE 2018
Copyright ? 2018, Texas Instruments Incorporated
Pin Functions (continued)
PIN TYPE(1) DESCRIPTION
NO. NAME
16 N.C. I/O Unused pin. Connect to Ground
17 N.C. I/O Unused pin. Connect to Ground
18 GND GND Ground
19 D2 I/O USB2.0 IEC ESD protection. Connect to any of the USB2.0 pins of the USB Type-Cconnector
20 D1 I/O USB2.0 IEC ESD protection. Connect to any of the USB2.0 pins of the USB Type-Cconnector
— Thermal Pad GND Internally connected to GND. Used as a heatsink. Connect to the PCB GND plane
6
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ZHCSIE6 –JUNE 2018 www.ti.com.cn
Copyright ? 2018, Texas Instruments Incorporated
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VI Input voltage VPWR –0.3 5 VRPD_G1, RPD_G2 –0.3 24 V
VO Output voltage FLT –0.3 6 VVBIAS –0.3 24 V
VIO I/O voltage
D1, D2 –0.3 6 V
CC1, CC2, SBU1, SBU2 –0.3 6 V
C_CC1, C_CC2, C_SBU1, C_SBU2 –0.3 24 V
TA Operating free air temperature –40 85 °C
Tstg Storage temperature –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000
V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V
may actually have higher performance.
7.2 ESD Ratings—JEDEC Specification
VALUE UNIT
V(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
VCharged-device model (CDM), per JEDEC specification
JESD22-C101(2) ±500
(1) Tested on the TPD6S300 EVM connected to the TPS65982 EVM.
7.3 ESD Ratings—IEC Specification
VALUE UNIT
V(ESD) Electrostatic discharge(1)
IEC 61000-4-2, C_CC1, C_CC2, D1, D2 Contact discharge ±8000
VAir-gap discharge ±15000
IEC 61000-4-2, C_SBU1, C_SBU2 Contact discharge ±6000Air-gap discharge ±15000
7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VI Input voltage VPWR 2.7 3.3 4.5 VRPD_G1, RPD_G2 0 5.5 V
VO Output voltage FLT pull-up resistor power rail 2.7 5.5 V
VIO I/O voltage
D1, D2 –0.3 5.5 V
CC1, CC2, C_CC1, C_CC2 0 5.5 V
SBU1, SBU2, C_SBU1, C_SBU2 0 4.3 V
IVCONN VCONN current
Current flowing into CC1/2 and flowing
out of C_CC1/2, VCCx – VC_CCx ≤
250 mV
600 mA
IVCONN VCONN current Current flowing into CC1/2 and flowingout of C_CC1/2, T
J ≤ 105°C
600 mA
IVCONN VCONN current Current flowing into CC1/2 and flowingout of C_CC1/2, T
J ≤ 85°C
1.25 A
7
TPD6S300A
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Copyright ? 2018, Texas Instruments Incorporated
Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
(1) For recommended values for capacitors and resistors, the typical values assume a component placed on the board near the pin.
Minimum and maximum values listed are inclusive of manufacturing tolerances, voltage derating, board capacitance, and temperature
variation. The effective value presented must be within the minimum and maximums listed in the table.
(2) The VBIAS pin requires a minimum 35-VDC rated capacitor. A 50-VDC rated capacitor is recommended to reduce capacitance derating.
See the VBIAS Capacitor Selection section for more information on selecting the VBIAS capacitor.
External components(1)
FLT pullup resistance 1.7 300 kΩ
VBIAS capacitance(2) 0.1 μF
VPWR capacitance 0.3 1 μF
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Thermal Information
THERMAL METRIC(1)
TPD6S300A
UNITRUK (WQFN)
20 PINS
RθJA Junction-to-ambient thermal resistance 45.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 48.8 °C/W
RθJB Junction-to-board thermal resistance 17.1 °C/W
ψJT Junction-to-top characterization parameter 0.6 °C/W
ψJB Junction-to-board characterization parameter 17.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.7 °C/W
7.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CC OVP SWITCHES
RON
On resistance of CC OVP FETs, TJ ≤
85°C CCx = 5.5 V 278 392 mΩ
On resistance of CC OVP FETs, TJ ≤
105°C CCx = 5.5 V 278 415 mΩ
RON(FLAT) On resistance flatness Sweep CCx voltage between 0 V and1.2 V 5 mΩ
CON_CC Equivalent on capacitance
Capacitance from C_CCx or CCx to
GND when device is powered.
VC_CCx/VCCx = 0 V to 1.2 V, f = 400
kHz
60 74 120 pF
RD
Dead battery pull-down resistance
(only present when device is
unpowered). Effective resistance of
RD and FET in series
V_C_CCx = 2.6 V 4.1 5.1 6.1 kΩ
VTH_DB
Threshold voltage of the pulldown
FET in series with RD during dead
battery
I_CC = 80 μA 0.5 0.9 1.2 V
VOVPCC OVP threshold on CC pins Place 5.5 V on C_CCx. Step upC_CCx until the FLT pin is asserted 5.75 6 6.2 V
VOVPCC_HYS Hysteresis on CC OVP
Place 6.5 V on C_CCx. Step down the
voltage on C_CCx until the FLT pin is
deasserted. Measure difference
between rising and falling OVP
threshold for C_CCx
50 mV
BWON On bandwidth single ended (–3 dB)
Measure the –3-dB bandwidth from
C_CCx to CCx. Single ended
measurement, 50-Ω system. Vcm = 0.1
V to 1.2 V
100 MHz
8
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ZHCSIE6 –JUNE 2018 www.ti.com.cn
Copyright ? 2018, Texas Instruments Incorporated
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VSTBUS_CC Short-to-VBUS tolerance on the CCpins
Hot-Plug C_CCx with a 1 meter USB
Type C Cable, place a 30-Ω load on
CCx
24 V
VSTBUS_CC_CL
AMP
Short-to-VBUS system-side clamping
voltage on the CC pins (CCx)
Hot-Plug C_CCx with a 1 meter USB
Type C Cable. Hot-Plug voltage
C_CCx = 24 V. VPWR = 3.3 V. Place
a 30-Ω load on CCx
8 V
SBU OVP SWITCHES
RON On resistance of SBU OVP FETs SBUx = 3.6 V. –40°C ≤ TJ ≤ +85°C 4 6.5 Ω
RON(FLAT) On resistance flatness Sweep SBUx voltage between 0 V and3.6 V. –40°C ≤ T
J ≤ +85°C
0.7 1.5 Ω
CON_SBU Equivalent on capacitance
Capacitance from SBUx or C_SBUx to
GND when device is powered.
Measure at VC_SBUx/VSBUx = 0.3 V
to 3.6 V
6 pF
VOVPSBU OVP threshold on SBU pins Place 3.6 V on C_SBUx. Step upC_SBUx until the FLT pin is asserted 4.35 4.5 4.7 V
VOVPSBU_HYS Hysteresis on SBU OVP
Place 5 V on C_CCx. Step down the
voltage on C_CCx until the FLT pin is
deasserted. Measure difference
between rising and falling OVP
threshold for C_SBUx
50 mV
BWON On bandwidth single ended (–3 dB)
Measure the –3-dB bandwidth from
C_SBUx to SBUx. Single ended
measurement, 50-Ω system. Vcm = 0.1
V to 3.6 V
1000 MHz
XTALK Crosstalk
Measure crosstalk at f = 1 MHz from
SBU1 to C_SBU2 or SBU2 to
C_SBU1. Vcm1 = 3.6 V, Vcm2 = 0.3 V.
Be sure to terminate open sides to 50
Ω
–80 dB
VSTBUS_SBU Short-to-VBUS tolerance on the SBUpins
Hot-Plug C_SBUx with a 1 meter USB
Type C Cable. Put a 100-nF capacitor
in series with a 40-Ω resistor to GND
on SBUx
24 V
VSTBUS_SBU_C
LAMP
Short-to-VBUS system-side clamping
voltage on the SBU pins (SBUx)
Hot-Plug C_SBUx with a 1 meter USB
Type C Cable. Hot-Plug voltage
C_SBUx = 24 V. VPWR = 3.3 V. Put a
150-nF capacitor in series with a 40-Ω
resistor to GND on SBUx
8 V
POWER SUPPLY and LEAKAGE CURRENTS
VPWR_UVLO VPWR under voltage lockout Place 1 V on VPWR and raise voltageuntil SBU or CC FETs turnon 2.1 2.3 2.5 V
VPWR_UVLO_H
YS
VPWR UVLO hysteresis
Place 3 V on VPWR and lower voltage
until SBU or CC FETs turnoff; measure
difference between rising and falling
UVLO to calculate hysteresis
100 150 200 mV
IVPWR VPWR supply current VPWR = 3.3 V (typical), VPWR = 4.5 V(maximum). –40°C ≤ T
J ≤ +85°C.
90 135 μA
ICC_LEAK Leakage current for CC pins whendevice is powered
VPWR = 3.3 V, VC_CCx = 3.6 V, CCx
pins are floating, measure leakage into
C_CCx pins. Result must be same if
CCx side is biased and C_CCx is left
floating
5 μA
9
TPD6S300A
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Copyright ? 2018, Texas Instruments Incorporated
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISBU_LEAK Leakage current for SBU pins whendevice is powered
VPWR = 3.3 V, VC_SBUx = 3.6 V,
SBUx pins are floating, measure
leakge into C_SBUx pins. Result must
be same if SBUx side is biased and
C_SBUx is left floating. –40°C ≤ TJ ≤
+85°C
3 μA
IC_CC_LEAK_OV
P
Leakage current for CC pins when
device is in OVP
VPWR = 0 V or 3.3 V, VC_CCx = 24
V, CCx pins are set to 0 V, measure
leakage into C_CCx pins
1200 μA
IC_SBU_LEAK_O
VP
Leakage current for SBU pins when
device is in OVP
VPWR = 0 V or 3.3 V, VC_SBUx = 24
V, SBUx pins are set to 0 V, measure
leakage into C_SBUx pins
400 μA
ICC_LEAK_OVP Leakage current for CC pins whendevice is in OVP
VPWR = 0 V or 3.3 V, VC_CCx = 24
V, CCx pins are set to 0 V, measure
leakage out of CCx pins
30 μA
ISBU_LEAK_OVP Leakage current for SBU pins whendevice is in OVP
VPWR = 0 V or 3.3 V, VC_SBUx = 24
V, SBUx pins are set to 0 V, measure
leakage out of SBUx pins
–1 1 μA
IDx_LEAK Leakage current for Dx pins V_Dx = 3.6 V, measure leakage intoDx pins 1 μA
FLT PIN
VOL Low-level output voltage IOL = 3 mA. Measure the voltage atthe FLT pin 0.4 V
OVER TEMPERATURE PROTECTION
TSD_RISING The rising over-temperatureprotection shutdown threshold 150 175 °C
TSD_FALLING The falling over-temperatureprotection shutdown threshold 130 140 °C
TSD_HYST The over-temperature protectionshutdown threshold hysteresis 35 °C
Dx ESD PROTECTION
VRWM_POS Reverse stand-off voltage from Dx toGND Dx to GND. IDX ≤ 1 μA 5.5 V
VRWM_NEG Reverse stand-off voltage from GNDto Dx GND to Dx 0 V
VBR_POS Break-down voltage from Dx to GND Dx to GND. IBR = 1 mA 7 V
VBR_NEG Break-down voltage from GND to Dx GND to Dx. IBR = 8 mA 0.6 V
CIO Dx to GND or GND to Dx f = 1 MHz, VIO = 2.5 V 1.7 pF
ΔCIO Differential capacitance between twoDx pins f = 1 MHz, VIO = 2.5 V 0.02 pF
RDYN Dynamic on-resistance Dx IECclamps Dx to GND or GND to Dx 0.4 Ω
7.7 Timing Requirements
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
POWER-ON and Off TIMINGS
tON_FET Time from crossing rising VPWR UVLO until CC and SBUOVP FETs are on 1.3 3.5 ms
tON_FET_DB
Time from crossing rising VPWR UVLO until CC and SBU
OVP FETs are on and the dead battery resistors are
turned off
5.7 9.5 ms
dVPWR_OFF/dt Minimum Slew rate allowed to guarantee CC and SBUFETs turnoff during a power off –0.5 V/μs
10
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ZHCSIE6 –JUNE 2018 www.ti.com.cn
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Timing Requirements (continued)
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
OVER VOLTAGE PROTECTION
tOVP_RESPONSE_CC OVP response time on the CC pins. Time from OVPasserted until OVP FETs turnoff 70 ns
tOVP_RESPONSE_SBU OVP response time on the SBU pins. Time from OVPasserted until OVP FETs turnoff 80 ns
tOVP_RECOVERY_CC_1_FET
OVP recovery time on the CC pins. Once an OVP has
occurred, the minimum time duration until the CC FETs
turn back on. OVP must be removed for CC FETs to turn
back on
0.93 ms
tOVP_RECOVERY_CC_1_DB
OVP recovery time on the CC pins. Once an OVP has
occurred, the minimum time duration until the CC FETs
turn back on and the dead battery resistors turn off. OVP
must be removed for CC FETs to turn back on
5 ms
tOVP_RECOVERY_SBU_1
OVP recovery time on the SBU pins. Once an OVP has
occurred, the minimum time duration until the SBU FETs
turn back on. OVP must be removed for SBU FETs to turn
back on
0.62 ms
tOVP_RECOVERY_CC_2_FET
OVP recovery time on the CC pins. Time from OVP
Removal until CC FETs turn back on, if device has been in
OVP > 0.6 ms
0.61 ms
tOVP_RECOVERY_CC_2_DB
OVP recovery time on the CC pins. Time from OVP
Removal until CC FETs turn back on and dead battery
resistors turn off, if device has been in OVP > 0.6 ms
4.75 ms
tOVP_RECOVERY_SBU_2
OVP recovery time on the SBU pins. Time from OVP
Removal until SBU FETs turn back on, if device has been
in OVP > 0.6 ms
0.3 ms
tOVP_FLT_ASSERTION Time from OVP asserted to FLT assertion 20 μs
tOVP_FLT_DEASSERTION Time from CC FET turnon after an OVP to FLTdeassertion 4.1 ms
VSBU1 (V)
RON
(:
)
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 3.6
2
3
4
5
6
7
D014
-40qC
25qC
85qC
125qC
Time (ns)
Volta
ge
(V)
-10 0 10 20 30 40 50 60 70 80 90 100 110
-80
-60
-40
-20
0
20
40
60
80
100
120
140
D001
C_SBU
SBU
Time (Ps)
Vol
tage (
V) o
r C
urr
en
t (A)
-0.05 0.2 0.45 0.7 0.95 1.2 1.45 1.7 1.95
-1.5
0.5
2.5
4.5
6.5
8.5
10.5
12.5
14.5
16.5
18.5
20.5
22.5
24.5
26.5
28.5
30.5
D014
VC_SBU1
IC_SBU1
VSBU1
V/FLT
Time (Ps)
Vol
tage (
V) o
r C
urr
en
t (A)
-2.2 -0.2 1.8 3.8 5.8 7.8 9.8 11.8 13.8 15.8 17.8
-1.5
0.5
2.5
4.5
6.5
8.5
10.5
D014
VC_SBU1
IC_SBU1
VSBU1
V/FLT
Frequency (Hz)
Ins
ertion
Los
s (dB)
1E+7 1E+8 1E+9 3E+9
-12
-9
-6
-3
0
D016 Frequency (Hz)
Cr
os
stalk
(d
B)
0 1E+9 2E+9 3E+9
-80
-70
-60
-50
-40
-30
-20
-10
0
D017
SBUx to C_SBUx
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7.8 Typical Characteristics
图图1. SBU S21 BW图图2. SBU Crosstalk
图图3. SBU Short-to-VBUS 20 V图图4. SBU Short-to-VBUS 5 V
图图5. SBU RON Flatness图图6. SBU IEC 61000-4-2 4-kV Response Waveform
Time (ms)
Volta
ge
(V)
-3 -2 -1 0 1 2 3 4 5 6 7
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
3.3
3.6
D014
VPWR
C_SBU1
SBU1
Voltage (V)
Cur
rent
(A)
0 5 10 15 20 25 30 35 40
0
5
10
15
20
25
30
D005
C_SBU
Temperature (qC)
Leak
age Cu
rre
nt
(P
A)
-40 -30 -20 -10 0 10 20 30 40 50 60 70 8085
0
50
100
150
200
250
300
350
400
450
500
D014
C_SBU1 at 24 V
C_SBU2 at 24 V
C_SBU1 at 5.5 V
C_SBU2 at 5.5 V
Temperature (qC)
Lea
ka
ge C
urren
t (P
A)
-40 -30 -20 -10 0 10 20 30 40 50 60 70 8085
0
2.5E-5
5E-5
7.5E-5
0.0001
0.000125
D014
SBU1: C_SBU1 at 24 V
SBU2: C_SBU2 at 24 V
SBU1: C_SBU1 at 5.5 V
SBU2: C_SBU2 at 5.5 V
Time (ns)
Vol
tage (
V)
-10 0 10 20 30 40 50 60 70 80 90 100 110
-100
-80
-60
-40
-20
0
20
40
60
80
D001
C_SBU
SBU
Temperature (qC)
Leak
ge Curr
ent
(P
A)
-40 -30 -20 -10 0 10 20 30 40 50 60 70 8085
0
0.5
1
1.5
2
2.5
D014
C_SBU1
C_SBU2
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Typical Characteristics (接接下下页页)
图图7. SBU IEC 61000-4-2 –4-kV Response Waveform图图8. SBU Path Leakage Current vs Ambient Temperature at
3.6 V
图图9. C_SBU OVP Leakage Current vs Ambient Temperature
at 5.5 V and 24 V
图图10. SBU OVP Leakage Current vs Ambient Temperature
at 5.5 V and 24 V
图图11. SBU FET Turnon Timing图图12. C_SBU TLP Curve Unpowered
Time (ns)
Volta
ge
(V)
-10 0 10 20 30 40 50 60 70 80 90 100 110
-80
-60
-40
-20
0
20
40
60
80
100
120
140
D001
C_CC
CC
Time (ns)
Vol
tage (
V)
-10 0 10 20 30 40 50 60 70 80 90 100 110
-100
-80
-60
-40
-20
0
20
40
60
80
D001
C_CC
CC
Time (Ps)
Vol
tage (
V) o
r C
urr
en
t (A)
-0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.71.8
-1.5
0.5
2.5
4.5
6.5
8.5
10.5
12.5
14.5
16.5
18.5
20.5
22.5
24.5
26.5
28.5
30.5
D014
VC_CC1
IC_CC1
VCC1
V/FLT
VCC1 (V)
RON
(:
)
0 0.2 0.4 0.6 0.8 1 1.2
0
0.1
0.2
0.3
0.4
0.5
0.6
D014
-40qC
25qC
85qC
125qC
Voltage (V)
Curr
ent
(mA)
-5 0 5 10 15 20 25 30 35
-1
-0.75
-0.5
-0.25
0
0.25
0.5
0.75
1
D003
C_SBU
Frequency (Hz)
Inse
rtion
Loss
(dB
)
1E+7 1E+8 1E+9 3E+9
-12
-9
-6
-3
0
D016
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Typical Characteristics (接接下下页页)
图图13. SBU IV Curve图图14. CC S21 BW
图图15. CC Short-to-VBUS 20 V图图16. CC RON Flatness
图图17. CC IEC 61000-4-2 8-kV Response Waveform图图18. CC IEC 61000-4-2 –8-kV Response Waveform
Voltage (V)
Cur
rent
(A)
0 5 10 15 20 25 30 35 40 45
0
5
10
15
20
25
30
D0035
C_CC
Voltage (V)
Curr
ent
(mA)
-5 0 5 10 15 20 25 30
-1
-0.75
-0.5
-0.25
0
0.25
0.5
0.75
1
D003
C_CC
Temperature (qC)
Leak
ge Curr
ent
(P
A)
-40 -30 -20 -10 0 10 20 30 40 50 60 70 8085
3E-5
8E-5
1.3E-4
1.8E-4
2.3E-4
2.8E-4
3.3E-4
3.8E-4
4.3E-4
D014
CC1: C_CC1 at 24 V
CC2: C_CC2 at 24 V
Time (ms)
Volta
ge
(V)
-3 -2 -1 0 1 2 3 4 5 6 7
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
D014
VPWR
C_CC1
CC1
Temperature (qC)
Lea
kg
e Cu
rren
t (P
A)
-40 -30 -20 -10 0 10 20 30 40 50 60 70 8085
8
9
10
11
12
13
14
15
16
17
18
19
20
D014
C_CC1
C_CC2
Temperature (qC)
Leak
ge Curr
ent
(P
A)
-40 -30 -20 -10 0 10 20 30 40 50 60 70 8085
1000
1005
1010
1015
1020
1025
1030
D014
C_CC1
C_CC2
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Typical Characteristics (接接下下页页)
图图19. C_CC Path Leakage Current vs Ambient Temperature
at C_CC = 5.5 V
图图20. C_CC OVP Leakage Current vs Ambient Temperature
at C_CC = 24 V
图图21. CC OVP Leakage Current vs Ambient Temperature at
C_CC = 24 V
图图22. CC FET Turnon Timing
图图23. C_CC TLP Curve Unpowered图图24. C_CC IV Curve
Voltage (V)
Curr
ent
(mA)
-2 0 2 4 6 8 10
-1
-0.75
-0.5
-0.25
0
0.25
0.5
0.75
1
D003
Dx
Voltage (V)
Cur
rent
(A)
0 2 4 6 8 10 12 14 16 18
0
5
10
15
20
25
30
D0035
Dx
Temperature (qC)
Cur
rent
(PA
)
-40 -30 -20 -10 0 10 20 30 40 50 60 70 8085
80
82.5
85
87.5
90
92.5
95
97.5
100
D014
IVPWR
Temperature (qC)
Leak
age Cu
rre
nt
(nA)
-40 -30 -20 -10 0 10 20 30 40 50 60 70 8085
0
1
2
3
4
5
6
7
D014
Dx at 3.6 V
Dx at 0.4 V
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Typical Characteristics (接接下下页页)
图图25. VPWR Supply Leakage vs Ambient Temperature at 3.6
V
图图26. Dx Leakage Current vs Ambient Temperature at 0.4 V
and 3.6 V
图图27. Dx IV Curve图图28. Dx TLP Curve
Control Logic and
Charge Pumps VPWR
Over-voltage
Protection
C_SBU1
C_SBU2
SBU1
SBU2
ESD
Clamps
FLT
C_CC1
C_CC2
CC1
CC2
ESD
Clamps
D1 D2
RD
/VPWRRD
/VPWR
RPD_G1
RPD_G2
System
Clamps
System
Clamps
VBIAS
Copyright ? 2016, Texas Instruments Incorporated
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8 Detailed Description
8.1 Overview
The TPD6S300A is a single chip USB Type-C port protection solution that provides 20-V Short-to-VBUS
overvoltage and IEC ESD protection. Due to the small pin pitch of the USB Type-C connector and non-compliant
USB Type-C cables and accessories, the VBUS pins can get shorted to the CC and SBU pins inside the USB
Type-C connector. Because of this short-to-VBUS event, the CC and SBU pins need to be 20-V tolerant, to
support protection on the full USB PD voltage range. Even if a device does not support 20-V operation on VBUS,
non complaint adaptors can start out with 20-V VBUS condition, making it necessary for any USB Type-C device
to support 20 V protection. The TPD6S300A integrates four channels of 20-V Short-to-VBUS overvoltage
protection for the CC1, CC2, SBU1, and SBU2 pins of the USB Type-C connector.
Additionally, IEC 61000-4-2 system level ESD protection is required in order to protect a USB Type-C port from
ESD strikes generated by end product users. The TPD6S300A integrates six channels of IEC61000-4-2 ESD
protection for the CC1, CC2, SBU1, SBU2, DP, and DM pins of the USB Type-C connector. This means IEC
ESD protection is provided for all of the low-speed pins on the USB Type-C connector in a single chip in the
TPD6S300A. Additionally, high-voltage IEC ESD protection that is 22-V DC tolerant is required for the CC and
SBU lines in order to simultaneously support IEC ESD and Short-to-VBUS protection; there are not many discrete
market solutions that can provide this kind of protection. This high-voltage IEC ESD diode is what the
TPD6S300A integrates, specifically designed to guarantee it works in conjunction with the overvoltage protection
FETs inside the device. This sort of solution is very hard to generate with discrete components.
8.2 Functional Block Diagram
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8.3 Feature Description
8.3.1 4-Channels of Short-to-VBUS Overvoltage Protection (CC1, CC2, SBU1, SBU2 Pins or CC1, CC2, DP,
DM Pins): 24-VDC Tolerant
The TPD6S300A provides 4-channels of Short-to-VBUS Overvoltage Protection for the CC1, CC2, SBU1, and
SBU2 pins (or the CC1, CC2, DP, and DM pins) of the USB Type-C connector. The TPD6S300A is able to
handle 24-VDC on its C_CC1, C_CC2, C_SBU1, and C_SBU2 pins. This is necessary because according to the
USB PD specification, with VBUS set for 20-V operation, the VBUS voltage is allowed to legally swing up to 21 V
and 21.5 V on voltage transitions from a different USB PD VBUS voltage. The TPD6S300A builds in tolerance up
to 24-VBUS to provide margin above this 21.5-V specification to be able to support USB PD adaptors that may
break the USB PD specification.
When a short-to-VBUS event occurs, ringing happens due to the RLC elements in the hot-plug event. With very
low resistance in this RLC circuit, ringing up to twice the settling voltage can appear on the connector. More than
2x ringing can be generated if any capacitor on the line derates in capacitance value during the short-to-VBUS
event. This means that more than 44 V could be seen on a USB Type-C pin during a Short-to-VBUS event. The
TPD6S300A has built in circuit protection to handle this ringing. The diode clamps used for IEC ESD protection
also clamp the ringing voltage during the short-to-VBUS event to limit the peak ringing to approximately 30 V.
Additionally, the overvoltage protection FETs integrated inside the TPD6S300A are 30-V tolerant, therefore being
capable of supporting the high-voltage ringing waveform that is experienced during the short-to-VBUS event. The
well designed combination of voltage clamps and 30-V tolerant OVP FETs insures the TPD6S300A can handle
Short-to-VBUS hot-plug events with hot-plug voltages as high as 24-VDC.
The TPD6S300A has an extremely fast turnoff time of 70 ns typical. Furthermore, additional voltage clamps are
placed after the OVP FET on the system side (CC1, CC2, SBU1, SBU2) pins of the TPD6S300A, to further limit
the voltage and current that are exposed to the USB Type-C CC/PD controller during the 70 ns interval while the
OVP FET is turning off. The combination of connector side voltage clamps, OVP FETs with extremely fast turnoff
time, and system side voltage clamps all work together to insure the level of stress seen on a CC1, CC2, SBU1,
or SBU2 pin during a short-to-VBUS event is less than or equal to an HBM event. This is done by design, as any
USB Type-C CC/PD controller will have built in HBM ESD protection.
The SBU OVP FETs where designed with a 1-GHz bandwidth to be able to be used to protect the DP, DM
(USB2.0) pins in addition to the SBU pins. Some systems designers also prefer to protect the DP, DM pins from
Short-to-VBUS events due to the potential for moisture/water in the connector to short the VBUS pins to DP, DM
pins. This can be especially applicable in cases where the end equipment with a USB Type-C connector is trying
to be made water-proof. If desiring to protect the DP, DM pins on the USB Type-C connector from a Short-to-
VBUS event, connect the C_SBUx pins to the DP, DM pins on the USB Type-C connector, and the SBUx pins to
the USB2.0 pins of the system device being protected from the Short-to-VBUS event.
图29 is an example of the TPD6S300A successfully protecting the TPS65982, the world''s first fully integrated,
full-featured USB Type-C and PD controller.
图图29. TPD6S300A Protecting the TPS65982 During a Short-to-VBUS Event
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Feature Description (接接下下页页)
8.3.2 6-Channels of IEC 61000-4-2 ESD Protection (CC1, CC2, SBU1, SBU2, DP, DM Pins)
The TPD6S300A integrates 6-Channels of IEC 61000-4-2 system level ESD protection for the CC1, CC2, SBU1,
SBU2, DP, and DM pins. USB Type-C ports on end-products need system level IEC ESD protection in order to
provide adequate protection for the ESD events that the connector can be exposed to from end users. The
TPD6S300A integrates IEC ESD protection for all of the low-speed pins on the USB Type-C connector in a
single chip. Also note, that while the RPD_Gx pins are not individually rated for IEC ESD, when they are shorted
to the C_CCx pins, the C_CCx pins provide protection for both the C_CCx pins and the RPD_Gx pins.
Additionally, high-voltage IEC ESD protection that is 24-V DC tolerant is required for the CC and SBU lines in
order to simultaneously support IEC ESD and Short-to-VBUS protection; there are not many discrete market
solutions that can provide this kind of protection. The TPD6S300A integrates this type of high-voltage ESD
protection so a system designer can meet both IEC ESD and Short-to-VBUS protection requirements in a single
device.
8.3.3 CC1, CC2 Overvoltage Protection FETs 600 mA Capable for Passing VCONN Power
The CC pins on the USB Type-C connector serve many functions; one of the functions is to be a provider of
power to active cables. Active cables are required when desiring to pass greater than 3 A of current on the VBUS
line or when the USB Type-C port uses the super-speed lines (TX1+, TX2–, RX1+, RX1–, TX2+, TX2–, RX2+,
RX2–). When CC is configured to provide power, it is called VCONN. VCONN is a DC voltage source in the
range of 3 V to 5.5 V. If supporting VCONN, a VCONN provider must be able to provide 1 W of power to a cable;
this translates into a current range of 200 mA to 333 mA (depending on your VCONN voltage level). Additionally,
if operating in a USB PD alternate mode, greater power levels are allowed on the VCONN line.
When a USB Type-C port is configured for VCONN and using the TPD6S300A, this VCONN current flows
through the OVP FETs of the TPD6S300A. Therefore, the TPD6S300A has been designed to handle these
currents and have an RON low enough to provide a specification compliant VCONN voltage to the active cable.
The TPD6S300A is designed to handle up to 600 mA of DC current to allow for alternate mode support in
addition to the standard 1 W required by the USB Type-C specification.
8.3.4 CC Dead Battery Resistors Integrated for Handling the Dead Battery Use Case in Mobile Devices
An important feature of USB Type-C and USB PD is the ability for this connector to serve as the sole power
source to mobile devices. With support up to 100 W, the USB Type-C connector supporting USB PD can be
used to power a whole new range of mobile devices not previously possible with legacy USB connectors.
When the USB Type-C connector is the sole power supply for a battery powered device, the device must be able
to charge from the USB Type-C connector even when its battery is dead. In order for a USB Type-C power
adapter to supply power on VBUS, RD pulldown resistors must be exposed on the CC pins. These RD resistors
are typically included inside a USB Type-C CC/PD controller. However, when the TPD6S300A is used to protect
the USB Type-C port, the OVP FETs inside the device isolate these RD resistors in the CC/PD controller when
the mobile device has no power. This is because when the TPD6S300A has no power, the OVP FETs are turned
off to guarantee overvoltage protection in a dead battery condition. Therefore, the TPD6S300A integrates high-
voltage, dead battery RD pull-down resistors to allow dead battery charging simultaneously with high-voltage
OVP protection.
If dead battery support is required, short the RPD_G1 pin to the C_CC1 pin, and short the RPD_G2 pin to the
C_CC2 pin. This connects the dead battery resistors to the connector CC pins. When the TPD6S300A is
unpowered, and the RP pull-up resistor is connected from a power adaptor, this RP pull-up resistor activates the
RD resistor inside the TPD6S300A. This enables VBUS to be applied from the power adaptor even in a dead
battery condition. Once power is restored back to the system and back to the TPD6S300A on its VPWR pin, the
TPD6S300A turns ON its OVP FETs in 3.5 ms and then turns OFF its dead battery RD. The TPD6S300A first
turns ON its CC OVP FETs fully, and then removes its dead battery RDs. This is to make sure the PD controller
RD is fully exposed before removing the RD of the TPD6S300A. This is to help ensure the USB Type-C source
remains attached because a USB Type-C sink must have an RD present on CC at all times to guarantee
according to the USB Type-C spec that the USB Type-C source remains attached.
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Feature Description (接接下下页页)
If desiring to power the CC/PD controller during dead battery mode and if the CC/PD Controller is configured as
a DRP, it is critical that the TPD6S300A be powered before or at the same time that the CC/PD controller is
powered. It is also critical that when unpowered, the CC/PD controller also expose its dead battery resistors.
When the TPD6S300A gets powered, it exposes the CC pins of the CC/PD controller within 3.5 ms, and then
removes its own RD dead battery resistors. Once the TPD6S300A turns on, the RD pull-down resistors of the
CC/PD controller must be present immediately, in order to guarantee the power adaptor connected to power the
dead battery device keeps its VBUS turned on. If the power adaptor does not see RD present, it can disconnect
VBUS. This removes power from the device with its battery still not sufficiently charged, which consequently
removes power from the CC/PD controller and the TPD6S300A. Then the RD resistors of the TPD6S300A are
exposed again, and connects the power adaptor''s VBUS to start the cycle over. This creates an infinite loop, never
or very slowly charging the mobile device.
If the CC/PD Controller is configured for DRP and has started its DRP toggle before the TPD6S300A turns on,
this DRP toggle is unable to guarantee that the power adaptor does not disconnect from the port. Therefore, it is
recommended if the CC/PD controller is configured for DRP, that its dead battery resistors be exposed as well,
and that they remain exposed until the TPD6S300A turns on. This is typically accomplished by powering the
TPD6S300A at the same time as the CC/PD controller when powering the CC/PD controller in dead battery
operation. When protecting the TPS6598x family of PD controllers with TPD6S300A, this is accomplished by
powering TPD6S300A from TPS6598x''s LDO_3V3 pin (connect TPS6598x''s LDO_3V3 pin to TPD6S300A''s
VPWR pin).
If dead battery charging is not required in your application, connect the RPD_G1 and RPD_G2 pins to ground.
8.3.5 Advantages over TPD6S300
8.3.5.1 Improved Dead Battery Performance
The TPD6S300A has improved dead battery performance over TPD6S300. In the TPD6S300 when the device is
first powered (VPWR pin goes from 0V to 3.3V), the CC RD dead battery resistors are disabled at the same time
the CC OVP FETs are enabled. This leads to a small ~400us time window where the CC pin can float up above
the SRC.RD voltage threshold because the CC OVP FETs are still too resistive for the source to detect RD from
the USB-PD controller. If the tSRCDisconnect debounce time of the USB Type-C source is less than ~400us, this
could cause a USB Type-C disconnect for the source port during the dead battery boot-up event. Many USB
Type-C Sources do not have a tSRCDisconnect debounce time less than ~400us; however, the USB Type-C
spec allows the tSRCDisconnect time to be as low as 0ms, so some USB Type-C sources may have a
tSRCDisconnect debounce time that is less than ~400us. TPD6S300A solves this problem. When the
TPD6S300A is first powered (VPWR pin goes from 0V to 3.3V), TPD6S300A waits for its CC OVP FETs to be
completely ON before it removes its RD dead battery resistors. This guarantees that an RD resistor will always
be present on the CC line during the dead battery boot-up, and that the USB Type-C source''s CC voltage will
always stay in the SRC.RD range; therefore, even if a source had a tSRCDisconnect debounce time of 0ms, it
will remain connected. See图32 for an oscilloscope capture of TPD6S300A''s proper dead battery boot-up
behavior.
8.3.5.2 USB Type-C Port Stays Connected during an IEC 61000-4-2 ESD Strike
The TPD6S300A will also make sure the USB Type-C ports stay connected, even during an IEC 61000-4-2 ESD
strike, whereas the TPD6S300 has the potential to cause a USB Type-C port disconnect during an IEC 61000-4-
2 ESD strike. In TPD6S300, in some PCB layouts an IEC 61000-4-2 ESD strike would cause TPD6S300 to go
into the OVP state. In TPD6S300, the CC OVP recovery time was 21ms minimum. This means that if an OVP
happened in TPD6S300, a USB-C disconnect was guaranteed to happen, because the maximum USB Type-C
port disconnect time for sources and sinks is 20ms max in the USB Type-C specification. However, in
TPD6S300A, the CC OVP recovery time is 0.93ms typical. For TPD6S300A, the OVP FET will turn back ON
much faster than a sinks minimum disconnect time, which is 10ms. So even if an IEC 61000-4-2 ESD strike
causes an OVP in TPD6S300A, the new CC OVP FET recovery time of 0.93ms will not cause a disconnect on
the USB Type-C port for a sink.
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Feature Description (接接下下页页)
(1) This row describes the state of the device while still in OVP after the IEC ESD strike which put the device into OVP is over, and the
voltages on the C_CCx and C_SBUx pins have returned to their normal voltage levels.
For a source port connected to a sink with a TPD6S300A, if an IEC 61000-4-2 ESD strike occurs that causes an
OVP event, even an OVP recovery time of 0.93ms could cause a disconnect, because for source USB Type-C
ports, they have a minimum disconnect time of 0ms in the USB Type-C specification. So the CC OVP FET in
TPD6S300A would open up and hide the PD controllers RD for 0.93ms, causing a potential for a disconnect on
the source USB Type-C port. To solve this problem, TPD6S300A turns on its dead battery RD resistor in an OVP
event caused by an IEC 61000-4-2 ESD strike while the CC OVP FET is OFF. This makes it so even during this
OVP event caused by IEC ESD, the source port connected to the sink port with TPD6S300A will always see an
RD resistor. Therefore, even if the source port has an extremely low tSrcDisconnect time close to 0ms, it will
remain connected because an RD resistor is always present on its CC pin.
8.3.6 3-mm × 3-mm WQFN Package
The TPD6S300A comes in a small, 3-mm × 3-mm WQFN package, greatly reducing the size of implementing a
similar protection solution discretely. The WQFN package allows support for a wider range of PCB designs.
8.4 Device Functional Modes
表1 describes all of the functional modes for the TPD6S300A. The "X" in the below table are "do not care"
conditions, meaning any value can be present within the absolute maximum ratings of the datasheet and
maintain that functional mode. Also note the D1 and D2 pins are not listed, because these pins have IEC ESD
protection diodes that are always present, regardless of whether the device is powered and regardless of the
conditions on any of the other pins.
表表1. Device Mode Table
Device Mode Table Inputs Outputs
MODE VPWR C_CCx C_SBUx RPD_Gx TJ FLT CC FETs SBU FETs
Normal
Operating
Conditions
Unpowered,
no dead
battery
support
Unpowered,
dead battery
support
Powered on >UVLO
Fault
Conditions
Thermal
shutdown >UVLO X X
X, forced
OFF >TSD
Low (Fault
Asserted) OFF OFF
CC over
voltage
condition
>UVLO >OVP X X, forcedOFF
SBU over
voltage
condition
>UVLO X >OVP X, forcedOFF
IEC ESD
generated
over voltage
condition(1)
>UVLO X X
RD ON if
RPD_Gx is
shorted to
C_CCx
TPD6S300A
CC2 CC1SBU1 VBUSSBU2DP_TDM_TDP_BDM_B
TPS65982
PP_5V
LDO_3V3
VBUS_SINK
EC
Battery
Battery
Charger
DC/DC
VBUS_SRCVCONN
C_SBU2 C_SBU1 C_CC2 C_CC1
SBU2 SBU1 CC2 CC1
D1
D2
N.C.
N.C.
VPWR
/FLT
VBIAS C
VBIAS
CVPWR
RPD_G1
RPD_G2
R/FLT
VBUS
C_CC2 C_CC1C_SBU2 C_SBU1DP_TDM_TDP_BDM_B
To EC or 82
PP_CABLEAUX_PAUX_NDPDMI2C
USB_DP
Controller
USB_DP
Controller
HV_GATE1
HV_GATE2
CCC1CCC2
N.C. N.C.
21
TPD6S300A
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9 Application and Implementation
注注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPD6S300A provides 4-channels of Short-to-VBUS overvoltage protection for the CC1, CC2, SBU1, and
SBU2 pins of the USB Type-C connector, and 6-channels of IEC ESD protection for the CC1, CC2, SBU1,
SBU2, DP, and DM pins of the USB Type-C connector. Care must be taken to insure that the TPD6S300A
provides adequate system protection as well as insuring that proper system operation is maintained. The
following application example explains how to properly design the TPD6S300A into a USB Type-C system.
9.2 Typical Application
图图30. TPD6S300A Typical Application Diagram
22
TPD6S300A
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Typical Application (接接下下页页)
图图31. TPD6S300A Reference Schematic
9.2.1 Design Requirements
In this application example we study the protection requirements for a full-featured USB Type-C DRP Port, fully
equipped with USB-PD, USB2.0, USB3.0, Display Port, and 100 W charging. The TPS65982 is used to easily
enable a full-featured port with a single chip solution. In this application, all the pins of the USB Type-C connector
are utilized. Both the CC and SBU pins are susceptible to shorting to the VBUS pin. With 100 W charging, VBUS
operates at 20 V, requiring the CC and SBU pins to tolerate 20-VDC. Additionally, the CC, SBU, and USB2.0 pins
require IEC system level ESD protection. With these protection requirements present for the USB Type-C
connector, the TPD6S300A is utilized. The TPD6S300A is a single chip solution that provides all the required
protection for the low speed and USB2.0 pins in the USB Type-C connector.
表2 lists the TPD6S300A design parameters.
表表2. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
VBUS nominal operating voltage 20 V
Short-to-VBUS tolerance for the CC and SBU pins 24 V
23
TPD6S300A
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表表2. Design Parameters (接接下下页页)
DESIGN PARAMETER EXAMPLE VALUE
VBIAS nominal capacitance 0.1 μF
Dead battery charging 100 W
Maximum ambient temperature requirement 85°C
9.2.2 Detailed Design Procedure
9.2.2.1 VBIAS Capacitor Selection
As noted in the Recommended Operating Conditions table, a minimum of 35-VBUS rated capacitor is required for
the VBIAS pin, and a 50-VBUS capacitor is recommended. The VBIAS capacitor is in parallel with the central IEC
diode clamp integrated inside the TPD6S300A. A forward biased hiding diode connects the VBIAS pin to the
C_CCx and C_SBUx pins. Therefore, when a Short-to-VBUS event occurs at 20 V, 20-VBUS minus a forward
biased diode drop is exposed to the VBIAS pin. Additionally, during the short-to-VBUS event, ringing can occur
almost double the settling voltage of 20 V, allowing a potential 40 V to be exposed to the C_CCx and C_SBUx
pins. However, the internal IEC clamps limit the voltage exposed to the C_CCx and C_SBUx pins to around 30
V. Therefore, at least 35-VBUS capacitor is required to insure the VBIAS capacitor does not get destroyed during
Short-to-VBUS events.
A 50-V, X7R capacitor is recommended, however. This is to further improve the derating performance of the
capacitors. When the voltage across a real capacitor is increased, its capacitance value derates. The more the
capacitor derates, the greater than 2x ringing can occur in the short-to-VBUS RLC circuit. 50-V X7R capacitors
have great derating performance, allowing for the best short-to-VBUS performance of the TPD6S300A.
Additionally, the VBIAS capacitor helps pass IEC 61000-4-2 ESD strikes. The more capacitance present, the
better the IEC performance. So the less the VBIAS capacitor derates, the better the IEC performance.表3
shows real capacitors recommended to achieve the best performance with the TPD6S300A.
表表3. Design Parameters
CAPACITOR SIZE PART NUMBER
0402 CC0402KRX7R9BB104
0603 GRM188R71H104KA93D
9.2.2.2 Dead Battery Operation
For this application, we want to support 100-W dead battery operation; when the laptop is out of battery, we still
want to charge the laptop at 20 V and 5 A. This means that the USB PD Controller must receive power in dead
battery mode. The TPS65982 has its own built in LDO in order to supply the TPS65982 power from VBUS in a
dead battery condition. The TPS65982 can also provide power to its flash during this condition through its
LDO_3V3 pin.
The OVP FETs of the TPD6S300A remain OFF when it is unpowered in order to insure in a dead battery
situation proper protection is still provided to the PD controller in the system, in this case the TPS65982.
However, when the OVP FETs are OFF, this isolates the TPS65982s dead battery resistors from the USB Type-
C ports CC pins. A USB Type-C power adaptor must see the RD pull-down dead battery resistors on the CC pins
or it does not provide power on VBUS. Since the TPS65982s dead battery resistors are isolated from the USB
Type-C connector''s CC pins, the built-in, dead battery resistors of the TPD6S300A must be connected. Short the
RPD_G1 pin to the C_CC1 pin, and short the RPD_G2 pin to the C_CC2 pin.
Once the power adaptor sees the dead battery resistors of the TPD6S300A, it applies 5 V on the VBUS pin. This
provides power to the TPS65982, turning the PD controller on, and allowing the battery to begin to charge.
However, this application requires 100 W charging in dead battery mode, so VBUS at 20 V and 5 A is required.
USB PD negotiation is required to accomplish this, so the TPS65982 needs to be able to communicate on the
CC pins. This means the TPD6S300A needs to be turned on in dead battery mode as well so the TPS65982s
PD controller can be exposed to the CC lines. To accomplish this, it is critical that the TPD6S300A is powered by
the TPS65982s internal LDO, the LDO_3V3 pin. This way, when the TPS65982 receives power on VBUS, the
TPD6S300A is turned on simultaneously.
24
TPD6S300A
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It is critical that the TPS65982''s dead battery resistors are also connected to its CC pins for dead battery
operation. Short the TPS65982s RPD_G1 pin to its C_CC1 pin, and its RPD_G2 pin to its C_CC2 pin. It is critical
that the TPS65982s dead battery resistors are present; once the TPD6S300A receives power, turns on its OVP
FETs and then removes its dead battery RD resistor, TPS65982''s RD pull-down resistors must be present on the
CC line in order to guarantee the power adaptor stays connected. If RD is not present the power adaptor will
eventually interpret this as a disconnect and remove VBUS.
Also, it is important that the TPS65982''s dead battery resistors are present so it properly boots up in dead
battery operation with the correct voltages on its CC pins.
Once this process has occurred, the TPS65982 can start negotiating with the power adaptor through USB PD for
higher power levels, allowing 100-W operation in dead battery mode.
For more information on the TPD6S300A dead battery operation, see the CC Dead Battery Resistors Integrated
for Handling the Dead Battery Use Case in Mobile Devices section of the datasheet.
9.2.2.3 CC Line Capacitance
USB PD has a specification for the total amount of capacitance that is required for proper USB PD BMC
operation on the CC lines. The specification from section 5.8.6 of the USB PD Specification is given below in表
4.
表表4. USB PD cReceiver Specification
NAME DESCRIPTION MIN MAX UNIT COMMENT
cReceiver CC receiver capacitance 200 600 pF
The DFP or UFP system shall have
capacitance within this range when
not transmitting on the line
Therefore, the capacitance on the CC lines must stay in between 200 pF and 600 pF when USB PD is being
used. Therefore, the combination of capacitances added to the system by the TPS65982, the TPD6S300A, and
any external capacitor must fall within these limits.表5 shows the analysis involved in choosing the correct
external CC capacitor for this system, and shows that an external CC capacitor is required.
表表5. CC Line Capacitor Calculation
CC Capacitance MIN MAX UNIT COMMENT
CC line target capacitance 200 600 pF From the USB PD Specification section
TPS65982 capacitance 70 120 pF From the TPS65982 Datasheet
TPD6S300A capacitance 60 120 pF From the Electrical Characteristics table.
Proposed capacitor GRM033R71E221KA01D 110 330 pF
CAP, CERM, 220 pF, 25 V, ±10%, X7R,
0201 (For min and max, assume ±50%
capacitance change with temperature and
voltage derating to be overly conservative)
TPS65982 + TPD6S300A + GRM033R71E221KA01D 240 570 pF Meets USB PD cReceiver specification
9.2.2.4 Additional ESD Protection on CC and SBU Lines
If additional IEC ESD protection is desired to be placed on either the CC or SBU lines, it is important that high-
voltage ESD protection diodes be used. The maximum DC voltage that can be seen in USB PD is 21-VBUS, with
21.5 V allowed during voltage transitions. Therefore, an ESD protection diode must have a reverse stand off
voltage higher than 21.5 V in order to guarantee the diode does not breakdown during a short-to-VBUS event and
have large amounts of current flowing through it indefinitely, destroying the diode. A reverse stand off voltage of
24 V is recommended to give margin above 21.5 V in case USB Type-C power adaptors are released in the
market which break the USB Type-C specification.
Furthermore, due to the fact that the Short-to-VBUS event applies a DC voltage to the CC and SBU pins, a deep-
snap-back diode cannot be used unless its minimum trigger voltage is above 42 V. During a Short-to-VBUS event,
RLC ringing of up to 2x the settling voltage can be exposed to CC and SBU, allowing for up to 42 V to be
exposed. Furthermore, if any capacitor derates on the CC or SBU line, greater than 2x ringing can occur. Since
this ringing is hard to bound, it is recommended to not use deep-snap-back diodes. If the deep-snap-back diode
triggers during the short-to-VBUS hot-plug event, it begins to operate in its conduction region. With a 20-VBUS
source present on the CC or SBU line, this allows the diode to conduct indefinitely, destroying the diode.
25
TPD6S300A
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9.2.2.5 FLT Pin Operation
Once a Short-to-VBUS occurs on the C_CCx or C_SBUx pins, the FLT pin is asserted in 20 μs (typical) so the PD
controller can be notified quickly. If VBUS is being shorted to CC or SBU, it is recommended to respond to the
event by forcing a detach in the USB PD controller to remove VBUS from the port. Although the USB Type-C port
using the TPD6S300A is not damaged, as the TPD6S300A provides protection from these events, the other
device connected through the USB Type-C Cable or any active circuitry in the cable can be damaged. Although
shutting the VBUS off through a detach does not guarantee it stops the other device or cable from being
damaged, it can mitigate any high current paths from causing further damage after the initial damage takes
place. Additionally, even if the active cable or other device does have proper protection, the short-to-VBUS event
may corrupt a configuration in an active cable or in the other PD controller, so it is best to detach and reconfigure
the port.
9.2.2.6 How to Connect Unused Pins
If either the RPD_Gx pins or any of the Dx pins are unused in a design, they must be connected to GND.
9.2.3 Application Curves
图图32. TPD6S300A Turning On in Dead Battery
Mode with RD on CC1
图图33. TPD6S300A Protecting the TPS65982 During
a Short-to-VBUS Event
26
TPD6S300A
ZHCSIE6 –JUNE 2018 www.ti.com.cn
版权? 2018, Texas Instruments Incorporated
10 Power Supply Recommendations
The VPWR pin provides power to all the circuitry in the TPD6S300A. It is recommended a 1-μF decoupling
capacitor is placed as close as possible to the VPWR pin. If USB PD is desired to be operated in dead battery
conditions, it is critical that the TPD6S300A share the same power supply as the PD controller in dead battery
boot-up (such as sharing the same dead battery LDO). See the CC Dead Battery Resistors Integrated for
Handling the Dead Battery Use Case in Mobile Devices section for more details.
C_
CC
1
C_
CC
2
VB
IAS
C_
SB
U2
C_
SB
U1
CC
2
CC
1
SB
U2 SBU1
RPD_G1
RPD_G2
/FLT
VPWR N.C.
N.C
D2
D1
GN
D
GND GND
CC1
CC2
SBU1
SBU2
D+
D-
D+
D-
VBUS
VBUS
VBUS
VBUS
TX1-
TX1+
TX2+
TX2-
RX1-
RX1+
RX2+
RX2-
GND
GND
GND
GND
27
TPD6S300A
www.ti.com.cn ZHCSIE6 –JUNE 2018
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11 Layout
11.1 Layout Guidelines
Proper routing and placement is important to maintain the signal integrity the USB2.0, SBU, CC line signals. The
following guidelines apply to the TPD6S300A:
? Place the bypass capacitors as close as possible to the VPWR pin, and ESD protection capacitor as close as
possible to the VBIAS pin. Capacitors must be attached to a solid ground. This minimizes voltage disturbances
during transient events such as short-to-VBUS and ESD strikes.
? The USB2.0 and SBU lines must be routed as straight as possible and any sharp bends must be minimized.
Standard ESD recommendations apply to the C_CC1, C_CC2, C_SBU1, C_SBU2, D1, and D2 pins as well:
? The optimum placement for the device is as close to the connector as possible:
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TPD6S300A and the connector.
? Route the protected traces as straight as possible.
? Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
? It is best practice to not via up to the D1 and D2 pins from a trace routed on another layer. Rather, it is better
to via the trace to the layer with the Dx pin, and to continue that trace on that same layer. See the ESD
Protection Layout Guide application report, section 1.3 for more details.
11.2 Layout Example
图图34. TPD6S300A Typical Layout
28
TPD6S300A
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版权? 2018, Texas Instruments Incorporated
12器器件件和和文文档档支支持持
12.1文文档档支支持持
12.1.1相相关关文文档档
请参阅如下相关文档：
《TPD6S300评估模块用户指南》
12.2接接收收文文档档更更新新通通知知
要接收文档更新通知，请导航至TI.com.cn上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3社社区区资资源源
下列链接提供到TI社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成TI技术规范，
并且不一定反映TI的观点；请参阅TI的《使用条款》。
TI E2E?在在线线社社区区TI的的工工程程师师对对工工程程师师(E2E)社社区区。。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设设计计支支持持TI参参考考设设计计支支持持可帮助您快速查找有帮助的E2E论坛、设计支持工具以及技术支持的联系信息。
12.4商商标标
E2E is a trademark of Texas Instruments.
USB Type-C is a trademark of USB Implementers Forum.
All other trademarks are the property of their respective owners.
12.5静静电电放放电电警警告告
这些装置包含有限的内置ESD保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止MOS门极遭受静电损
伤。
12.6术术语语表表
SLYZ022 — TI术语表。
这份术语表列出并解释术语、缩写和定义。
13机机械械、、封封装装和和可可订订购购信信息息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPD6S300ARUKR ACTIVE WQFN RUK 20 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 6S30A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI''s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI''s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
www.ti.com
PACKAGE OUTLINE
C
SEE TERMINAL
DETAIL
20X
0.25
0.15
1.7 0.05
20X
0.5
0.3
0.8 MAX
(DIM A) TYP
OPT 02 SHOWN
0.05
0.00
16X 0.4
4X
1.6
A
3.1
2.9
B
3.1
2.9
0.25
0.15
0.5
0.3
WQFN - 0.8 mm max heightRUK0020B
PLASTIC QUAD FLATPACK - NO LEAD
4222676/A 02/2016
DIMENSION A
OPTION 01 (0.1)
OPTION 02 (0.2)
PIN 1 INDEX AREA
0.08 C
SEATING PLANE
1
5
11
15
6 10
20 16
(OPTIONAL)
PIN 1 ID
0.1 C A B
0.05
EXPOSED
THERMAL PAD
21
SYMM
SYMM
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 4.000
DETAIL
OPTIONAL TERMINAL
TYPICAL
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
20X (0.2)
20X (0.6)
( ) TYP
VIA
0.2
16X (0.4)
(2.8)
(2.8)
(0.6)
TYP
( 1.7)
(R )
TYP
0.05
WQFN - 0.8 mm max heightRUK0020B
PLASTIC QUAD FLATPACK - NO LEAD
4222676/A 02/2016
SYMM
1
5
6 10
11
15
1620
SYMM
LAND PATTERN EXAMPLE
SCALE:20X
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
21
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
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EXAMPLE STENCIL DESIGN
20X (0.6)
20X (0.2)
16X (0.4)
(2.8)
(2.8)
4X ( 0.75)
(0.47)
TYP
(0.47) TYP
(R ) TYP0.05
WQFN - 0.8 mm max heightRUK0020B
PLASTIC QUAD FLATPACK - NO LEAD
4222676/A 02/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
21
SYMM
METAL
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 21:
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
SYMM
1
5
6 10
11
15
1620
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