Ultracompact, 1.5 A Thermoelectric Cooler
(TEC) Controller
Data Sheet
ADN8834
Rev. B Document Feedback
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FEATURES
Patented high efficiency single inductor architecture
Integrated low R
DSON
MOSFETs for the TEC controller
TEC voltage and current operation monitoring
No external sense resistor required
Independent TEC heating and cooling current limit settings
Programmable maximum TEC voltage
2.0 MHz PWM driver switching frequency
External synchronization
Two integrated, zero drift, rail-to-rail chopper amplifiers
Capable of NTC or RTD thermal sensors
2.50 V reference output with 1% accuracy
Temperature lock indicator
Available in a 25-ball, 2.5 mm × 2.5 mm WLCSP or in a
24-lead, 4 mm × 4 mm LFCSP
APPLICATIONS
TEC temperature control
Optical modules
Optical fiber amplifiers
Optical networking systems
Instruments requiring TEC temperature control
FUNCTIONAL BLOCK DIAGRAM
TEC CURRENT
AND VOLTAGE
SENSE AND LIMIT
CONTROLLER
LINEAR
POWER
STAGE
TEC DRIVER
PWM
POWER
STAGE
OSCILLATOR
VOLTAGE
REFERENCE
OUT1
VLIM/
SD VTECILIM PVINITEC
EN/SYVREF
LDR
SFB
IN2P
IN2N
IN1P
IN1N
OUT2
SW
PGNDx
VDD
AGND
ERROR
AMP
COMP
AMP
12954-
001
Figure 1.
GENERAL DESCRIPTION
The ADN8834
1
is a monolithic TEC controller with an integrated
TEC controller. It has a linear power stage, a pulse-width
modulation (PWM) power stage, and two zero-drift, rail-to-rail
operational amplifiers. The linear controller works with the PWM
driver to control the internal power MOSFETs in an H-bridge
configuration. By measuring the thermal sensor feedback
voltage and using the integrated operational amplifiers as a
proportional integral differential (PID) compensator to condition
the signal, the ADN8834 drives current through a TEC to settle
the temperature of a laser diode or a passive component attached
to the TEC module to the programmed target temperature.
The ADN8834 supports negative temperature coefficient (NTC)
thermistors as well as positive temperature coefficient (PTC)
resistive temperature detectors (RTD). The target temperature is
set as an analog voltage input either from a digital-to-analog
converter (DAC) or from an external resistor divider.
The temperature control loop of the ADN8834 is stabilized by
PID compensation utilizing the built in, zero drift chopper
amplifiers. The internal 2.50 V reference voltage provides a 1%
accurate output that is used to bias a thermistor temperature
sensing bridge as well as a voltage divider network to program
the maximum TEC current and voltage limits for both the heating
and cooling modes. With the zero drift chopper amplifiers,
extremely good long-term temperature stability is maintained via
an autonomous analog temperature control loop.
Table 1. TEC Family Models
Device No. MOSFET Thermal Loop Package
ADN8831 Discrete Digital/analog LFCSP (CP-32-7)
ADN8833 Integrated Digital WLCSP (CB-25-7),
LFCSP (CP-24-15)
ADN8834 Integrated Digital/analog WLCSP (CB-25-7),
LFCSP (CP-24-15)
1
Product is covered by U.S. Patent No. 6,486,643.
ADN8834 Data Sheet
Rev. B | Page 2 of 27
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Detailed Functional Block Diagram ............................................ 12
Theory of Operation ...................................................................... 13
Analog PID Control ................................................................... 14
Digital PID Control .................................................................... 14
Powering the Controller ............................................................ 14
Enable and Shutdown ................................................................ 15
Oscillator Clock Frequency ....................................................... 15
Temperature Lock Indicator (LFCSP Only) ........................... 15
Soft Start on Power-Up .............................................................. 15
TEC Voltage/Current Monitor ................................................. 16
Maximum TEC Voltage Limit .................................................. 16
Maximum TEC Current Limit ................................................. 17
Applications Information .............................................................. 18
Signal Flow .................................................................................. 18
Thermistor Setup ........................................................................ 18
Thermistor Amplifier (Chopper 1) .......................................... 19
PID Compensation Amplifier (Chopper 2) ............................ 19
MOSFET Driver Amplifiers ...................................................... 20
PWM Output Filter Requirements .......................................... 20
Input Capacitor Selection .......................................................... 21
Power Dissipation....................................................................... 21
PCB Layout Guidelines .................................................................. 23
Block Diagrams and Signal Flow ............................................. 23
Guidelines for Reducing Noise and Minimizing Power Loss .... 23
Example PCB Layout Using Two Layers ................................. 24
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
9/18—Rev. A to Rev. B
Added Patent Information............................................................... 1
8/15—Rev. 0 to Rev. A
Added 24-Lead LFCSP ....................................................... Universal
Changes to Features Section and Table 1 ...................................... 1
Changes to Table 2 ............................................................................ 3
Changes to Table 3 ............................................................................ 6
Added Figure 3; Renumbered Sequentially .................................. 7
Changes to Figure 13 ........................................................................ 9
Changes to Figure 23 and Figure 24 ............................................. 11
Changes to Figure 25 ...................................................................... 12
Changes to Powering the Controller Section and Figure 27
Caption ............................................................................................ 14
Change to Soft Start on Power-Up Section ................................. 15
Change to Figure 33 ....................................................................... 18
Changes to Table 7 .......................................................................... 21
Added Table 8; Renumbered Sequentially .................................. 21
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 27
4/15—Revision 0: Initial Version
Data Sheet ADN8834
Rev. B | Page 3 of 27
SPECIFICATIONS
V
IN
= 2.7 V to 5.5 V, T
J
= ?40°C to +125°C for minimum/maximum specifications, and T
A
= 25°C for typical specifications, unless
otherwise noted.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Driver Supply Voltage V
PVIN
2.7 5.5 V
Controller Supply Voltage V
VDD
2.7 5.5 V
Supply Current I
VDD
PWM not switching 3.3 5 mA
Shutdown Current I
SD
EN/SY = AGND or VLIM/SD = AGND 350 700 μA
Undervoltage Lockout (UVLO) V
UVLO
V
VDD
rising 2.45 2.55 2.65 V
UVLO Hysteresis UVLO
HYST
80 90 100 mV
REFERENCE VOLTAGE V
VREF
I
VREF
= 0 mA to 10 mA 2.475 2.50 2.525 V
LINEAR OUTPUT
Output Voltage V
LDR
I
LDR
= 0 A
Low 0 V
High V
PVIN
V
Maximum Source Current I
LDR_SOURCE
T
J
= ?40°C to +105°C 1.5 A
T
J
= ?40°C to +125°C 1.2 A
Maximum Sink Current I
LDR_SINK
T
J
= ?40°C to +105°C 1.5 A
T
J
= ?40°C to +125°C 1.2 A
On Resistance I
LDR
= 0.6 A
P-MOSFET R
DS_PL(ON)
W LC S P, V
PVIN
= 5.0 V 35 50 m?
W LC S P, V
PVIN
= 3.3 V 44 60 m?
LFCSP, V
PVIN
= 5.0 V 50 65 m?
LFCSP, V
PVIN
= 3.3 V 55 75 m?
N-MOSFET R
DS_NL(ON)
W LC S P, V
PVIN
= 5.0 V 31 50 m?
W LC S P, V
PVIN
= 3.3 V 40 55 m?
LFCSP, V
PVIN
= 5.0 V 45 70 m?
LFCSP, V
PVIN
= 3.3 V 50 80 m?
Leakage Current
P-MOSFET I
LDR_P_LKG
0.1 10 μA
N-MOSFET I
LDR_N_LKG
0.1 10 μA
Linear Amplifier Gain A
LDR
40 V/V
LDR Short-Circuit Threshold I
LDR_SH_GNDL
LDR short to PGNDL, enter hiccup 2.2 A
I
LDR_SH_PVIN(L)
LDR short to PVIN, enter hiccup ?2.2 A
Hiccup Cycle T
HICCUP
15 ms
PWM OUTPUT
Output Voltage V
SFB
I
SFB
= 0 A V
Low 0.06 × V
PVIN
V
High 0.93 × V
PVIN
V
Maximum Source Current I
SW_SOURCE
T
J
= ?40°C to +105°C 1.5 A
T
J
= ?40°C to +125°C 1.2 A
Maximum Sink Current I
SW_SINK
T
J
= ?40°C to +105°C 1.5 A
T
J
= ?40°C to +125°C 1.2 A
On Resistance I
SW
= 0.6 A
P-MOSFET R
DS_PS(ON)
W LC S P, V
PVIN
= 5.0 V 47 65 m?
W LC S P, V
PVIN
= 3.3 V 60 80 m?
LFCSP, V
PVIN
= 5.0 V 60 80 m?
LFCSP, V
PVIN
= 3.3 V 70 95 m?
ADN8834 Data Sheet
Rev. B | Page 4 of 27
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
N-MOSFET R
DS_NS(ON)
W LC S P, V
PVIN
= 5.0 V 40 60 m?
W LC S P, V
PVIN
= 3.3 V 45 65 m?
LFCSP, V
PVIN
= 5.0 V 45 75 m?
LFCSP, V
PVIN
= 3.3 V 55 85 m?
Leakage Current
P-MOSFET I
SW_P_LKG
0.1 10 μA
N-MOSFET I
SW_N_LKG
0.1 10 μA
SW Node Rise Time
1
t
SW_R
C
SW
= 1 nF 1 ns
PWM Duty Cycle
2
D
SW
6 93 %
SFB Input Bias Current I
SFB
1 2 μA
PWM OSCILLATOR
Internal Oscillator Frequency f
OSC
EN/SY high 1.85 2.0 2.15 MHz
EN/SY Input Voltage
Low V
EN/SY_ILOW
0.8 V
High V
EN/SY_IHIGH
2.1 V
External Synchronization Frequency f
SYNC
1.85 3.25 MHz
Synchronization Pulse Duty Cycle D
SYNC
10 90 %
EN/SY Rising to PWM Rising Delay t
SYNC_PWM
50 ns
EN/SY to PWM Lock Time t
SY_LOCK
Number of SYNC cycles 10 Cycles
EN/SY Input Current I
EN/SY
0.3 0.5 μA
Pull-Down Current 0.3 0.5 μA
ERROR/COMPENSATION AMPLIFIERS
Input Offset Voltage V
OS1
V
CM1
= 1.5 V, V
OS1
= V
IN1P
? V
IN1N
10 100 μV
V
OS2
V
CM2
= 1.5 V, V
OS2
= V
IN2P
? V
IN2N
10 100 μV
Input Voltage Range V
CM1
, V
CM2
0 V
VDD
V
Common-Mode Rejection Ratio (CMRR) CMRR
1
, CMRR
2
V
CM1
, V
CM2
= 0.2 V to V
VDD
? 0.2 V 120 dB
Output Voltage
High V
OH1
, V
OH2
V
VDD
?
0.04
V
Low V
OL1
, V
OL2
10 mV
Power Supply Rejection Ratio (PSRR) PSRR
1
, PSRR
2
120 dB
Output Current I
OUT1
, I
OUT2
Sourcing and sinking 5 mA
Gain Bandwidth Product
1
GBW
1
, GBW
2
V
OUT1
,V
OUT2
= 0.5 V to V
VDD
? 1 V 2 MHz
TEC CURRENT LIMIT
ILIM Input Voltage Range
Cooling V
ILIMC
1.3 V
VREF
?
0.2
V
Heating V
ILIMH
0.2 1.2 V
Current-Limit Threshold
Cooling V
ILIMC_TH
V
ITEC
= 0.5 V 1.98 2.0 2.02 V
Heating V
ILIMH_TH
V
ITEC
= 2 V 0.48 0.5 0.52 V
ILIM Input Current
Heating I
ILIMH
?0.2 +0.2 μA
Cooling I
ILIMC
Sourcing current 37.5 40 42.5 μA
Cooling to Heating Current Detection
Threshold
I
COOL_HEAT_TH
40 mA
TEC VOLTAGE LIMIT
Voltage Limit Gain A
VLIM
(V
DRL
? V
SFB
)/V
VLIM
2 V/V
VLIM/SD Input Voltage Range
1
V
VLIM
0.2 V
VDD
/2 V
VLIM/SD Input Current
Cooling I
ILIMC
V
OUT2
< V
VREF
/2 ?0.2 +0.2 μA
Heating I
ILIMH
V
OUT2
> V
VREF
/2, sinking current 8 10 12.2 μA
Data Sheet ADN8834
Rev. B | Page 5 of 27
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
TEC CURRENT MEASUREMENT (WLCSP)
Current Sense Gain R
CS
V
PVIN
= 3.3 V 0.525 V/A
V
PVIN
= 5 V 0.535 V/A
Current Measurement Accuracy I
LDR_ERROR
700 mA ≤ I
LDR
≤ 1.5 A, V
PVIN
= 3.3 V ?10 +10 %
800 mA ≤ I
LDR
≤ 1.5 A, V
PVIN
= 5 V ?10 +10 %
ITEC Voltage Accuracy V
ITEC_@_700_mA
V
PVIN
= 3.3 V, cooling, V
VREF
/2 +
I
LDR
× R
CS
1.597 1.618 1.649 V
V
ITEC_@_?700_mA
V
PVIN
= 3.3 V, heating, V
VREF
/2 ?
I
LDR
× R
CS
0.846 0.883 0.891 V
V
ITEC_@_800_mA
V
PVIN
= 5 V, cooling, V
VREF
/2 + I
LDR
× R
CS
1.657 1.678 1.718 V
V
ITEC_@_?800_mA
V
PVIN
= 5 V, heating, V
VREF
/2 ? I
LDR
× R
CS
0.783 0.822 0.836 V
TEC CURRENT MEASUREMENT (LFCSP)
Current Sense Gain R
CS
V
PVIN
= 3.3 V 0.525 V/A
V
PVIN
= 5 V 0.525 V/A
Current Measurement Accuracy I
LDR_ERROR
700 mA ≤ I
LDR
≤ 1 A, V
PVIN
= 3.3 V ?15 +15 %
800 mA ≤ I
LDR
≤ 1 A, V
PVIN
= 5 V ?15 +15 %
ITEC Voltage Accuracy V
ITEC_@_700_mA
V
PVIN
= 3.3 V, cooling, V
VREF
/2 + I
LDR
×
R
CS
1.374 1.618 1.861 V
V
ITEC_@_?700_mA
V
PVIN
= 3.3 V, heating, V
VREF
/2 ? I
LDR
×
R
CS
0.750 0.883 1.015 V
V
ITEC_@_800_mA
V
PVIN
= 5 V, cooling, V
VREF
/2 + I
LDR
×
R
CS
1.419 1.678 1.921 V
V
ITEC_@_?800_mA
V
PVIN
= 5 V, heating, V
VREF
/2 ? I
LDR
×
R
CS
0.705 0.830 0.955 V
ITEC Voltage Output Range V
ITEC
I
TEC
= 0 A 0 V
VREF
?
0.05
V
ITEC Bias Voltage V
ITEC
I
LDR
= 0 A 1.210 1.250 1.285 V
Maximum ITEC Output Current I
ITEC
?2 +2 mA
TEC VOLTAGE MEASUREMENT
Voltage Sense Gain A
VTEC
0.24 0.25 0.26 V/V
Voltage Measurement Accuracy V
VTEC_@_1_V
V
LDR
– V
SFB
= 1 V, V
VREF/2
+ A
VTEC
×
(V
LDR
– V
SFB
)
1.475 1.50 1.525 V
VTEC Output Voltage Range V
VTEC
0.005 2.625 V
VTEC Bias Voltage V
VTEC_B
V
LDR
= V
SFB
1.225 1.250 1.285 V
Maximum VTEC Output Current R
VTEC
?2 +2 mA
TEMPERATURE GOOD (LFCSP Only)
TMPGD Low Output Voltage V
TMPGD_LO
No load 0.4 V
TMPGD High Output Voltage V
TMPGD_HO
No load 2.0 V
TMPGD Output Low Impedance R
TMPGD_LOW
25 ?
TMPGD Output High Impedance R
TMPGD_LOW
50 ?
High Threshold V
OUT1_THH
IN2N tied to OUT2, V
IN2P
= 1.5 V 1.54 1.56 V
Low Threshold V
OUT1_THL
IN2N tied to OUT2, V
IN2P
= 1.5 V 1.40 1.46 V
INTERNAL SOFT START
Soft Start Time t
SS
150 ms
VLIM/SD SHUTDOWN
VLIM/SD Low Voltage Threshold V
VLIM/SD_THL
0.07 V
THERMAL SHUTDOWN
Thermal Shutdown Threshold T
SHDN_TH
170 °C
Thermal Shutdown Hysteresis T
SHDN_HYS
17 °C
1
This specification is guaranteed by design.
2
This specification is guaranteed by characterization.
ADN8834 Data Sheet
Rev. B | Page 6 of 27
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
PVIN to PGNDL (WLCSP) ?0.3 V to +5.75 V
PVIN to PGNDS (WLCSP) ?0.3 V to +5.75 V
PVINL to PGNDL (LFCSP) ?0.3 V to +5.75 V
PVINS to PGNDS (LFCSP) ?0.3 V to +5.75 V
LDR to PGNDL (WLCSP) ?0.3 V to V
PVIN
LDR to PGNDL (LFCSP) ?0.3 V to V
PVINL
SW to PGNDS ?0.3 V to +5.75 V
SFB to AGND ?0.3 V to V
VDD
AGND to PGNDL ?0.3 V to +0.3 V
AGND to PGNDS ?0.3 V to +0.3 V
VLIM/SD to AGND ?0.3 V to V
VDD
ILIM to AGND ?0.3 V to V
VDD
VREF to AGND ?0.3 V to +3 V
VDD to AGND ?0.3 V to +5.75 V
IN1P to AGND ?0.3 V to V
VDD
IN1N to AGND ?0.3 V to V
VDD
OUT1 to AGND ?0.3 V to +5.75 V
IN2P to AGND ?0.3 V to V
VDD
IN2N to AGND ?0.3 V to V
VDD
OUT2 to AGND ?0.3 V to +5.75 V
EN/SY to AGND ?0.3 V to V
VDD
ITEC to AGND ?0.3 V to +5.75 V
VTEC to AGND ?0.3 V to +5.75 V
Maximum Current
VREF to AGND 20 mA
OUT1 to AGND 50 mA
OUT2 to AGND 50 mA
ITEC to AGND 50 mA
VTEC to AGND 50 mA
Junction Temperature 125°C
Storage Temperature Range ?65°C to +150°C
Lead Temperature (Soldering, 10 sec) 260°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages, and is
based on a 4-layer standard JEDEC board.
Table 4.
Package Type θ
JA
θ
JC
Unit
25-Ball WLCSP 48 0.6 °C/W
24-Lead LFCSP 37 1.65 °C/W
ESD CAUTION
Data Sheet ADN8834
Rev. B | Page 7 of 27
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
A
B
C
D
E
1 2 3 4 5
VLIM/
SD
ILIM
VREF
VDD
IN2PIN1P
OUT2
AGND
IN2N
EN/SY
OUT1
ADN8834
TOP VIEW
(BALLS ON THE BOTTOM SIDE)
IN1N
ITEC
VTEC
SFB
SW
LDR
PGNDL
PVIN
PGNDSPGNDS
SW
PVIN
PGNDL
LDR
2.54mm
2.54mm
0.5mm
PITCH
12954-
002
Figure 2. WLCSP Pin Configuration (Top View)
12954-
200
2
1
3
4
5
6
18
17
16
15
14
13VREF
VDD
ILIM
VLIM/SD
OUT2
IN2N
PGNDS
SW
PVINS
PVINL
LDR
PGNDL
8 9
10 11
7
EN
/
SY
VT
EC
SF
B
ITE
C
12
P
G
NDS
AG
ND
20 1921
T
MPG
D
P
G
NDL
OU
T1
22
I
N1N
23
I
N1P
24
I
N2P
ADN8834
TOP VIEW
(Not to Scale)
NOTES
1. EXPOSED PAD. SOLDER TO THE ANALOG
GROUND PLANE ON THE BOARD.
Figure 3. LFCSP Pin Configuration (Top View)
Table 5. Pin Function Descriptions
Pin No.
Mnemonic Description WLCSP LFCSP
A1, A2 18, 19 PGNDL Power Ground of the Linear TEC Controller.
N/A
1
20 TMPGD Temperature Good Output.
A3 21 OUT1 Output of the Error Amplifier.
A4 23 IN1P Noninverting Input of the Error Amplifier.
A5 24 IN2P Noninverting Input of the Compensation Amplifier.
B1, B2 17 LDR Output of the Linear TEC Controller.
B3 22 IN1N Inverting Input of the Error Amplifier.
B4 1 IN2N Inverting Input of the Compensation Amplifier.
B5 3 VLIM/SD Voltage Limit/Shutdown. This pin sets the cooling and heating TEC voltage limits. When this pin
is pulled low, the device shuts down.
C1, C2 N/A
1
PVIN Power Input for the TEC Controller.
N/A
1
16 PVINL Power Input for the Linear TEC Driver.
N/A
1
15 PVINS Power Input for the PWM TEC Driver.
C3 11 ITEC TEC Current Output.
C4 2 OUT2 Output of the Compensation Amplifier.
C5 4 ILIM Current Limit. This pin sets the TEC cooling and heating current limits.
D1, D2 14 SW Switch Node Output of the PWM TEC Controller.
D3 9 VTEC TEC Voltage Output.
D4 8 EN/SY Enable/Synchronization. Set this pin high to enable the device. An external synchronization
clock input can be applied to this pin.
D5 5 VDD Power for the Controller Circuits.
E1, E2 12, 13 PGNDS Power Ground of the PWM TEC Controller.
E3 10 SFB Feedback of the PWM TEC Controller Output.
E4 7 AGND Signal Ground.
E5 6 VREF 2.5 V Reference Output.
N/A
1
0 EPAD Exposed Pad. Solder to the analog ground plane on the board.
1
N/A means not applicable.
ADN8834 Data Sheet
Rev. B | Page 8 of 27
TYPICAL PERFORMANCE CHARACTERISTICS
T
A
= 25°C, unless otherwise noted.
0
10
20
30
40
50
60
70
80
90
100
0 0.5 1.0 1.5
E
FFIC
IE
N
C
Y
(
%)
TEC CURRENT (A)
V
IN
= 3.3V
V
IN
= 5V
12954-
003
Figure 4. Efficiency vs. TEC Current at V
IN
= 3.3 V and 5 V in Cooling Mode
with 2 ? Load
0
10
20
30
40
50
60
70
80
90
100
0 0.5 1.0 1.5
E
FFIC
IE
N
C
Y
(
%)
TEC CURRENT (A)
V
IN
= 3.3V
V
IN
= 5V
12954-
004
Figure 5. Efficiency vs. TEC Current at V
IN
= 3.3 V and 5 V in Heating Mode
with 2 ? Load
0
10
20
30
40
50
60
70
80
90
100
E
F
F
CI
E
NCY
(
%)
LOAD = 2Ω
LOAD = 3Ω
LOAD = 4Ω
LOAD = 5Ω
12954-
105
0 0.5 1.0 1.5
TEC CURRENT (A)
Figure 6. Efficiency vs. TEC Current at V
IN
= 3.3 V with Different Loads in
Cooling Mode
0
10
20
30
40
50
60
70
80
90
100
0 1.5
E
FFIC
IE
N
C
Y
(
%)
TEC CURRENT (A)
LOAD = 2Ω
LOAD = 3Ω
LOAD = 4Ω
LOAD = 5Ω
12954-
1060.5 1.0
Figure 7. Efficiency vs. TEC Current at V
IN
= 3.3 V with Different Loads in
Heating Mode
2.7 5.04.54.03.53.0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
M
AX
I
M
UM
T
E
C CURRE
NT
(
A)
INPUT VOLTAGE AT PVIN (V)
LOAD = 2Ω
LOAD = 3Ω
LOAD = 4Ω
LOAD = 5Ω
12954-
1075.5
Figure 8. Maximum TEC Current vs. Input Voltage at PVIN (V
IN
= 3.3 V),
Without Voltage and Current Limit in Cooling Mode
2.7 5.55.04.54.03.53.0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
M
AX
I
M
UM
T
E
C CURRE
NT
(
A)
INPUT VOLTAGE AT PVIN (V)
LOAD = 2Ω
LOAD = 3Ω
LOAD = 4Ω
LOAD = 5Ω
12954-
108
Figure 9. Maximum TEC Current vs. Input Voltage at PVIN (V
IN
= 3.3 V),
Without Voltage and Current Limit in Heating Mode
Data Sheet ADN8834
Rev. B | Page 9 of 27
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
0 20 40 60 80 100 120 140 160 180 200
T
EMPO
U
T
[V
O
UT
1
] VO
LT
AG
E
E
RRO
R (
%)
TIME (Seconds)
T = 15°C
T = 25°C
T = 35°C
T = 45°C
T = 55°C
12954-
109
Figure 10. Thermal Stability over Ambient Temperature at V
IN
= 3.3 V,
V
TEMPSET
= 1 V
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
0 20 40 60 80 100 120 140 160 180 200
T
EMPO
U
T
[V
O
UT
1
] VO
LT
AG
E
E
RRO
R (
%)
TIME (Seconds)
T = 15°C
T = 25°C
T = 35°C
T = 45°C
T = 55°C
12954-
1
10
Figure 11. Thermal Stability over Ambient Temperature at V
IN
= 3.3 V,
V
TEMPSET
= 1.5 V
V
IN
= 2.7V AT NO LOAD
V
IN
= 3.3V AT NO LOAD
V
IN
= 5.5V AT NO LOAD
V
IN
= 2.7V AT 5mA LOAD
V
IN
= 3.3V AT 5mA LOAD
V
IN
= 5.5V AT 5mA LOAD
1.0
–50 0 50
AMBIENT TEMPERATURE (°C)
100 150
0.8
0.6
0.4
0.2
0
V
RE
F
E
RRO
R (
%)
–0.2
–0.4
–0.6
–0.8
–1.0
12954-
11
1
Figure 12. V
REF
Error vs. Ambient Temperature
0.20
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0 10987654321
V
RE
F
(
%)
LOAD CURRENT AT V
REF
(mA)
12954-
201
V
IN
= 3.3V, ITEC = 0A
V
IN
= 3.3V, ITEC = 0.5A, COOLING
V
IN
= 3.3V, ITEC = 0.5A, HEATING
V
IN
= 5.0V, ITEC = 0A
V
IN
= 5.0V, ITEC = 0.5A, COOLING
V
IN
= 5.0V, ITEC = 0.5A, HEATING
Figure 13. V
REF
Load Regulation
–20
–15
–10
–5
0
5
10
15
20
0 0.5 1.0 1.5
I
T
E
C CURRE
NT
RE
ADI
NG
E
RRO
R (
%)
TEC CURRENT (A)
V
IN
= 3.3V
V
IN
= 5V
12954-
010
Figure 14. ITEC Current Reading Error vs. TEC Current in Cooling Mode
–20
–15
–10
–5
0
5
10
15
20
–1.5 –1.0 –0.5 0
I
T
E
C CURRE
NT
RE
ADI
NG
E
RRO
R (
%)
TEC CURRENT (A)
V
IN
= 3.3V
V
IN
= 5V
12954-
013
Figure 15. ITEC Current Reading Error vs. TEC Current in Heating Mode
ADN8834 Data Sheet
Rev. B | Page 10 of 27
–20
–15
–10
–5
0
5
10
15
20
0.5 1.0 1.5 2.0 2.5
VT
EC
VO
LT
AG
E
RE
ADI
NG
E
RRO
R (
%)
TEC VOLTAGE (V)
V
IN
= 3.3V
V
IN
= 5V
12954-
0
1
1
Figure 16. VTEC Voltage Reading Error vs. TEC Voltage in Cooling Mode
–20
–15
–10
–5
0
5
10
15
20
–2.5 –2.0 –1.5 –1.0 –0.5
VT
EC
VO
LT
AG
E
RE
ADI
NG
E
RRO
R (
%)
TEC VOLTAGE (V)
V
IN
= 3.3V
V
IN
= 5V
12954-
014
Figure 17. VTEC Voltage Reading Error vs. TEC Voltage in Heating Mode
CH1 500mV CH2 500mV M200ms A CH4 –108mA
T –28.000ms
B
W
B
W
CH4 200mA ?
B
W
4
1
PWM (TEC–)
TEC CURRENT
LDO (TEC+)
12954-
1
18
Figure 18. Cooling to Heating Transition
4
1
CH1 500mV CH2 500mV M10ms A CH4 –8mA
T 5.4ms
B
W
B
W
CH3 300mA ?
B
W 12954-
120
PWM (TEC–)
TEC CURRENT
LDO (TEC+)
Figure 19. Zero Crossing TEC Current Zoom in from Heating to Cooling
4
1
CH1 500mV CH2 500mV M10ms A CH4 12mA
T 5.4ms
B
W
B
W
CH3 200mA ?
B
W
PWM (TEC–)
TEC CURRENT
LDO (TEC+)
12954-
120
Figure 20. Zero Crossing TEC Current Zoom in from Cooling to Heating
EN
TEC CURRENT
LDO (TEC–)
PWM (TEC+)
12954-
121
CH1 1V CH2 1V M20.0ms A CH3 800mV
T 40ms
B
W
B
W CH3 2V
B
W
CH4 500mA ?
B
W
3
4
1
Figure 21. Typical Enable Waveforms in Cooling Mode,
V
IN
= 3.3 V, Load = 2 ?, TEC Current = 1 A
Data Sheet ADN8834
Rev. B | Page 11 of 27
12954-
122
3
4
2
EN
TEC CURRENT
LDO (TEC+)
PWM (TEC–)
CH1 1V CH2 1V M20.0ms A CH3 800mV
T 40ms
B
W
B
W CH3 2V
B
W
CH4 500mA ?
B
W
Figure 22. Typical Enable Waveforms in Heating Mode,
V
IN
= 3.3 V, Load = 2 ?, TEC Current = 1 A
12954-
202
3
1
2
SW
LDO (TEC+)
PWM (TEC–)
CH1 20mV
B
W
CH2 20mV
B
W
M400ns A
2.50GS/s
CH3 1.00V
T 0.0sCH3 2.0V
B
W
Figure 23. Typical Switch and Voltage Ripple Waveforms in Cooling Mode
V
IN
= 3.3 V, Load = 2 ?, TEC Current = 1 A
12954-
203
3
1
2
SW
LDO (TEC+)
PWM (TEC–)
CH1 20mV
B
W
CH2 20mV
B
W
M400ns A
2.50GS/s
CH3 1.00V
T 0.0sCH3 2.0V
B
W
Figure 24. Typical Switch and Voltage Ripple Waveforms in Heating Mode,
V
IN
= 3.3 V, Load = 2 ?, TEC Current = 1 A
ADN8834 Data Sheet
Rev. B | Page 12 of 27
DETAILED FUNCTIONAL BLOCK DIAGRAM
V
B
LINEAR
AMPLIFIER
V
C
20kΩ
ITEC
1.25V1.25V1.25V
5kΩ
VTEC
20kΩ20kΩ
5kΩ
SFB
IN2P
IN2N
OUT2
IN1P
IN1N
OUT1
1.25V
VLIM/SD
V
C
V
B
= 2.5V AT VDD > 4.0V
V
B
= 1.5V AT VDD < 4.0V
BAND GAP
VOLTAGE
REFERENCE
V
B
VREF
2.5V
VDD
AGND
TEC VOLTAGE
LIMIT AND INTERNAL
SOFT START
COMPENSATION
AMPLIFIER
TEMPERATURE
ERROR
AMPLIFIER
VDD
ADN8834
VDD
40μA
10μA
HEATING
TEC CURRENT SENSE
LDR
TEC
VOLTAGE
SENSE
SW
PGNDS
PVIN
PWM POWER
STAGE
PWM
MOSFET
DRIVER
EN/SY
SFB
20kΩ20kΩ
20kΩ
20kΩ
100kΩ
V
B
V
B
400kΩ
80kΩ
PWM
MODULATOR
PWM
ERROR
AMPLIFIER
ILIM
COOLING
ITEC
20kΩ
TEC
CURRENT
LIMIT
PGNDS
LDR
PGNDL
PVIN
PGNDL
HEATING
COOLING
CLK
SHUTDOWN
0.07V
OSCILLATOR CLK
SHUTDOWN
DEGLITCH
V
HIGH
≥ 2.1V
V
LOW
≤ 0.8V
2kΩ 80kΩ
TEC DRIVER
LINEAR POWER
STAGE
+
–
+
–
12954-
018
Figure 25. Detailed Functional Block Diagram of the ADN8834 for the WLCSP
Data Sheet ADN8834
Rev. B | Page 13 of 27
THEORY OF OPERATION
The ADN8834 is a single chip TEC controller that sets and
stabilizes a TEC temperature. A voltage applied to the input of
the ADN8834 corresponds to the temperature setpoint of the target
object attached to the TEC. The ADN8834 controls an internal
FET H-bridge whereby the direction of the current fed through
the TEC can be either positive (for cooling mode), to pump
heat away from the object attached to the TEC, or negative (for
heating mode), to pump heat into the object attached to the TEC.
Temperature is measured with a thermal sensor attached to the
target object and the sensed temperature (voltage) is fed back to
the ADN8834 to complete a closed thermal control loop of the
TEC. For the best overall stability, couple the thermal sensor
close to the TEC. In most laser diode modules, a TEC and a
NTC thermistor are already mounted in the same package to
regulate the laser diode temperature.
The TEC is differentially driven in an H-bridge configuration.
The ADN8834 drives its internal MOSFET transistors to provide
the TEC current. To provide good power efficiency and zero
crossing quality, only one side of the H-bridge uses a PWM
driver. Only one inductor and one capacitor are required to filter
out the switching frequency. The other side of the H-bridge uses a
linear output without requiring any additional circuitry. This pro-
prietary configuration allows the ADN8834 to provide efficiency of
>90%. For most applications, a 1 μH inductor, a 10 μF capacitor,
and a switching frequency of 2 MHz maintain less than 1% of the
worst-case output voltage ripple across a TEC.
The maximum voltage across the TEC and the current flowing
through the TEC are set by using the VLIM/SD and ILIM pins.
The maximum cooling and heating currents can be set indepen-
dently to allow asymmetric heating and cooling limits. For
additional details, see the Maximum TEC Voltage Limit section
and the Maximum TEC Current Limit section.
ADN8834
L = 1μH
V
IN
2.7V TO 5.5V
TEC
SW
SFB
LDR
PGNDS
PVIN
VDD
ILIM
VLIM/SD
ITEC
TEC
VOLTAGE
LIMIT
SHUTDOWN
VTEC
+
–
EN/SY
C
SW_OUT
10μF
C
L_OUT
0.1μF
C
IN
10μF
C
VDD
0.1μF
R
BP
R
FB
PGNDL
NTC
TEC
VOLTAGE
TEC
CURRENT
ENABLE/
SYNC
TEMP
SET
IN1N
IN1P
IN2P
VREF
AGND
OUT1 IN2N OUT2
R
C2
R
C1
R
V2RV1
TEC
CURRENT
LIMITS
C
VREF
0.1μF
R
A
R
R
B
R
I
R
D
C
D
C
F
C
IR
P
R
X
R
TH
THERMISTER
12954-
019
Figure 26. Typical Application Circuit with Analog PID Compensation in a Temperature Control Loop
ADN8834 Data Sheet
Rev. B | Page 14 of 27
ANALOG PID CONTROL
The ADN8834 integrates two self-correcting, auto-zeroing
amplifiers (Chopper 1 and Chopper 2). The Chopper 1 amplifier
takes a thermal sensor input and converts or regulates the input
to a linear voltage output. The OUT1 voltage is proportional to
the object temperature. The OUT1 voltage is fed into the
compensation amplifier (Chopper 2) and is compared with a
temperature setpoint voltage, which creates an error voltage that is
proportional to the difference. For autonomous analog temperature
control, Chopper 2 can be used to implement a PID network as
shown in Figure 27 to set the overall stability and response of the
thermal loop. Adjusting the PID network optimizes the step
response of the TEC control loop. A compromised settling time
and the maximum current ringing become available when this
adjustment is done. To adjust the compensation network, see
the PID Compensation Amplifier (Chopper 2) section.
DIGITAL PID CONTROL
The ADN8834 can also be configured for use in a software
controlled PID loop. In this scenario, the Chopper 1 amplifier
can either be left unused or configured as a thermistor input
amplifier connected to an external temperature measurement
analog-to-digital converter (ADC). For more information, see
the Thermistor Amplifier (Chopper 1) section. If Chopper 1 is
left unused, tie IN1N and IN1P to AGND.
The Chopper 2 amplifier is used as a buffer for the external
DAC, which controls the temperature setpoint. Connect the
DAC to IN2P and short the IN2N and OUT2 pins together. See
Figure 27 for an overview of how to configure the ADN8834
external circuitry for digital PID control.
POWERING THE CONTROLLER
The ADN8834 operates at an input voltage range of 2.7 V to
5.5 V that is applied to the VDD pin and the PVIN pin for the
WLCSP (the PVINS pin and PVINL pin for the LFCSP. The
VDD pin is the input power for the driver and internal reference.
The PVIN input power pins are combined for both the linear
and the switching driver. Apply the same input voltage to all power
input pins: VDD and PVIN. In some circumstances, an RC low-
pass filter can be added optionally between the PVIN for the
WLCSP (PVINS and PVINL for the LFCSP) and VDD pins to
prevent high frequency noise from entering VDD, as shown in
Figure 27. The capacitor and resistor values are typically 10 ?
and 100 nF, respectively.
When configuring power supply to the ADN8834, keep in mind
that at high current loads, the input voltage may drop substantially
due to a voltage drop on the wires between the front-end power
supply and the PVIN for the WLCSP (PVINS and PVINL for
the LFCSP) pin. Leave a proper voltage margin when designing
the front-end power supply to maintain the performance.
Minimize the trace length from the power supply to the PVIN
for the WLCSP (PVINS and PVINL for the LFCSP) pin to help
mitigate the voltage drop.
ADN8834
L = 1μH
V
IN
2.7V TO 5.5V
TEC
SW
SFB
LDR
PGNDS
PVIN
VDDILIM
VLIM/SD
ITEC
IN2P
VTEC
TEC
VOLTAGE
LIMIT
2.5V VREF
+
–
EN/SY
C
SW_OUT
10μF
F
SW
= 2MHz
C
L_OUT
0.1μF
C
IN
10μF
C
VDD
0.1μF
PGNDL
ENABLE
IN1N
IN1P
VREF
AGND
IN2N OUT2OUT1
R
V1
R
V2
R
C1
R
C2
COOLING AND HEATING
TEC CURRENT LIMITS
C
VREF
0.1uF
R
A
R
2.5V VREF
TEC VOLTAGE READBACK
TEC CURRENT READBACK
TEMPERATURE SET
R
B
R
FB
R
BP
R
X
NTC
THERMISTER
R
TH
TEMPERATURE
READBACK
ADC
DAC
2.5V VREF
2.5V VREF
12954-
020
Figure 27. TEC Controller in a Digital Temperature Control Loop (WLCSP)
Data Sheet ADN8834
Rev. B | Page 15 of 27
ENABLE AND SHUTDOWN
To enable the ADN8834, apply a logic high voltage to the
EN/SY pin while the voltage at the VLIM/SD pin is above the
maximum shutdown threshold of 0.07 V. If either the EN/SY
pin voltage is set to logic low or the VLIM/SD voltage is below
0.07 V, t h e controller goes into an ultralow current state. The
current drawn in shutdown mode is 350 μA typically. Most of
the current is consumed by the VREF circuit block, which is
always on even when the device is disabled or shut down. The
device can also be enabled when an external synchronization
clock signal is applied to the EN/SY pin, and the voltage at
VLIM/SD input is above 0.07 V. Table 6 shows the combinations
of the two input signals that are required to enable the ADN8834.
Table 6. Enable Pin Combinations
EN/SY Input VLIM/SD Input Controller
>2.1 V >0.07 V Enabled
Switching between high
>2.1 V and low < 0.8 V
>0.07 V Enabled
<0.8 V No effect
1
Shutdown
Floating No effect
1
Shutdown
No effect
1
≤0.07 V Shutdown
1
No effect means this signal has no effect in shutting down or in enabling the
device.
OSCILLATOR CLOCK FREQUENCY
The ADN8834 has an internal oscillator that generates a 2.0 MHz
switching frequency for the PWM output stage. This oscillator is
active when the enabled voltage at the EN/SY pin is set to a logic
level higher than 2.1 V and the VLIM/SD pin voltage is greater
than the shutdown threshold of 0.07 V.
External Clock Operation
The PWM switching frequency of the ADN8834 can be
synchronized to an external clock from 1.85 MHz to 3.25 MHz,
applied to the EN/SY input pin as shown on Figure 28.
EXTERNAL CLOCK
SOURCE
ADN8834
AGND
EN/SY
12954-
021
Figure 28. Synchronize to an External Clock
Connecting Multiple ADN8834 Devices
Multiple ADN8834 devices can be driven from a single master
clock signal by connecting the external clock source to the
EN/SY pin of each slave device. The input ripple can be greatly
reduced by operating the ADN8834 devices 180° out of phase
from each other by placing an inverter at one of the EN/SY pins,
as shown in Figure 29.
ADN8834
ADN8834
EXTERNAL CLOCK
SOURCE
AGND
EN/SY
AGND
EN/SY
12954-
022
Figure 29. Multiple ADN8834 Devices Driven from a Master Clock
TEMPERATURE LOCK INDICATOR (LFCSP ONLY)
The TMPGD outputs logic high when the temperature error
amplifier output voltage, V
OUT1
, reaches the IN2P temperature
setpoint (TEMPSET) voltage. The TMPGD has a detection range
between 1.46 V and 1.54 V of V
OUT1
and hysteresis. The TMPGD
function allows direct interfacing either to the microcontrollers
or to the supervisory circuitry.
SOFT START ON POWER-UP
The ADN8834 has an internal soft start circuit that generates
aramp with a typical 150 ms profile to minimize inrush current
during power-up. The settling time and the final voltage across
the TEC depends on the TEC voltage required by the control
voltage of voltage loop. The higher the TEC voltage is, the longer it
requires to be built up.
When the ADN8834 is first powered up, the linear side discharges
the output of any prebias voltage. As soon as the prebias is
eliminated, the soft start cycle begins. During the soft start
cycle, both the PWM and linear outputs track the internal soft
start ramp until they reach midscale, where the control voltage,
V
C
, is equal to the bias voltage, V
B
. From the midscale voltage,
the PWM and linear outputs are then controlled by V
C
and
diverge from each other until the required differential voltage is
developed across the TEC or the differential voltage reaches the
voltage limit. The voltage developed across the TEC depends on
the control point at that moment in time. Figure 30 shows an
example of the soft start in cooling mode. Note that, as both the
LDR and SFB voltages increase with the soft start ramp and
ADN8834 Data Sheet
Rev. B | Page 16 of 27
approach V
B
, the ramp slows down to avoid possible current
overshoot at the point where the TEC voltage starts to build up.
V
B
LDR
SFB
TIME
DISCHARGE
PREBIAS
SOFT START
BEGINS
TEC VOLTAGE
BUILDS UP
REACH
VOLTAGE LIMIT
12954-
023
Figure 30. Soft Start Profile in Cooling Mode
TEC VOLTAGE/CURRENT MONITOR
The TEC real-time voltage and current are detectable at VTEC
and ITEC, respectively.
Voltage Monitor
VTEC is an analog voltage output pin with a voltage proportional
to the actual voltage across the TEC. A center VTEC voltage of
1.25 V corresponds to 0 V across the TEC. Convert the voltage
at VTEC and the voltage across the TEC using the following
equation:
V
VTEC
= 1.25 V + 0.25 × (V
LDR
? V
SFB
)
Current Monitor
ITEC is an analog voltage output pin with a voltage proportional
to the actual current through the TEC. A center ITEC voltage of
1.25 V corresponds to 0 A through the TEC. Convert the
voltage at ITEC and the current through the TEC using the
following equations:
V
ITEC_COOLING
= 1.25 V + I
LDR
× R
CS
where the current sense gain (R
CS
) is 0.525 V/A.
V
ITEC_HEATING
= 1.25 V ? I
LDR
× R
CS
MAXIMUM TEC VOLTAGE LIMIT
The maximum TEC voltage is set by applying a voltage divider
at the VLIM/SD pin to protect the TEC. The voltage limiter
operates bidirectionally and allows the cooling limit to be
different from the heating limit.
Using a Resistor Divider to Set the TEC Voltage Limit
Separate voltage limits are set using a resistor divider. The
internal current sink circuitry connected to VLIM/SD draws a
current when the ADN8834 drives the TEC in a heating direction,
which lowers the voltage at VLIM/SD. The current sink is not
active when the TEC is driven in a cooling direction; therefore,
the TEC heating voltage limit is always lower than the cooling
voltage limit.
VLIM/SD
TEC VOLTAGE
LIMIT AND
INTERNAL
SOFT START
10μA
HEATING
CLK
DISABLE
V
REF
R
V1
R
V2
12954-
024
SW OPEN = V
VLIMC
SW CLOSED = V
VLIMH
Figure 31. Using a Resistor Divider to Set the TEC Voltage Limit
Calculate the cooling and heating limits using the following
equations:
V
VLIM_COOLING
= V
REF
× R
V2
/(R
V1
+R
V2
)
where V
REF
= 2.5 V.
V
VLIM_HEATING
= V
VLIM_COOLING
? I
SINK_VLIM
× R
V1
||R
V2
where I
SINK_VLIM
= 10 μA.
V
TEC_MAX_COOLING
= V
VLIM_COOLING
× A
VLIM
where A
VLIM
= 2 V / V.
V
TEC_MAX_HEATING
= V
VLIM_HEATING
× A
VLIM
Data Sheet ADN8834
Rev. B | Page 17 of 27
MAXIMUM TEC CURRENT LIMIT
To protect the TEC, separate maximum TEC current limits in
cooling and heating directions are set by applying a voltage
combination at the ILIM pin.
Using a Resistor Divider to Set the TEC Current Limit
The internal current sink circuitry connected to ILIM draws a
40 μA current when the ADN8834 drives the TEC in a cooling
direction, which allows a high cooling current. Use the following
equations to calculate the maximum TEC currents:
V
ILIM_HEATING
= V
REF
× R
C2
/(R
C1
+R
C2
)
where V
REF
= 2.5 V.
V
ILIM_COOLING
= V
ILIM_HEATING
+ I
SINK_ILIM
× R
C1
||R
C2
where I
SINK_ILIM
= 40 μA.
CS
COOLINGILIM
COOLINGMAXTEC
R
V
I
V25.1
_
__
?
=
where R
CS
= 0.525 V/A.
CS
HEATINGILIM
HEATINGMAXTEC
R
V
I
_
__
V25.1 ?
=
V
ILIM_HEATING
must not exceed 1.2 V and V
ILIM_COOLING
must be
more than 1.3 V to leave proper margins between the heating
and the cooling modes.
VDD
40μA
ILIM
COOLING
ITEC +
–
TEC
CURRENT
LIMIT
V
REF
R
C1
R
C2
SW OPEN = V
ILIMH
SW CLOSED = V
ILIMC
12954-
025
Figure 32. Using a Resistor Divider to Set the TEC Current Limit
ADN8834 Data Sheet
Rev. B | Page 18 of 27
APPLICATIONS INFORMATION
LINEAR
AMPLIFIER
LDR
TEC CURRENT SENSE
SW
PGNDS
PVIN
PWM POWER
STAGE
PWM
MOSFET
DRIVER
CONTROL
SFB
PWM
MODULATOR
PGNDS
LDR
TEC
PGNDL
PVIN
PGNDL
+
–
OSCILLATOR
IN2P
OUT2
IN2N
TEC DRIVER
LINEAR POWER
STAGE
+
–
+
–
IN1P
OUT1
IN1N
Z
2
Z
1R
FB
R
R
X
R
TH
V
REF
/2
V
REF
V
TEMPSET
V
OUT2
V
OUT1
V
IN
V
IN
TEMPERATURE ERROR
AMPLIFIER
A
V
= R
FB
/(R
TH
+ R
X
) – R
FB
/R
CHOPPER 1
PID COMPENSATION
AMPLIFIER
A
V
= Z2/Z1
CHOPPER 2
12954-
026
Figure 33. Signal Flow Block Diagram
SIGNAL FLOW
The ADN8834 integrates two auto-zero amplifiers, defined as
the Chopper 1 amplifier and the Chopper 2 amplifier. Both of the
amplifiers can be used as standalone amplifiers; therefore, the
implementation of temperature control can vary. Figure 33
shows the signal flow through the ADN8834, and a typical
implementation of the temperature control loop using the
Chopper 1 amplifier and the Chopper 2 amplifier.
In Figure 33, the Chopper 1 and Chopper 2 amplifiers are config-
ured as the thermistor input amplifier and the PID compensation
amplifier, respectively. The thermistor input amplifier gains the
thermistor voltage, then outputs to the PID compensation amplifier.
The PID compensation amplifier then compensates a loop
response over the frequency domain.
The output from the compensation loop at OUT2 is fed to the linear
MOSFET gate driver. The voltage at LDR is fed with OUT2 into
the PWM MOSFET gate driver. Including the internal transistors,
the gain of the differential output section is fixed at 5. For details
on the output drivers, see the MOSFET Driver Amplifier section.
THERMISTOR SETUP
The thermistor has a nonlinear relationship to temperature; near
optimal linearity over a specified temperature range can be achieved
with the proper value of R
X
placed in series with the thermistor.
First, the resistance of the thermistor must be known, where
? R
LOW
= R
TH
at T
LOW
? R
MID
= R
TH
at T
MID
? R
HIGH
= R
TH
at T
HIGH
T
LOW
and T
HIGH
are the endpoints of the temperature range and
T
MID
is the average. In some cases, with only the β constant
available, calculate R
TH
using the following equation:
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?=
R
RTH
TT
RR
11
exp β
where:
R
TH
is a resistance at T (K).
R
R
is a resistance at T
R
(K).
Data Sheet ADN8834
Rev. B | Page 19 of 27
Calculate R
X
using the following equation:
?
?
?
?
?
?
?
?
?+
?+
=
MIDHIGHLOW
HIGHLOWHIGHMIDMIDLOW
X
RRR
RRRRRR
R
2
2
THERMISTOR AMPLIFIER (CHOPPER 1)
The Chopper 1 amplifier can be used as a thermistor input
amplifier. In Figure 33, the output voltage is a function of the
thermistor temperature. The voltage at OUT1 is expressed as:
2
1
REFFB
XTH
FB
OUT1
V
R
R
RR
R
V ×
?
?
?
?
?
?
?
?
+?
+
=
where:
R
TH
is a thermistor.
R
X
is a compensation resistor.
Calculate R using the following equation:
R = R
X
+ R
TH_@_25°C
V
OUT1
is centered around V
REF
/2 at 25°C. An average temperature-
to-voltage coefficient is ?25 mV/°C at a range of 5°C to 45°C.
–15 5 25 45
0
2.5
65
0.5
1.0
1.5
2.0
TEMPERATURE (°C)
V
O
UT
1
(V)
12954-
027
Figure 34. V
OUT1
vs. Temperature
PID COMPENSATION AMPLIFIER (CHOPPER 2)
Use the Chopper 2 amplifier as the PID compensation amplifier.
The voltage at OUT1 feeds into the PID compensation amplifier.
The frequency response of the PID compensation amplifier is
dictated by the compensation network. Apply the temperature
set voltage at IN2P. In Figure 39, the voltage at OUT2 is
calculated using the following equation:
)(
TEMPSETOUT1TEMPSETOUT2
VV
Z1
Z2
VV ??=
where:
V
TEMPSET
is the control voltage input to the IN2P pin.
Z1 is the combination of R
I
, R
D
, and C
D
(see Figure 35).
Z2 is the combination of R
P
, C
I
, and C
F
(see Figure 35).
The user sets the exact compensation network. This network
varies from a simple integrator to proportional-integral (PI), PID
(proportional-integral-derivative), or any other type of network.
The user also determines the type of compensation and component
values because they are dependent on the thermal response of the
object and the TEC. One method to empirically determine these
values is to input a step function to IN2P; thus changing the target
temperature, and adjust the compensation network to minimize
the settling time of the TEC temperature.
A typical compensation network for temperature control of a laser
module is a PID loop consisting of a very low frequency pole and
two separate zeros at higher frequencies. Figure 35 shows a simple
network for implementing PID compensation. To reduce the noise
sensitivity of the control loop, an additional pole is added at a higher
frequency than that of the zeros. The bode plot of the magnitude is
shown in Figure 36. Use the following equation to calculate the
unity-gain crossover frequency of the feed-forward amplifier:
TECGAIN
R
R
RR
R
CR
f
FB
XTH
FB
II
0dB
×
?
?
?
?
?
?
?
?
?
+
×=
2π
1
To ensure stability, the unity-gain crossover frequency must be
lower than the thermal time constant of the TEC and thermistor.
However, this thermal time constant is sometimes unspecified,
making it difficult to characterize. There are many texts written
on loop stabilization, and it is beyond the scope of this data sheet to
discuss all methods and trade-offs for optimizing compensation
networks.
V
OUT1
is a convenient measure to gauge the thermal instability of
the system, which is also known as TEMPOUT. If the thermal loop
is in steady state, the TEMPOUT voltage equals the TEMPSET
voltage, meaning that the temperature of the controlled object
equals the target temperature.
OUT1 IN2N OUT2
PID COMPENSATOR
CHOPPER 2
IN2P
ADN8834
V
TEMPSET
R
I
R
D
C
D
C
F
C
IR
P
12954-
028
Figure 35. Implementing a PID Compensation Loop
FREQUENCY (Hz Log Scale)
M
AG
NI
T
UDE
(
L
o
g
S
cal
e)
0dB
1
2π × R
I
C
I
R
P
R
I
1
2π × R
I
C
D
1
2π × R
P
C
I
1
2π × C
D
(R
D
+ R
I
)
R
P
R
D
|| R
I
12954-
029
Figure 36. Bode Plot for PID Compensation
ADN8834 Data Sheet
Rev. B | Page 20 of 27
MOSFET DRIVER AMPLIFIERS
The ADN8834 has two separate MOSFET drivers: a switched
output or pulse-width modulated (PWM) amplifier, and a high
gain linear amplifier. Each amplifier has a pair of outputs that drive
the gates of the internal MOSFETs, which, in turn, drive the TEC as
shown in Figure 33. A voltage across the TEC is monitored via
the SFB and LDR pins. Although both MOSFET drivers achieve
the same result, to provide constant voltage and high current,
their operation is different. The exact equations for the two
outputs are
V
LDR
= V
B
? 40(V
OUT2
? 1.25 V)
V
SFB
= V
LDR
+ 5(V
OUT2
? 1.25 V)
where:
V
OUT2
is the voltage at OUT2.
V
B
is determined by V
VDD
as
V
B
= 1.5 V for V
VDD
< 4.0 V
V
B
= 2.5 V for V
VDD
> 4.0 V
The compensation network that receives the temperature set voltage
and the thermistor voltage fed by the input amplifier determines
the voltage at OUT2. V
LDR
and V
SFB
have a low limit of 0 V and
an upper limit of V
VDD
. Figure 37, Figure 38, and Figure 39 show
the graphs of these equations.
OUT2 (V)
L
DR (
V
)
1.250.750.250 1.75 2.25 2.75
–2.5
2.5
7.5
0
5.0
V
SYS
= 5.0V
V
SYS
= 3.3V
12954-
030
Figure 37. LDR Voltage vs. OUT2 Voltage
12954-
031
SF
B
(V)
OUT2 (V)
1.250.750.250 1.75 2.25 2.75
–2.5
2.5
7.5
0
5.0
V
SYS
= 5.0V
V
SYS
= 3.3V
Figure 38. SFB Voltage vs. OUT2 Voltage
–2.5
–5.0
0
2.5
5.0
OUT2 (V)
V
SYS
= 5.0V
V
SYS
= 3.3V
VT
EC
(V)
L
DR – S
F
B
1.250.750.250 1.75 2.25 2.75
12954-
032
Figure 39. TEC Voltage vs. OUT2 Voltage
PWM OUTPUT FILTER REQUIREMENTS
A type three compensator internally compensates the PWM
amplifier. As the poles and zeros of the compensator are designed
and fixed by assuming the resonance frequency of the output
LC tank being 50 kHz, the selection of the inductor and the
capacitor must follow this guideline to ensure system stability.
Inductor Selection
The inductor selection determines the inductor current ripple and
loop dynamic response. Larger inductance results in smaller
current ripple and slower transient response as smaller inductance
results in the opposite performance. To optimize the performance,
the trade-off must be made between transient response speed,
efficiency, and component size. Calculate the inductor value
with the following equation:
( )
LSWIN
OUTSWINOUTSW
IfV
VVV
L
?××
×
=
__
–
where:
V
SW_OUT
is the PWM amplifier output.
f
SW
is the switching frequency (2 MHz by default).
?I
L
is the inductor current ripple.
A 1 μH inductor is typically recommended to allow reasonable
output capacitor selection while maintaining a low inductor current
ripple. If lower inductance is required, a minimum inductor value
of 0.68 μH is suggested to ensure that the current ripple is set to
a value between 30% and 40% of the maximum load current,
which is 1.5 A.
Except for the inductor value, the equivalent dc resistance (DCR)
inherent in the metal conductor is also a critical factor for
inductor selection. The DCR accounts for most of the power loss
on the inductor by DCR × I
OUT
2
. Using an inductor with high
DCR degrades the overall efficiency significantly. In addition,
there is a conduct voltage drop across the inductor because of
the DCR. When the PWM amplifier is sinking current in cooling
mode, this voltage drives the minimum voltage of the amplifier
higher than 0.06 × V
IN
by at least tenth of millivolts. Similarly, the
maximum PWM amplifier output voltage is lower than 0.93 × V
IN
.
Data Sheet ADN8834
Rev. B | Page 21 of 27
This voltage drop is proportional to the value of the DCR and it
reduces the output voltage range at the TEC.
When selecting an inductor, ensure that the saturation current
rating is higher than the maximum current peak to prevent sat-
uration. In general, ceramic multilayer inductors are suitable for low
current applications due to small size and low DCR. When the
noise level is critical, use a shielded ferrite inductor to reduce the
electromagnetic interference (EMI).
Table 7. Recommended Inductors
Vendor Value Device No. Footprint
Toko 1.0 μH ± 20%,
2.6 A (typical)
DFE201612R-H-1R0M 2.0 × 1.6
Taiyo
Yuden
1.0 μH ± 20%,
2.2 A (typical)
MAKK2016T1R0M 2.0 × 1.6
Murata 1.0 μH ± 20%,
2.3 A (typical)
LQM2MPN1R0MGH 2.0 × 1.6
Capacitor Selection
The output capacitor selection determines the output voltage
ripple, transient response, as well as the loop dynamic response
of the PWM amplifier output. Use the following equation to
select the capacitor:
( )
OUTSWIN
OUTSWINOUTSW
VfLV
VVV
C
?××××
×
=
2
__
)(8
–
Note that the voltage caused by the product of current ripple,
ΔI
L
, and the capacitor equivalent series resistance (ESR) also
add up to the total output voltage ripple. Selecting a capacitor
with low ESR can increase overall regulation and efficiency
performance.
Table 8. Recommended Capacitors
Vendor Value Device No.
Footprint
(mm)
Murata 10 μF ±
10%, 10 V
ZRB18AD71A106KE01L 1.6 × 0.8
Murata 10 μF ±
20%, 10 V
GRM188D71A106MA73 1.6 × 0.8
Taiyo
Yuden
10 μF ±
20%, 10 V
LMK107BC6106MA-T 1.6 × 0.8
INPUT CAPACITOR SELECTION
On the PVIN pin, the amplifiers require an input capacitor
to decouple the noise and to provide the transient current to
maintain a stable input and output voltage. A 10 μF ceramic
capacitor rated at 10 V is the minimum recommended value.
Increasing the capacitance reduces the switching ripple that
couples into the power supply but increases the capacitor size.
Because the current at the input terminal of the PWM amplifier
is discontinuous, a capacitor with low effective series inductance
(ESL) is preferred to reduce voltage spikes.
In most applications, a decoupling capacitor is used in parallel
with the input capacitor. The decoupling capacitor is usually a
100 nF ceramic capacitor with very low ESR and ESL, which
provides better noise rejection at high frequency bands.
POWER DISSIPATION
This section provides guidelines to calculate the power
dissipation of the ADN8834. Approximate the total power
dissipation in the device by
P
LOSS
= P
PWM
+ P
LINEAR
where:
P
LOSS
is the total power dissipation in the ADN8834.
P
LINEAR
is the power dissipation in the linear regulator.
PWM Regulator Power Dissipation
The PWM power stage is configured as a buck regulator and
its dominant power dissipation (P
PWM
) includes power switch
conduction losses (P
COND
), switching losses (P
SW
), and transition
losses (P
TRAN
). Other sources of power dissipation are usually
less significant at the high output currents of the application
thermal limit and can be neglected in approximation.
Use the following equation to estimate the power dissipation of
the buck regulator:
P
LOSS
= P
COND
+ P
SW
+ P
TRAN
Conduction Loss (P
COND
)
The conduction loss consists of two parts: inductor conduction
loss (P
COND_L
) and power switch conduction loss (P
COND_S
).
P
COND
= P
COND_L
+ P
COND_S
Inductor conduction loss is proportional to the DCR of the output
inductor, L. Using an inductor with low DCR enhances the overall
efficiency performance. Estimate inductor conduction loss by
P
COND_L
= DCR × I
OUT
2
Power switch conduction losses are caused by the flow of the
output current through both the high-side and low-side power
switches, each of which has its own internal on resistance (R
DSON
).
Use the following equation to estimate the amount of power
switch conduction loss:
P
COND_S
= (R
DSON_HS
× D + R
DSON_LS
× (1 ? D)) × I
OUT
2
where:
R
DSON_HS
is the on resistance of the high-side MOSFET.
D is the duty cycle (D = V
OUT
/V
IN
).
R
DSON_LS
is the on resistance of the low-side MOSFET.
ADN8834 Data Sheet
Rev. B | Page 22 of 27
Switching Loss (P
SW
)
Switching losses are associated with the current drawn by the
controller to turn the power devices on and off at the switching
frequency. Each time a power device gate is turned on or off,
the controller transfers a charge from the input supply to the
gate, and then from the gate to ground. Use the following
equation to estimate the switching loss:
P
SW
= (C
GATE_HS
+ C
GATE_LS
) × V
IN
2
× f
SW
where:
C
GATE_HS
is the gate capacitance of the high-side MOSFET.
C
GATE_LS
is the gate capacitance of the low-side MOSFET.
f
SW
is the switching frequency.
For the ADN8834, the total of (C
GATE_HS
+ C
GATE_LS
) is
approximately 1 nF.
Transition Loss (P
TRAN
)
Transition losses occur because the high-side MOSFET cannot
turn on or off instantaneously. During a switch node transition,
the MOSFET provides all the inductor current. The source-to-
drain voltage of the MOSFET is half the input voltage, resulting
in power loss. Transition losses increase with both load and input
voltage and occur twice for each switching cycle.
Use the following equation to estimate the transition loss:
P
TRAN
= 0.5 × V
IN
× I
OUT
× (t
R
+ t
F
) × f
SW
where:
t
R
is the rise time of the switch node.
t
F
is the fall time of the switch node.
For the ADN8834, t
R
and t
F
are both approximately 1 ns.
Linear Regulator Power Dissipation
The power dissipation of the linear regulator is given by the
following equation:
P
LINEAR
= [(V
IN
? V
OUT
) × I
OUT
] + (V
IN
× I
GND
)
where:
V
IN
and V
OUT
are the input and output voltages of the linear
regulator.
I
OUT
is the load current of the linear regulator.
I
GND
is the ground current of the linear regulator.
Power dissipation due to the ground current is generally small
and can be ignored for the purposes of this calculation.
Data Sheet ADN8834
Rev. B | Page 23 of 27
PCB LAYOUT GUIDELINES
TEMPERATURE
SIGNAL
CONDITIONING
TEC
VOLTAGE
LIMITING
TEC
CURRENT
LIMITING
TEC
VOLTAGE
SENSING
TEC
CURRENT
SENSING
TEC
DRIVER
OBJECT
THERMOELECTRIC
COOLER
(TEC)
TEMPERATURE
ERROR
COMPENSATION
TEMPERATURE
SENSOR
SOURCE OF
ELECTRICAL
POWER
TARGET
TEMPERATURE
12954-
033
Figure 40. System Block Diagram
BLOCK DIAGRAMS AND SIGNAL FLOW
The ADN8834 integrates analog signal conditioning blocks, a
load protection block, and a TEC controller power stage all in a
single IC. To achieve the best possible circuit performance,
attention must be paid to keep noise of the power stage from
contaminating the sensitive analog conditioning and protection
circuits. In addition, the layout of the power stage must be
performed such that the IR losses are minimized to obtain the
best possible electrical efficiency.
The system block diagram of the ADN8834 is shown in Figure 40.
GUIDELINES FOR REDUCING NOISE AND
MINIMIZING POWER LOSS
Each printed circuit board (PCB) layout is unique because of
the physical constraints defined by the mechanical aspects of a
given design. In addition, several other circuits work in conjunction
with the TEC controller; these circuits have their own layout
requirements, so there are always compromises that must be
made for a given system. However, to minimize noise and keep
power losses to a minimum during the PCB layout process,
observe the following guidelines.
General PCB Layout Guidelines
Switching noise can interfere with other signals in the system;
therefore, the switching signal traces must be placed away from
the power stage to minimize the effect. If possible, place the
ground plate between the small signal layer and power stage
layer as a shield.
Supply voltage drop on traces is also an important consideration
because it determines the voltage headroom of the TEC controller
at high currents. For example, if the supply voltage from the front-
end system is 3.3 V, and the voltage drop on the traces is 0.5 V,
PVIN sees only 2.8 V, which limits the maximum voltage of the
linear regulator as well as the maximum voltage across the TEC . To
mitigate the voltage waste on traces and impedance interconnec-
tion, place the ADN8834 and the input decoupling components
close to the supply voltage terminal. This placement not only
improves the system efficiency but also provides better regulation
performance at the output.
To prevent noise signal from circulating through ground plates,
reference all of the sensitive analog signals to AGND and connect
AGND to PGNDS using only a single point connection. This
ensures that the switching currents of the power stage do not
flow into the sensitive AGND node.
PWM Power Stage Layout Guidelines
The PWM power stage consists of a MOSFET pair that forms a
switch mode output that switches current from PVIN to the load
via an LC filter. The ripple voltage on the PVIN pin is caused by
the discontinuous current switched by the PWM side MOSFETs.
This rapid switching causes voltage ripple to form at the PVIN
input, which must be filtered using a bypass capacitor. Place a 10 μF
capacitor as close as possible to the PVIN pin to connect PVIN to
PGNDS. Because the 10 μF capacitor is sometimes bulky and has
higher ESR and ESL, a 100 nF decoupling capacitor is usually
used in parallel with it, placed between PVIN and PGNDS.
Because the decoupling is part of the pulsating current loop,
which carries high di/dt signals, the traces must be short and
wide to minimize the parasitic inductance. As a result, this
capacitor is usually placed on the same side of the board as the
ADN8834 to ensure short connections. If the layout requires
that a 10 μF capacitor be on the opposite side of the PCB, use
multiple vias to reduce via impedance.
The layout around the SW node is also critical because it switches
between PVIN and ground rapidly, which makes this node a
strong EMI source. Keep the copper area that connects the SW
node to the inductor small to minimize parasitic capacitance
between the SW node and other signal traces. This helps minimize
noise on the SW node due to excessive charge injection. However,
in high current applications, the copper area may be increased
reasonably to provide heat sink and to sustain high current flow.
Connect the ground side of the capacitor in the LC filter as close as
possible to PGNDS to minimize the ESL in the return path.
ADN8834 Data Sheet
Rev. B | Page 24 of 27
Linear Power Stage Layout Guidelines
The linear power stage consists of a MOSFET pair that forms a
linear amplifier, which operates in linear mode for very low output
currents, and changes to fully enhanced mode for greater
output currents.
Because the linear power stage does not switch currents rapidly
like the PWM power stage, it does not generate noise currents.
However, the linear power stage still requires a minimum
amount of bypass capacitance to decouple its input.
Place a 100 nF capacitor that connects from PVIN to PGNDL as
close as possible to the PVIN pin.
Placing the Thermistor Amplifier and PID Components
The thermistor conditioning and PID compensation amplifiers
work with very small signals and have gain; therefore, attention
must be paid when placing the external components with these
circuits.
Place the thermistor conditioning and PID circuit components
close to each other near the inputs of Chopper 1 and Chopper 2.
Avoid crossing paths between the amplifier circuits and the
power stages to prevent noise pickup on the sensitive nodes.
Always reference the thermistor to AGND to have the cleanest
connection to the amplifier input and to avoid any noise or
offset build up.
EXAMPLE PCB LAYOUT USING TWO LAYERS
Figure 41, Figure 42, and Figure 43 show an example ADN8834
PCB layout that uses two layers. This layout example achieves a
small solution size of approximately 20 mm
2
with all of the
conditioning circuitry and PID included. Using more layers and
blinds via allows the solution size to be reduced even further
because more of the discrete components can relocate to the
bottom side of the PCB.
R
BP
0201
C
V
DD
0201
C
B
ULK
0402
0201
0201
C
ITEC
VTEC
PGND
TEMPSET
VIN
TEC+
TEC–
NTC
CONNECT TO GROUND PLANE
CONNECT TO GROUND PLANE
U
N
I
T
S
=
(
mm)
C
BU
04
UULK
402
U 0U
4
U
L
0805
C
SW_OUT
0402
C
IN_S
C
IN_L
R
BP
0201
20
R
B
02
201
0201
201
BPBBPB
R
C2
C
V
DD
V
DD
020102
20
BPB
R
C1
0201
R
V2
0201
R
V1
0201
R
B
0201
R
A
0201
R
0201
R
X
0201
C
VREF
0201
C
I
0402
C
F
0201
C
D
0201
R
D
0201
R
I
0201
R
P
0201
R
FB
0201
C
L_O
U
T
0201
C
VDD
R
BP
PGNDL PGNDL OUT 1 IN1P IN2P
LDR LDR IN1N IN2N
VLIM /
SD
PVIN PVIN ITEC OUT 2 ILIM
SW SW VTEC EN/SY VDD
PGNDS PGNDS SFB AGND VREF
NL UT N N
00202020020
20
0
202
01
11
0101
L
2020
00
20202022
LDR N N
TE UT L
0000
2
02
22
0202
01010010
111
20202220202020
000000
TE DD
NGN SDS NGNNDDSS RE
CONNECT AGND
TO PGNDS ONLY AT A
SINGLE POINT AS A
STAR CONNECTION
AGND
4.0
3.5
3.0
2.5
1.5
1.0
0.5
0
0
0.
5
1.
0
1.
5
2.
0
2.
5
3.
0
3.
5
4.
0
4.
5
5.
0
2.0
12954-
034
Figure 41. Example PCB Layout Using Two Layers (Top and Bottom Layers)
Data Sheet ADN8834
Rev. B | Page 25 of 27
ITEC
VTEC
PGND
TEMPSET
VIN
TEC+
TEC–
NTC
CONNECT TO GROUND PLANE
CONNECT TO GROUND PLANE
UNI
T
S
= (
mm
)
L
0805
C
SW_OUT
0402
C
IN_L
R
C2
0201
R
C1
0201
R
V2
0201
R
V1
0201
R
B
0201
R
A
0201
R
0201
R
X
0201
C
VREF
0201
C
I
0402
C
F
0201
C
D
0201
R
D
0201
R
I
0201
R
P
0201
R
FB
0201
C
L
_
O
UT
0201
C
VDD
PGNDL PGNDL OUT 1 IN1P IN2P
IN1N IN2N
VLIM /
SD
PVIN PVIN ITEC OUT 2 ILIM
VTEC EN/SY VDD
SFB AGND VREF
GN L GN L UT N
N N
TE UT ML
F RE
AGND
4.0
3.5
3.0
2.5
1.5
1.0
0.5
0
0
0.
5
1.
0
1.
5
2.
0
2.
5
3.
0
3.
5
4.
0
4.
5
5.
0
2.0
12954-
035
Figure 42. Example PCB Layout Using Two Layers (Top Layer Only)
ADN8834 Data Sheet
Rev. B | Page 26 of 27
R
BP
0201
C
V
DD
0201
V
DD
201
R
BP
C
B
ULK
0402
UL
0
0201
0201
ITEC
VTEC
PGND
TEMPSET
VIN
TEC+
TEC–
NTC
4.0
3.5
3.0
2.5
1.5
1.0
0.5
0
CONNECT TO GROUND PLANE
CONNECT TO GROUND PLANE
U
N
I
T
S
=
(
mm)
C
IN_S
C
IN_L
0
C
VDD
R
BP
AGND
0.
5
1.
0
1.
5
2.
0
2.
5
3.
0
3.
5
4.
0
4.
5
5.
0
2.0
12954-
036
Figure 43. Example PCB Layout Using Two Layers (Bottom Layer Only)
Data Sheet ADN8834
Rev. B | Page 27 of 27
OUTLINE DIMENSIONS
06-
07-
2013-
A
P
K
G
-
003121
A
B
C
D
E
0.660
0.600
0.540
2.58
2.54 SQ
2.50
12345
BOTTOM VIEW
(BALL SIDE UP)
TOP VIEW
(BALL SIDE DOWN)
END VIEW
0.360
0.320
0.280
BALL A1
IDENTIFIER
SEATING
PLANE
0.390
0.360
0.330
COPLANARITY
0.05
2.00
REF
0.50
BSC
0.270
0.240
0.210
Figure 44. 25-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-25-7)
Dimensions shown in millimeters
0.50
BSC
0.50
0.40
0.30
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8.
BOTTOM VIEWTOP VIEW
4.10
4.00 SQ
3.90
SEATING
PLANE
0.80
0.75
0.70
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
PIN 1
INDICATOR
1
24
712
13
18
19
6
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
12-
03-
2013-
A
0.30
0.25
0.18
PIN 1
INDICATOR
0.20 MIN
2.70
2.60 SQ
2.50
EXPOSED
PAD
P
K
G
-
004273
Figure 45. 24-Lead Lead-frame Chip Scale Package [LFCSP_WQ]
(CP-24-15)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range
2
Package Description
Package
Option
ADN8834ACBZ-R7 ?40°C to +125°C 25-Ball Wafer Level Chip Scale Package [WLCSP] CB-25-7
ADN8834CB-EVALZ 25-Ball WLCSP Evaluation Board: ±1.5 A TEC Current Limit, 3 V TEC Voltage Limit
ADN8834ACPZ-R2 ?40°C to +125°C 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-24-15
ADN8834ACPZ-R7 ?40°C to +125°C 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-24-15
ADN8834CP-EVALZ 24-Lead LFCSP Evaluation Board: ±1.5 A TEC Current Limit, 3 V TEC Voltage Limit
ADN8834MB-EVALZ Mother Evaluation Board of the ADN8834 for PID tuning
1
Z = RoHS Compliant Part.
2
Operating junction temperature range. The ambient operating temperature range is ?40°C to +85°C.
?2015–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12954-0-9/18(B)
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