Hot Swappable Dual I
2
C Isolators
ADuM1250/ADuM1251
Rev. 0
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
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Fax: 781.461.3113 ?2006 Analog Devices, Inc. All rights reserved.
FEATURES
Bidirectional I
2
C communication
Open-drain interfaces
Suitable for hot swap applications
30 mA current sink capability
1000 kHz operation
3.0 V to 5.5 V supply/logic levels
8-lead SOIC lead-free package
High temperature operation: 105°C
Safety and regulatory approvals
UL recognition
2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A (pending)
VDE Certificate of Conformity (pending)
DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01
DIN EN 60950 (VDE 0805): 2001-12; DIN EN 60950: 2000
VIORM = 560 V peak
APPLICATIONS
Isolated I
2
C, SMBus, or PMBus interfaces
Multilevel I
2
C interfaces
Power supplies
Networking
Power-over-Ethernet
FUNCTIONAL BLOCK DIAGRAMS
ENCODE DECODE
DECODE ENCODE
ENCODE DECODE
DECODE ENCODEV
DD1
SDA
1
SCL
1
GND
1
V
DD2
SDA
2
SCL
2
GND
2
1
2
3
4
8
7
6
5
064
01
-
00
1
Figure 1. ADuM1250 Functional Block Diagram
ENCODE DECODE
ENCODE DECODE
DECODE ENCODEV
DD1
SDA
1
SCL
1
GND
1
V
DD2
SDA
2
SCL
2
GND
2
1
2
3
4
8
7
6
5
064
01
-
00
2
Figure 2. ADuM1251 Functional Block Diagram
GENERAL DESCRIPTION
The ADuM1250/ADuM1251
1
are hot swappable digital
isolators with non latching bidirectional communication
channels compatible with I
2
C interfaces. This eliminates the
need for splitting I
2
C signals into separate transmit and receive
signals for use with standalone optocouplers.
The ADuM1250 provides two bidirectional channels
supporting a complete isolated I
2
C interface. The ADuM1251
provides one bidirectional channel and one unidirectional
channel for those applications where a bidirectional clock is not
required.
Both the ADuM1250 and ADuM1251 contain hot swap
circuitry to prevent glitching data when an unpowered card is
inserted onto an active bus.
These isolators are based on iCoupler? chip scale transformer
technology from Analog Devices, Inc. iCoupler is a magnetic
isolation technology with functional, performance, size, and
power consumption advantages as compared to optocouplers.
With the ADuM1250/ADuM1251, iCoupler channels can be
integrated with semiconductor circuitry, which enables a
complete isolated I
2
C interface to be provided in a small
form factor.
1
Protected by U.S. Patents 5,952,849 and 6,873,065. Other patents pending.
ADuM1250/ADuM1251
Rev. 0 | Page 2 of 12
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Package Characteristics ............................................................... 5
Regulatory Information............................................................... 5
Insulation and Safety-Related Specifications............................ 5
DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation
Characteristics .............................................................................. 6
Recommended Operating Conditions ...................................... 6
Absolute Maximum Ratings ............................................................7
ESD Caution...................................................................................7
Pin Configuration and Function Descriptions..............................8
Test Conditions..................................................................................9
Application Notes ........................................................................... 10
Functional Description.............................................................. 10
Startup.......................................................................................... 10
Typical Application Diagram .................................................... 11
Magnetic Field Immunity............................................................. 11
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 12
REVISION HISTORY
10/06—Revision 0: Initial Version 0
ADuM1250/ADuM1251
Rev. 0 | Page 3 of 12
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
DC Specifications
All voltages are relative to their respective ground. All min/max specifications apply over the entire recommended operating range, unless
otherwise noted. All typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 5 V, unless otherwise noted.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM1250
Input Supply Current, Side 1, 5 V IDD1 2.8 5.0 mA VDD1 = 5 V
Input Supply Current, Side 2, 5 V IDD2 2.7 5.0 mA VDD2 = 5 V
Input Supply Current, Side 1, 3.3 V IDD1 1.9 3.0 mA VDD1 = 3.3 V
Input Supply Current, Side 2, 3.3 V IDD2 1.7 3.0 mA VDD2 = 3.3 V
ADuM1251
Input Supply Current, Side 1, 5 V IDD1 2.8 6.0 mA VDD1 = 5 V
Input Supply Current, Side 2, 5 V IDD2 2.5 4.7 mA VDD2 = 5 V
Input Supply Current, Side 1, 3.3 V IDD1 1.8 3.0 mA VDD1 = 3.3 V
Input Supply Current, Side 2, 3.3V IDD2 1.6 2.8 mA VDD2 = 3.3 V
LEAKAGE CURRENTS ISDA1, ISDA2, ISCL1,
ISCL2
0.01 10 μA VSDA1 = VDD1, VSDA2 = VDD2,
VSCL1 = VDD1, VSCL2 = VDD2
SIDE 1 LOGIC LEVELS
Logic Input Threshold
1
VSDA1T, VSCL1T 500 700 mV
Logic Low Output Voltages VSDA1OL, VSCL1OL 600 900 mV ISDA1 = ISCL1 = 3.0 mA
850 ISDA1 = ISCL1 = 0.5 mA
Input/Output Logic Low Level
Difference
2
ΔVSDA1, ΔVSCL1 50 mV
SIDE 2 LOGIC LEVELS
Logic Low Input Voltage VSDA2IL, VSCL2IL 0.3 VDD2 V
Logic High Input Voltage VSDA2IH, VSCL2IH 0.7 VDD2 V
Logic Low Output Voltage VSDA2OL, VSCL2OL 400 mV ISDA2 = ISCL2 = 30 mA
1
V < 0.5 V, V > 0.7 V. IL IH
2
ΔV = V – V . This is the minimum difference between the output logic low level and the input logic threshold within a given component. This ensures that there
is no possibility of the part latching up the bus to which it is connected.
S1 S1OL S1T
ADuM1250/ADuM1251
Rev. 0 | Page 4 of 12
AC Specifications
All voltages are relative to their respective ground. All min/max specifications apply over the entire recommended operating range, unless
otherwise noted. All typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 5 V, unless otherwise noted. Refer to Figure 5.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
MAXIMUM FREQUENCY 1000 kHz
OUTPUT FALL TIME
5 V Operation 4.5 V ≤ VDD1,VDD2 ≤ 5.5 V, CL1 = 40 pF, R1 = 1.6 kΩ,
CL2 = 400 pF, R2 = 180 Ω
Side 1 Output (0.9 VDD1 to 0.9 V) tf1 13 26 120 ns
Side 2 Output (0.9 VDD2 to 0.1 VDD2) tf2 32 52 120 ns
3 V Operation 3.0 V ≤ VDD1,VDD2 ≤ 3.6 V, CL1 = 40 pF, R1 = 1.0 kΩ,
CL2 = 400 pF, R2 = 120 Ω
Side 1 Output (0.9 VDD1 to 0.9 V) tf1 13 32 120 ns
Side 2 Output (0.9 VDD2 to 0.1 VDD2) tf2 32 61 120 ns
PROPAGATION DELAY
5 V Operation 4.5 ≤ VDD1, VDD2 ≤ 5.5 V,
CL1 = CL2 = 0, R1 = 1.6 kΩ, R2 = 180 Ω
Side 1-to-Side 2, Rising Edge
1
tPLH12 95 130 ns
Side 1-to-Side 2, Falling Edge
2
tPHL12 162 275 ns
Side 2-to-Side 1, Rising Edge
3
tPLH21 31 70 ns
Side 2-to-Side 1, Falling Edge
4
tPHL21 85 155 ns
3 V Operation 3.0 V ≤ VDD1,VDD2 ≤ 3.6 V,
CL1 = CL2 = 0, R1 = 1.0 kΩ, R2 = 120 Ω
Side 1-to-Side 2, Rising Edge
1
tPLH12 82 125 ns
Side 1-to-Side 2, Falling Edge
2
tPHL12 196 340 ns
Side 2-to-Side 1, Rising Edge
3
tPLH21 32 75 ns
Side 2-to-Side 1, Falling Edge
4
tPHL21 110 210 ns
PULSE WIDTH DISTORTION
5 V Operation 4.5 V ≤ VDD1, VDD2 ≤ 5.5 V,
CL1 = CL2 = 0, R1 = 1.6 kΩ, R2 = 180 Ω
Side 1-to-Side 2, |tPLH12 ? tPHL12| PWD12 67 145 ns
Side 2-to-Side 1, |tPLH21 ? tPHL21| PWD21 54 85 ns
3 V Operation 3.0 V ≤ VDD1,VDD2 ≤ 3.6 V,
CL1 = CL2 = 0, R1 = 1.0 kΩ, R2 = 120 Ω
Side 1-to-Side 2, |tPLH12 ? tPHL12| PWD12 114 215 ns
Side 2-to-Side 1, |tPLH21 ? tPHL21| PWD21 77 135 ns
COMMON-MODE TRANSIENT
IMMUNITY
5
|CMH|,
|CML|
25 35 kV/μs
1
tPLH12 propagation delay is measured from the Side 1 input logic threshold to an output value of 0.7 VDD2.
2
tPHL12 propagation delay is measured from the Side 1 input logic threshold to an output value of 0.4 V.
3
tPLH21 propagation delay is measured from the Side 2 input logic threshold to an output value of 0.7 VDD1.
4
tPLH21 propagation delay is measured from the Side 2 input logic threshold to an output value of 0.9 V.
5
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
ADuM1250/ADuM1251
Rev. 0 | Page 5 of 12
PACKAGE CHARACTERISTICS
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions
Resistance (Input-Output)
1
RI-O 10
12
Ω
Capacitance (Input-Output)
1
CI-O 1.0 pF f = 1 MHz
Input Capacitance CI 4.0 pF
IC Junction-to-Case Thermal Resistance, Side 1 θJCI 46 °C/W Thermocouple located at center of package
underside
IC Junction-to-Case Thermal Resistance, Side 2 θJCO 41 °C/W
1
The device is considered a 2-terminal device; Pin 1 through Pin 4 are shorted together, and Pin 5 through Pin 8 are shorted together.
REGULATORY INFORMATION
The ADuM1250/ADuM1251 has been approved by the following organizations:
Table 4.
UL CSA (Pending) VDE (Pending)
Recognized under 1577 Component
Recognition Program
1
Basic insulation, 2500 V rms isolation rating
Approved under CSA Component Acceptance
Notice #5A
Basic insulation per CSA 60950-1-03 and IEC
60950-1, 400 V rms (560 V peak) maximum
working voltage
Certified according to DIN EN 60747-5-2
(VDE 0884 Part 2):2003-01
2
Basic insulation,400 V rms (560 V peak)
maximum working voltage
File E214100 File 205078 File 2471900-4880-0001
1
In accordance with UL1577, each device is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second
(current leakage detection limit = 5 μA).
2
In accordance with DIN EN 60747-5-2, each device is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 second
(partial discharge detection limit = 5 pC).
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 5.
Parameter Symbol Value Unit Conditions
Rated Dielectric Insulation Voltage 2500 V rms 1 minute duration
Minimum External Air Gap (Clearance) L(I01) 4.90 min mm Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage) L(I02) 4.01 min mm Measured from input terminals to output terminals,
shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
ADuM1250/ADuM1251
Rev. 0 | Page 6 of 12
DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS
This isolator is suitable for basic isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits.
The marking on the package denotes DIN EN 60747-5-2 approval for a 560 V peak working voltage.
Table 6.
Description Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to III
For Rated Mains Voltage ≤ 400 V rms I to II
Climatic Classification 40/105/21
Pollution Degree (DIN VDE 0110, Table 1) 2
Maximum Working Insulation Voltage VIORM 560 VPEAK
Input-to-Output Test Voltage, Method b1 VPR 1050 VPEAK
VIORM × 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC
Input-to-Output Test Voltage, Method a VPR
After Environmental Tests Subgroup 1
VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC 896 VPEAK
After Input and/or Safety Test Subgroup 2/3 672
VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec) VTR 4000 VPEAK
Safety-Limiting Values (Maximum Value Allowed in the Event of a Failure (See also Figure 3)
Case Temperature TS 150 °C
Side 1 Current IS1 160 mA
Side 2 Current IS2 170 mA
Insulation Resistance at TS, VIO = 500 V RS >10
9
Ω
CASE TEMPERATURE (°C)
S
A
FE
TY
-
L
IM
IT
IN
G
C
U
R
R
E
N
T
(
m
A
)
0
0
350
50 100 150 200
50
300
06
40
1-
0
03
150
100
200
250
Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values on
Case Temperature, per DIN EN 60747-5-2
RECOMMENDED OPERATING CONDITIONS
Table 7.
Parameter Symbol Min Max Unit
Operating Temperature TA ?40 +105 °C
Supply Voltages
1
VDD1, VDD2 3.0 5.5 V
Input/Output Signal Voltage VSDA1, VSCL1, VSDA2, VSCL2 5.5 V
Capacitive Load, Side 1 CL1 40 pF
Capacitive Load, Side 2 CL2 400 pF
Static Output Loading, Side 1 ISDA1, ISCL1 0.5 3 mA
Static Output Loading, Side 2 ISDA2, ISCL2 0.5 30 mA
1
All voltages are relative to their respective ground. See the Application Notes section for data on immunity to external magnetic fields.
ADuM1250/ADuM1251
Rev. 0 | Page 7 of 12
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 8.
Parameter Symbol Min Max Unit
Storage Temperature TST ?55 +150 °C
Ambient Operating
Temperature
TA ?40 +105 °C
Supply Voltages
1
VDD1,
VDD2
?0.5 +7.0 V
Input/Output Voltage
1
,
Side 1
VSDA1,
VSCL1
?0.5 VDD1 + 0.5 V
Input/Output Voltage
1
,
Side 2
VSDA2,
VSCL2
?0.5 VDD2 + 0.5 V
Average Output
Current, per Pin2
IO mA
Common-Mode
Transients
3
?100 +100 kV/μs
1
All voltages are relative to their respective ground.
2
See Figure 3 for maximum rated current values for various temperatures.
3
Refers to common-mode transients across the insulation barrier. Common-
mode transients exceeding the absolute maximum rating may cause latch-
up or permanent damage.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ADuM1250/ADuM1251
Rev. 0 | Page 8 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
DD1
1
SDA
1
2
SCL
1
3
GND
1
4
V
DD2
8
SDA
2
7
SCL
2
6
GND
2
5
ADuM1250/
ADuM1251
TOP VIEW
(Not to Scale)
06
40
1-
00
4
Figure 4. ADuM1250/ADuM1251 Pin Configuration
Table 9. ADuM1250 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1 Supply Voltage, 3.0 V to 5.5 V.
2 SDA1 Data Input/Output, Side 1.
3 SCL1 Clock Input/Output, Side 1.
4 GND1 Ground 1. Ground reference for isolator Side 1.
5 GND2 Ground 2. Isolated ground reference for isolator Side 2.
6 SCL2 Clock Input/Output, Side 2.
7 SDA2 Data Input/Output, Side 2.
8 VDD2 Supply Voltage, 3.0 V to 5.5 V.
Table 10. ADuM1251 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1 Supply Voltage, 3.0 V to 5.5 V.
2 SDA1 Data Input/Output, Side 1.
3 SCL1 Clock Input, Side 1.
4 GND1 Ground 1. Ground reference for isolator Side 1.
5 GND2 Ground 2. Isolated ground reference for isolator Side 2.
6 SCL2 Clock Output, Side 2.
7 SDA2 Data Input/Output, Side 2.
8 VDD2 Supply Voltage, 3.0 V to 5.5 V.
ADuM1250/ADuM1251
Rev. 0 | Page 9 of 12
TEST CONDITIONS
ENCODE DECODE
DECODE ENCODE
ENCODE DECODE
DECODE ENCODE
V
DD1
SDA
1
SCL
1
V
DD2
SDA
2
SCL
2
C
L2GND
2
1
2
3
8
7
6
0
64
01
-
00
5
5
GND
1
4
C
L2
R2 R2
C
L1
C
L1
R1 R1
Figure 5. Timing Test Diagram
ADuM1250/ADuM1251
Rev. 0 | Page 10 of 12
APPLICATION NOTES
FUNCTIONAL DESCRIPTION
The ADuM1250/ADuM1251 interfaces on each side to a
bidirectional I
2
C signal. Internally, the I
2
C interface is split into
two unidirectional channels communicating in opposing
directions via a dedicated iCoupler isolation channel for each.
One channel (the bottom channel of each channel pair shown
in Figure 6) senses the voltage state of the Side 1 I
2
C pin and
transmits its state to its respective Side 2 I
2
C pin.
Both the Side 1 and the Side 2 I
2
C pins are designed to interface
to an I
2
C bus operating in the 3.0 V to 5.5 V range. A logic low
on either causes the opposite pin to be pulled low enough to
comply with the logic low threshold requirements of other I
2
C
devices on the bus. Avoidance of I
2
C bus contention is ensured
by an input low threshold at SDA1 or SCL1 guaranteed to be at
least 50 mV less than the output low signal at the same pin. This
prevents an output logic low at Side 1 being transmitted back to
Side 2 and pulling down the I
2
C bus.
Since the Side 2 logic levels/thresholds are standard I
2
C values,
multiple ADuM1250/ADuM1251 devices connected to a bus by
their Side 2 pins can communicate with each other and with
other devices having I
2
C compatibility
1
.
However, since the Side 1 pin has a modified output level/input
threshold, this side of the ADuM1250/ADuM1251 can only
communicate with devices conforming to the I
2
C standard. In
other words, Side 2 of the ADuM1250/ADuM1251 is I
2
C-
compliant while Side 1 is only I
2
C-compatible.
The output logic low levels are independent of the VDD1 and
VDD2 voltages. The input logic low threshold at Side 1 is also
independent of VDD1. However, the input logic low threshold at
Side 2 is designed to be at 0.3 VDD2, consistent with I
2
C
requirements. The Side 1 and Side 2 pins have open-collector
outputs whose high levels are set via pull-up resistors to their
respective supply voltages.
ENCODE DECODE
DECODE ENCODE
ENCODE DECODE
DECODE ENCODEV
DD1
SDA
1
SCL
1
V
DD2
SDA
2
SCL
2
C
LGND
2
1
2
3
8
7
6
0
64
01-
006
5GND
1
4
C
L
R2 R2
Figure 6. ADuM1250 Block Diagram
1
Here a distinction is made between I
2
C compatibility and I
2
C compliance. I
2
C
compatibility refers to situations in which a component''s logic levels do not
necessarily meet the requirements of the I
2
C specification but still allow the
component to communication with an I
2
C-compliant device. I
2
C compliance
refers to situations in which a component''s logic levels meet the
requirements of the I
2
C specification.
STARTUP
Both the VDD1 and VDD2 supplies have an under voltage lockout
feature to prevent the signal channels from operating unless
certain criteria are met. This avoids the possibility of input logic
low signals from pulling down the I
2
C bus inadvertently during
power-up/power-down.
The two criteria that must be met in order for the signal
channels to be enabled are as follows:
? Both supplies must be at least 2.5 V.
? At least 40 μs must elapse after both supplies exceeded the
internal startup threshold of 2.0 V.
Until both of these criteria are met for both supplies, the
ADuM1250/ADuM1251 outputs are pulled high, ensuring a
startup that avoids any disturbances on the bus. Figure 7 and
Figure 8 illustrate the supply conditions for fast and slow input
supply slew rates.
06
40
1-
0
07
MINIMUM RECOMMENDED
OPERATING SUPPLY, 3.0V
MINIMUM VALID SUPPLY, 2.5V
INTERNAL STARTUP
THRESHOLD, 2.0V
40μs
SUPPLY VALID
Figure 7. Start-Up Condition, Supply Slew Rate >12.5 V/ms
06
40
1-
0
08
40μs
SUPPLY VALID
MIN. RECOMMENDED
OPERATING SUPPLY, 3.0V
MIN. VALID SUPPLY, 2.5V
INTERNAL STARTUP
THRESHOLD, 2.0V
Figure 8. Start-Up Condition, Supply Slew Rate <12.5 V/ms
ADuM1250/ADuM1251
Rev. 0 | Page 11 of 12
TYPICAL APPLICATION DIAGRAM
06
40
1-
0
09
V
DD
GND
1
SDA
1
GND
2
V
2
SDA
2
ADuM1250
SCL
1
SCL
2
I
2
C BUS
1
2
3
4
8
7
6
5
Figure 9. Typical Isolated I
2
C Interface using ADuM1250
MAGNETIC FIELD IMMUNITY
The ADuM1250 is extremely immune to external magnetic
fields. The limitation on the ADuM1250’s magnetic field
immunity is set by the condition in which induced voltage in
the transformer’s receiving coil is sufficiently large to either
falsely set or reset the decoder. The following analysis defines
the conditions under which this may occur. The 3 V operating
condition of the ADuM1250 is examined because it represents
the most susceptible mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
∑
=Π?= NnrdtdV
n
...,2,1;)/β(
2
where:
β is the magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
Given the geometry of the receiving coil in the ADuM1250 and
an imposed requirement that the induced voltage is at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated, as shown in Figure 10.
MAGNETIC FIELD FREQUENCY (Hz)
100
MA
X
I
MU
M A
L
L
O
W
A
B
L
E
M
A
G
N
E
T
I
C
F
L
U
X
DE
NS
I
T
Y
(
k
g
a
u
ss)
0.001
1M
10
0.01
1k 10k 10M
0.1
1
100M100k
06
40
1-
01
0
Figure 10. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurs during a transmitted pulse
(with the worst-case polarity), it reduces the received pulse
from > 1.0 V to 0.75 V. Note that this is still well above the 0.5 V
sensing threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances away from the
ADuM1250 transformers. Figure 11 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As shown in Figure 11, the ADuM1250 is extremely
immune and can be affected only by extremely large currents
operated at high frequency and very close to the component.
For the 1 MHz example, one would have to place a 0.5 kA
current 5 mm away from the ADuM1250 to affect the
component’s operation.
MAGNETIC FIELD FREQUENCY (Hz)
M
A
X
I
M
U
M
AL
L
O
W
A
BL
E
C
URRE
NT
(
k
A)
1000
100
10
1
0.1
0.01
1k 10k 100M100k 1M 10M
DISTANCE = 5mm
DISTANCE = 1m
DISTANCE = 100mm
06
40
1-
0
11
Figure 11. Maximum Allowable Current for Various
Current-to-ADuM1250 Spacings
Note that at combinations of strong magnetic fields and high
frequencies, any loops formed by printed circuit board traces
could induce sufficiently large error voltages to trigger the
threshold of succeeding circuitry. Care should be taken in the
layout of such traces to avoid this possibility.
ADuM1250/ADuM1251
Rev. 0 | Page 12 of 12
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
06
05
06
-
A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 12. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters (inches)
ORDERING GUIDE
Model
Number
of Inputs,
VDD1 Side
Number
of Inputs,
VDD2 Side
Maximum
Data Rate
(Mbps)
Maximum
Propagation
Delay (ns)
Temperature
Range
Package
Description
Package
Option
ADuM1250ARZ
1
2 2 1 150 ?40°C to +105°C 8-Lead SOIC_N R-8
ADuM1250ARZ-RL7
1
2 2 1 150 ?40°C to +105°C 8-Lead SOIC_N R-8
ADuM1251ARZ
1
2 1 1 150 ?40°C to +105°C 8-Lead SOIC_N R-8
ADuM1251ARZ-RL7
1
2 1 1 150 ?40°C to +105°C 8-Lead SOIC_N R-8
1
Z = Pb-free part.
?2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06113-0-10/06(0)
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