Isolated, Single-Channel
RS-232 Line Driver/Receiver
ADM3251E
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ?2008 Analog Devices, Inc. All rights reserved.
FEATURES
2.5 kV fully isolated (power and data) RS-232 transceiver
isoPower integrated, isolated dc-to-dc converter
460 kbps data rate
1 Tx and 1 Rx
Meets EIA/TIA-232E specifications
ESD protection on RIN and TOUT pins
±8 kV: contact discharge
±15 kV: air gap discharge
0.1 μF charge pump capacitors
High common-mode transient immunity: >25 kV/μs
Safety and regulatory approvals (pending)
UL recognition
2500 V rms for 1 minute per UL 1577
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 560 V peak
Operating temperature range: ?40°C to +85°C
Wide body, 20-lead SOIC package
APPLICATIONS
High noise data communications
Industrial communications
General-purpose RS-232 data links
Industrial/telecommunications diagnostic ports
Medical equipment
FUNCTIONAL BLOCK DIAGRAM
073
88-
001
DECODE
RECT REG
V–
C4
0.1μF
16V
VOLTAGE
DOUBLER
C1+ C1– V+
V
ISO C2+ C2–
R
T
VOLTAGE
INVERTER
V
CC
R
OUT
T
IN
GND GND
ISO
R
IN
T
OUT
ADM3251E
OSC
ENCODE
ENCODE
DECODE
5k? PULL-DOWN RESISTOR ON THE RS-232 INPUT.
0.1μF
C3
0.1μF
10V
C2
0.1μF
16V0.1μF
C1
0.1μF
16V
Figure 1.
GENERAL DESCRIPTION
The ADM3251E is a high speed, 2.5 kV fully isolated, single-
channel RS-232/V.28 transceiver device that operates from a
single 5 V power supply. Due to the high ESD protection on the
RIN and TOUT pins, the device is ideally suited for operation in
electrically harsh environments or where RS-232 cables are
frequently being plugged and unplugged.
The ADM3251E incorporates dual-channel digital isolators with
isoPower? integrated, isolated power. There is no requirement
to use a separate isolated dc-to-dc converter. Chip-scale trans-
former iCoupler? technology from Analog Devices, Inc., is used
both for the isolation of the logic signals as well as for the
integrated dc-to-dc converter. The result is a total isolation
solution.
The ADM3251E conforms to the EIA/TIA-232E and ITU-T V. 28
specifications and operates at data rates up to 460 kbps.
Four external 0.1 μF charge pump capacitors are used for the
voltage doubler/inverter, permitting operation from a single
5 V supply.
The ADM3251E is available in a 20-lead, wide body SOIC package
and is specified over the ?40°C to +85°C temperature range.
ADM3251E
Rev. 0 | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Package Characteristics ............................................................... 5
Regulatory Information (Pending) ............................................ 5
Insulation and Safety-Related Specifications ............................ 5
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation
Characteristics (Pending) ............................................................ 6
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ..............................8
Typical Performance Characteristics ..............................................9
Theory of Operation ...................................................................... 11
Isolation of Power and Data ...................................................... 11
Charge Pump Voltage Converter ............................................. 12
5.0 V Logic to EIA/TIA-232E Transmitter .............................. 12
EIA/TIA-232E to 5 V Logic Receiver ...................................... 12
High Baud Rate ........................................................................... 12
Thermal Analysis ....................................................................... 12
PCB Layout ................................................................................. 13
Insulation Lifetime ..................................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
7/08—Revision 0: Initial Version
ADM3251E
Rev. 0 | Page 3 of 16
SPECIFICATIONS
All voltages are relative to their respective ground; all minimum/maximum specifications apply over the entire recommended operating
range; TA = 25°C and VCC = 5.0 V (dc-to-dc converter enabled), unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
DC CHARACTERISTICS
VCC Operating Voltage Range 4.5 5.5 V
DC-to-DC Converter Enable Threshold, VCC(ENABLE)
1
4.5 V
DC-to-DC Converter Disable Threshold, VCC(DISABLE)
1
3.7 V
DC-to-DC Converter Enabled
Input Supply Current, ICC(ENABLE) 110 mA VCC = 5.5 V, no load
145 mA VCC = 5.5 V, RL = 3 kΩ
VISO Output
2
5.0 V IISO = 0 μA
LOGIC
Transmitter Input, TIN
Logic Input Current, ITIN ?10 +0.01 +10 μA
Logic Low Input Threshold, VTINL 0.3 VCC V
Logic High Input Threshold, VTINH 0.7 VCC V
Receiver Output, ROUT
Logic High Output, VROUTH CC ? 0.1 VCC V IROUTH = ?20 μA
CC ? 0.5 VCC ? 0.3 V IROUTH = ?4 mA
Logic Low Output, VROUTL 0.0 0.1 IROUTH = 20 μA
0.3 0.4 IROUTH = 4 mA
RS-232
Receiver, RIN
EIA-232 Input Voltage Range
3
?30 +30 V
EIA-232 Input Threshold Low 0.6 2.0 V
EIA-232 Input Threshold High 2.1 2.4 V
EIA-232 Input Hysteresis 0.1 V
EIA-232 Input Resistance 3 5 7 kΩ
Transmitter, TOUT
Output Voltage Swing (RS-232) ±5 ±5.7 V RL = 3 kΩ to GND
Transmitter Output Resistance 300 Ω VISO = 0 V
Output Short-Circuit Current (RS-232) ±12 mA
TIMING CHARACTERISTICS
Maximum Data Rate 460 kbps RL = 3 kΩ to 7 kΩ, CL = 50 pF to 1000 pF
Receiver Propagation Delay
tPHL 190 μs
tPLH 135 μs
Transmitter Propagation Delay 650 μs RL = 3 kΩ, CL = 1000 pF
Transmitter Skew 80 ns
Receiver Skew 70 ns
Transition Region Slew Rate
3
5.5 10 30 V/μs +3 V to ?3 V or ?3 V to +3 V, VCC = +3.3 V,
RL = +3 kΩ, CL = 1000 pF, TA = 25°C
AC SPECIFICATIONS
Output Rise/Fall Time, tR/tF (10% to 90%) 2.3 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic High Output
4
25 kV/μs VCM = 1 kV, transient magnitude = 800 V
Common-Mode Transient Immunity at Logic Low Output
4
25 kV/μs VCM = 1 kV, transient magnitude = 800 V
ESD PROTECTION (RIN And TOUT PINS) ±15 kV Human body model air discharge
±8 kV Human body model contact discharge
1
Enable/disable threshold is the VCC voltage at which the internal dc-to-dc converter is enabled/disabled.
2
To maintain data sheet specifications, do not draw current from VISO.
3
Guaranteed by design.
4
CM is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation. VCM is the common-mode potential
difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The common-mode voltage slew rates
apply to both rising and falling common-mode voltage edges.
ADM3251E
Rev. 0 | Page 4 of 16
All voltages are relative to their respective ground; all minimum/maximum specifications apply over the entire recommended operating
range; TA = 25°C, VCC = 3.3 V (dc-to-dc converter disabled), and the secondary side is powered externally by VISO = 3.3 V, unless
otherwise noted.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
DC CHARACTERISTICS
VCC Operating Voltage Range 3.0 3.7 V
DC-to-DC Converter Disable Threshold, VCC(DISABLE)
1
3.7 V
DC-to-DC Converter Disabled
VISO
2
3.0 5.5 V
Primary Side Supply Input Current, ICC(DISABLE) 1. mA No load
Secondary Side Supply Input Current, IISO(DISABLE) 12 mA VISO = 5.5 V, RL = 3 kΩ
Secondary Side Supply Input Current, IISO(DISABLE) 6.2 mA RL = 3 kΩ
LOGIC
Transmitter Input, TIN
Logic Input Current, ITIN ?10 +0.01 +10 μA
Logic Low Input Threshold, VTINL 0.3 VCC V
Logic High Input Threshold, VTINH 0.7 VCC V
Receiver Output, ROUT
Logic High Output, VROUTH CC ? 0.1 VCC V IROUTH = ?20 μA
CC ? 0.5 VCC ? 0.3 V IROUTH = ?4 mA
Logic Low Output, VROUTL 0.0 0.1 V IROUTH = 20 μA
0.3 0.4 IROUTH = 4 mA
RS-232
Receiver, RIN
EIA-232 Input Voltage Range
3
?30 +30 V
EIA-232 Input Threshold Low 0.6 1.3 V
EIA-232 Input Threshold High 1.6 2.4 V
EIA-232 Input Hysteresis 0.3 V
EIA-232 Input Resistance 3 5 7 kΩ
Transmitter, TOUT
Output Voltage Swing (RS-232) ±5 ±5.7 V RL = 3 kΩ to GND
Transmitter Output Resistance 300 Ω VISO = 0 V
Output Short-Circuit Current (RS-232) ±11 mA
TIMING CHARACTERISTICS
Maximum Data Rate 460 kbps RL = 3 kΩ to 7 kΩ, CL = 50 pF to 1000 pF
Receiver Propagation Delay
tPHL 190 μs
tPLH 135 μs
Transmitter Propagation Delay 650 μs RL = 3 kΩ, CL = 1000 pF
Transmitter Skew 80 ns
Receiver Skew 55 ns
Transition Region Slew Rate
3
5.5 10 30 V/μs +3 V to ?3 V or ?3 V to +3 V, VCC = 3.3 V,
RL = 3 kΩ, CL = 1000 pF, TA = 25°C
AC SPECIFICATIONS
Output Rise/Fall Time, tR/tF (10% to 90%) 2.3 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic High Output
4
25 kV/μs V
CM = 1 kV, transient magnitude = 800 V
Common-Mode Transient Immunity at Logic Low Output
4
25 kV/μs VCM = 1 kV, transient magnitude = 800 V
ESD PROTECTION (RIN AND TOUT PINS) ±15 kV Human body model air discharge
±8 kV Human body model contact discharge
1
Enable/disable threshold is the VCC voltage at which the internal dc-to-dc converter is enabled/disabled.
2
To maintain data sheet specifications, do not draw current from VISO.
3
Guaranteed by design.
4
CM is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation. VCM is the common-mode potential
difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The common-mode voltage slew rates
apply to both rising and falling common-mode voltage edges.
ADM3251E
Rev. 0 | Page 5 of 16
PACKAGE CHARACTERISTICS
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions
Resistance (Input-Output) RI-O 10
12
Ω
Capacitance (Input-Output) CI-O 2.2 pF f = 1 MHz
Input Capacitance CI 4.0 pF
IC Junction-to-Air Thermal Resistance θJA 47.05 °C/W
REGULATORY INFORMATION (PENDING)
Table 4.
UL
1
VDE
1577 Component Recognition Program (Pending)
Single/Basic Insulation, 2500 V rms Isolation Rating
To be certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
2
Reinforced insulation, 560 V peak
1
In accordance with UL 1577, each ADM3251E is proof-tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 μA).
2
In accordance with DIN V VDE V 0884-10, each ADM3251E is proof-tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection
limit = 5 pC).
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 5.
Parameter Symbol Value Unit Conditions
Rated Dielectric Insulation Voltage 2500 V rms 1 minute duration
Minimum External Air Gap (Clearance) L(I01) 7.7 mm Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage) L(I02) 4.16 mm Measured from input terminals to output terminals,
shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.017 mm Distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material group (DIN VDE 0110, 1/89, Table 1)
Maximum Working Voltage Compatible with
50-Year Service Life
VIORM 425 V peak Continuous peak voltage across the isolation barrier
ADM3251E
Rev. 0 | Page 6 of 16
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS (PENDING)
This isolator is suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits.
Table 6.
Description Conditions Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to III
Climatic Classification 40/105/21
Pollution Degree (DIN VDE 0110, Table 1) 2
Maximum Working Insulation Voltage VIORM 424 V peak
Input-to-Output Test Voltage
Method b1 VIORM × 1.875 = VPR, 100% production
test, tm = 1 sec, partial discharge < 5 pC
VPR 795 V peak
Method a
After Environmental Test Subgroup 1 VIORM × 1.6 = VPR, tm = 60 sec, partial
discharge < 5 pC
VPR 680 V peak
After Input and/or Safety Subgroup 2/Subgroup 3 VIORM × 1.2 = VPR, tm = 60 sec, partial
discharge < 5 pC
VP 510 V peak
Highest Allowable Overvoltage Transient overvoltage, tTR = 10 sec VTR 4000 V peak
Safety-Limiting Values Maximum value allowed in the event
of a failure
Case Temperature TS 150 °C
Supply Current IS1 531 mA
Insulation Resistance at TS VIO = 500 V RS >10
9
Ω
ADM3251E
Rev. 0 | Page 7 of 16
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter Rating
VCC, VISO ?0.3 V to +6 V
V+ (VCC ? 0.3 V) to +13 V
V? –13 V to +0.3 V
Input Voltages
TIN ?0.3 V to (VCC + 0.3 V)
RIN ±30 V
Output Voltages
TOUT ±15 V
ROUT ?0.3 V to (VCC + 0.3 V)
Short-Circuit Duration
TOUT Continuous
Power Dissipation
θJA, Thermal Impedance 47.05°C/W
Operating Temperature Range
Industrial ?40°C to +85°C
Storage Temperature Range ?65°C to +150°C
Pb-Free Temperature (Soldering, 30 sec) 260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ADM3251E
Rev. 0 | Page 8 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC 1
V
CC
2
V
CC
3
GND 4
V
ISO
20
V+19
C1+18
C1–17
GND 5 T
OUT
16
GND 6 R
IN
15
GND 7 C2+14
R
OUT
8 C2–13
T
IN
9 V–12
GND 10 GND
ISO
11
NC = NO CONNECT
ADM3251E
TOP VIEW
(Not to Scale)
07
38
8-
0
0
2
Figure 2. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1 NC No Connect. This pin should always remain unconnected.
2, 3 VCC Power Supply Input. A 0.1 μF decoupling capacitor is required between VCC and ground. When a voltage
between 4.5 V and 5.5 V is applied to the VCC pin, the integrated dc-to-dc converter is enabled. If this voltage is
lowered to between 3.0 V and 3.7 V, the integrated dc-to-dc converter is disabled.
4, 5, 6, 7, 10 GND Ground Pin.
8 ROUT Receiver Output. This pin outputs CMOS logic levels.
9 TIN Transmitter (Driver) Input. This pin accepts TTL/CMOS levels.
11 GNDISO Ground Reference for Isolator Primary Side.
12 V? Internally Generated Negative Supply.
13, 14 C2?, C2+ Positive and Negative Connections for Charge Pump Capacitors. External Capacitor C2 is connected between
these pins; a 0.1 μF capacitor is recommended, but larger capacitors up to 10 μF can be used.
15 RIN Receiver Input. This input accepts RS-232 signal levels.
16 TOUT Transmitter (Driver) Output. This outputs RS-232 signal levels.
17, 18 C1?, C1+ Positive and Negative Connections for Charge Pump Capacitors. External Capacitor C1 is connected between
these pins; a 0.1 μF capacitor is recommended, but larger capacitors up to 10 μF can be used.
19 V+ Internally Generated Positive Supply.
20 VISO Isolated Supply Voltage for Isolator Secondary Side. A 0.1 μF decoupling capacitor is required between VISO and
ground. When the integrated dc-to-dc converter is enabled, the VISO pin should not be used to power external
circuitry. If the integrated dc-to-dc converter is disabled, power the secondary side by applying a voltage in the
range of 3.0 V to 5.5 V to this pin.
ADM3251E
Rev. 0 | Page 9 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
12
8
4
0
–4
–8
–12
0 200 400 600 800 1000
LOAD CAPACITANCE (pF)
Tx
OU
T
P
U
T
(
V
)
07
38
8-
00
4
Tx LOW (V
CC
= 5V)
Tx LOW (V
ISO
= 3.3V)
Tx HIGH (V
CC
= 5V)
Tx HIGH (V
ISO
= 3.3V)
Figure 3. Transmitter Output Voltage High/Low vs. Load
Capacitance @ 460 kbps
12
10
8
6
4
2
0
–2
–4
–6
–8
–10
4.5 4.7 4.9 5.1 5.3 5.5
V
CC
(V)
Tx
OU
TP
U
T
(
V
)
07
38
8-
00
5
Tx OUTPUT HIGH
Tx OUTPUT LOW
Figure 4. Transmitter Output Voltage High/Low vs. VCC, RL = 3 kΩ
12
8
4
0
–4
–8
–12
10
6
2
–2
–6
–10
3.0 3.5 4.0 4.5 5.0 5.5
V
ISO
(V)
Tx
O
U
T
P
U
T
(
V
)
07
38
8-
0
09
Tx OUTPUT HIGH
Tx OUTPUT LOW
Figure 5. Transmitter Output Voltage High/Low vs. VISO, RL = 3 kΩ
12
10
8
6
4
2
0
–2
–4
–6
–8
–10
–12
01234
LOAD CURRENT (mA)
Tx
O
U
T
P
U
T
(
V
)
07
38
8-
00
6
Tx OUTPUT LOW (V
CC
= 5V)
Tx OUTPUT LOW (V
ISO
= 3.3V)
Tx OUTPUT HIGH (V
CC
= 5V)
Tx OUTPUT HIGH (V
ISO
= 3.3V)
Figure 6. Transmitter Output Voltage High/Low vs. Load Current
15
10
5
0
–5
–10
–15
0123
LOAD CURRENT (mA)
V
+
, V
–
(
V
)
0
738
8-
0
07
4
V+ (V
CC
= 5V)
V– (V
CC
= 5V)
V+ (V
ISO
= 3.3V)
V– (V
ISO
= 3.3V)
Figure 7. Charge Pump V+, V? vs. Load Current
400
V+
V–
350
300
250
200
150
100
50
0
4.50 4.75 5.00 5.25 5.50
V
CC
(V)
CH
ARG
E
P
U
M
P
I
M
P
E
DANC
E
(
?
)
07
388
-
00
8
Figure 8. Charge Pump Impedance vs. VCC
ADM3251E
Rev. 0 | Page 10 of 16
400
V–
350
300
250
200
150
100
50
0
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50
V
ISO
(V)
CH
ARG
E
P
U
M
P
I
M
P
E
DANC
E
(
?
)
07
388
-
01
0
V+
Figure 9. Charge Pump Impedance vs. VISO
200
180
160
140
120
100
80
60
40
20
0
0 46 92 138 184 230 276 322 368 414 460
DATA RATE (kbps)
S
UP
P
L
Y
CURRE
NT
(
m
A)
07
38
8-
00
3
V
CC
= 4.5V
V
CC
= 5.5V
V
CC
= 5V
Figure 10. Primary Supply Current vs. Data Rate
07
38
8-
0
12
5
V
/DIV
5
V
/DIV
TIME (500ns/DIV)
2
1
V
CC
=5V
LOAD = 3k? AND 1nF
Figure 11. 460 kpbs Data Transmission
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4.50 4.75 5.00 5.25 5.50
V
CC
(V)
T
IN
V
O
L
T
A
G
E
T
HRE
S
HO
L
D (
V
)
0
738
8-
0
11
HIGH THRESHOLD
LOW THRESHOLD
Figure 12. TIN Voltage Threshold vs. VCC
ADM3251E
Rev. 0 | Page 11 of 16
THEORY OF OPERATION
The ADM3251E is a high speed, 2.5 kV fully isolated, single-
channel RS-232 transceiver device that operates from a single
power supply.
The internal circuitry consists of the following main sections:
? Isolation of power and data
? A charge pump voltage converter
? A 5.0 V logic to EIA/TIA-232E transmitter
? A EIA/TIA-232E to 5.0 V logic receiver
073
88-
013
DECODE
RECT REG
V–
C4
0.1μF
16V
VOLTAGE
DOUBLER
C1+ C1– V+
V
ISO C2+ C2–
R
T
VOLTAGE
INVERTER
V
CC
R
OUT
T
IN
GND GND
ISO
R
IN
T
OUT
ADM3251E
OSC
ENCODE
ENCODE
DECODE
5k? PULL-DOWN RESISTOR ON THE RS-232 INPUT.
0.1μF
C3
0.1μF
10V
C2
0.1μF
16V0.1μF
C1
0.1μF
16V
Figure 13. Functional Block Diagram
ISOLATION OF POWER AND DATA
The ADM3251E incorporates a dc-to-dc converter section,
which works on principles that are common to most modern
power supply designs. VCC power is supplied to an oscillating
circuit that switches current into a chip-scale air core transformer.
Power is transferred to the secondary side, where it is rectified
to a high dc voltage. The power is then linearly regulated to
about 5.0 V and supplied to the secondary side data section
and to the VISO pin. The VISO pin should not be used to power
external circuitry.
Because the oscillator runs at a constant high frequency
independent of the load, excess power is internally dissipated
in the output voltage regulation process. Limited space for
transformer coils and components also adds to internal power
dissipation. This results in low power conversion efficiency.
The ADM3251E can be operated with the dc-to-dc converter
enabled or disabled. The internal dc-to-dc converter state of the
ADM3251E is controlled by the input VCC voltage. In normal
operating mode, VCC is set between 4.5 V and 5.5 V and the
internal dc-to-dc converter is enabled. When/if it is desired
to disable the dc-to-dc converter, lower VCC to a value between
3.0 V and 3.7 V. In this mode, the user must externally supply
isolated power to the VISO pin. An isolated secondary side
voltage of between 3.0 V and 5.5 V and a secondary side input
current, IISO, of 12 mA (maximum) is required on the VISO pin.
The signal channels of the ADM3251E then continue to operate
normally.
The TIN pin accepts TTL/CMOS input levels. The driver input
signal that is applied to the TIN pin is referenced to logic ground
(GND). It is coupled across the isolation barrier, inverted, and
then appears at the transceiver section, referenced to isolated
ground (GNDISO). Similarly, the receiver input (RIN) accepts
RS-232 signal levels that are referenced to isolated ground.
The RIN input is inverted and coupled across the isolation
barrier to appear at the ROUT pin, referenced to logic ground.
The digital signals are transmitted across the isolation barrier
using iCoupler technology. Chip-scale transformer windings
couple the digital signals magnetically from one side of the
barrier to the other. Digital inputs are encoded into waveforms
that are capable of exciting the primary transformer of the winding.
At the secondary winding, the induced waveforms are decoded
into the binary value that was originally transmitted.
There is hysteresis in the VCC input voltage detect circuit.
Once the dc-to-dc converter is active, the input voltage
must be decreased below the turn-on threshold to disable
the converter. This feature ensures that the converter does
not go into oscillation due to noisy input power.
ADM3251E
Rev. 0 | Page 12 of 16
+
+
C3
0.1μF
10V
+
C1
0.1μF
16V
+
C2
0.1μF
16V
0.1μF
+
C4
0.1μF
16V
EIA/TIA-232E OUTPUT
EIA/TIA-232E INPUT
V
ISO
V+
C1+
C1–
T
OUT
R
IN
C2+
C2–
V–
GND
ISO
07
38
8-
01
4
ISOLATION
BARRIER
CMOS OUTPUT
CMOS INPUT
4.5V TO 5.5V
V
CC
R
OUT
T
IN
GND
0.1μF
ADM3251E
Figure 14. Typical Operating Circuit with the DC-to-DC Converter Enabled
(VCC = 4.5 V to 5.5 V)
+
+
C3
0.1μF
10V
+
C1
0.1μF
16V
+
C2
0.1μF
16V
0.1μF
+
C4
0.1μF
16V
EIA/TIA-232E OUTPUT
EIA/TIA-232E INPUT
V
ISO
V+
C1+
C1–
T
OUT
R
IN
C2+
C2–
V–
GND
ISO
07
38
8-
0
15
ISOLATION
BARRIER
CMOS OUTPUT
CMOS INPUT
3.0V TO 3.7V
3.0V TO 5.5V
ISOLATED SUPPLY
V
CC
R
OUT
T
IN
GND
0.1μF
ADM3251E
Figure 15. Typical Operating Circuit with the DC-to-DC Converter Disabled
(VCC = 3.0 V to 3.7 V)
CHARGE PUMP VOLTAGE CONVERTER
The charge pump voltage converter consists of a 200 kHz
oscillator and a switching matrix. The converter generates a
±10.0 V supply from the input 5.0 V level. This is done in two
stages by using a switched capacitor technique as illustrated in
Figure 16 and Figure 17. First, the 5.0 V input supply is doubled
to 10.0 V by using C1 as the charge storage element. The +10.0 V
level is then inverted to generate ?10.0 V using C2 as the storage
element. C3 is shown connected between V+ and VISO, but is
equally effective if connected between V+ and GNDISO.
Capacitors C3 and C4 are used to reduce the output ripple.
Their values are not critical and can be increased, if desired.
Larger capacitors (up to 10 μF) can be used in place of
Capacitors C1, C2, C3, and C4.
GND
C3C1
S1
S2
S3
S4
V+ = 2V
ISO
+ +
INTERNAL
OSCILLATOR
V
ISO
V
ISO
07
38
8-
0
16
Figure 16. Charge Pump Voltage Doubler
GND
ISO
C4C2
S1
S2
S3
S4
GND
ISO
+ +
INTERNAL
OSCILLATOR
V+
V– = –(V+)
FROM
VOLTAGE
DOUBLER
07
38
8-
0
17
Figure 17. Charge Pump Voltage Inverter
5.0 V LOGIC TO EIA/TIA-232E TRANSMITTER
The transmitter driver converts the 5.0 V logic input levels
into RS-232 output levels. When driving an RS-232 load with
VCC = 5.0 V, the output voltage swing is typically ±10 V.
EIA/TIA-232E TO 5 V LOGIC RECEIVER
The receiver is an inverting level-shifter that accepts the RS-232
input level and translates it into a 5.0 V logic output level. The
input has an internal 5 kΩ pull-down resistor to ground and is
also protected against overvoltages of up to ±30 V. An uncon-
nected input is pulled to 0 V by the internal 5 kΩ pull-down
resistor. This, therefore, results in a Logic 1 output level for an
unconnected input or for an input connected to GND. The
receiver has a Schmitt-trigger input with a hysteresis level of
0.1 V. This ensures error-free reception for both a noisy input
and for an input with slow transition times.
HIGH BAUD RATE
The ADM3251E offers high slew rates, permitting data trans-
mission at rates well in excess of the EIA/TIA-232E specifications.
The RS-232 voltage levels are maintained at data rates up to
460 kbps.
THERMAL ANALYSIS
Each ADM3251E device consists of three internal die, attached
to a split-paddle lead frame. For the purposes of thermal analysis,
it is treated as a thermal unit with the highest junction temper-
ature reflected in the θJA value from Table 7. The value of θJA is
based on measurements taken with the part mounted on a
JEDEC standard 4-layer PCB with fine-width traces in still
air. Following the recommendations in the PCB Layout section
decreases the thermal resistance to the PCB, allowing increased
thermal margin at high ambient temperatures.
ADM3251E
Rev. 0 | Page 13 of 16
PCB LAYOUT
Because it is not possible to apply a heat sink to an isolation
device, the device primarily depends on heat dissipating into
the PCB through the GND pins. If the device is used at high
ambient temperatures, care should be taken to provide a
thermal path from the GND pins to the PCB ground plane.
The board layout in Figure 18 shows enlarged pads for Pin 4,
Pin 5, Pin 6, Pin 7, Pin 10, and Pin 11. Multiple vias should be
implemented from each of the pads to the ground plane,
which significantly reduce the temperatures inside the chip.
The dimensions of the expanded pads are left to the discretion
of the designer and the available board space.
The ADM3251E requires no external circuitry for its logic
interfaces. Power supply bypassing is required at the input
and output supply pins (see Figure 18).
The power supply section of the ADM3251E uses a 300 MHz
oscillator frequency to pass power through its chip-scale trans-
formers. In addition, the normal operation of the data section
of the iCoupler introduces switching transients on the power
supply pins. Low inductance capacitors are required to bypass
noise generated at the switching frequency as well as 1 ns pulses
generated by the data transfer and dc refresh circuitry. The total
lead length between both ends of the capacitor and the input
power supply pin should not exceed 20 mm.
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of insula-
tion degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition
to the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADM3251E.
In cases where EMI emission is a concern, series inductance can
be added to critical power and ground traces. Discrete inductors
should be added to the line such that the high frequency bypass
capacitors are between the inductor and the ADM3251E device
pin. Inductance can be added in the form of discrete inductors
or ferrite beads added to both power and ground traces. The
recommended value corresponds to impedance between 50 Ω
and 100 Ω at approximately 300 MHz.
The insulation lifetime of the ADM3251E depends on the
voltage waveform type imposed across the isolation barrier.
The iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 19, Figure 20, and Figure 21 illustrate these
different isolation voltage waveforms.
In applications involving high common-mode transients,
care should be taken to ensure that board coupling across the
isolation barrier is minimized. Furthermore, the board layout
should be designed such that any coupling that does occur
equally affects all pins on a given component side. Failure
to ensure this can cause voltage differentials between pins to
exceed the absolute maximum ratings of the device, thereby
leading to latch-up and/or permanent damage.
Bipolar ac voltage is the most stringent environment. In the
case of unipolar ac or dc voltage, the stress on the insulation is
significantly lower.
0V
RATED PEAK VOLTAGE
073
88
-
0
19
NC
V
CC
V
CC
GND
V
ISO
V+
C1+
C1–
GND T
OUT
GND RIN
GND C2+
R
OUT C2–
T
IN V–
GND GND
ISO
07
38
8-
01
8
ADM3251E
VIA TO GND
ISO
0.1μF
C3
C1
C2
0.1μF
NC = NO CONNECT
C4
Figure 19. Bipolar AC Waveform
0V
RATED PEAK VOLTAGE
07
38
8
-
02
0
Figure 20. Unipolar AC Waveform
0V
RATED PEAK VOLTAGE
073
88
-
021
Figure 21. DC Waveform Outline Dimensions
Figure 18. Recommended Printed Circuit Board Layout
ADM3251E
Rev. 0 | Page 14 of 16
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AC
13.00 (0.5118)
12.60 (0.4961)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75 (0.0295)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10
0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
20 11
10
1
1.27
(0.0500)
BSC
0607
06-
A
45°
Figure 22. 20-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-20)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADM3251EARWZ
1
?40°C to +85°C 20-Lead Standard Small Outline Package [SOIC_W] RW-20
ADM3251EARWZ-REEL
1
?40°C to +85°C 20-Lead Standard Small Outline Package [SOIC_W] RW-20
1
Z = RoHS Compliant Part.
ADM3251E
Rev. 0 | Page 15 of 16
NOTES
ADM3251E
Rev. 0 | Page 16 of 16
NOTES
?2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07388-0-7/08(0)
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