1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
D D
C C
B B
A A
C4
0.1uF
C8
2.2uF
GND
C1
0.1uF
GND
C2
0.1uF
GND
C3
0.1uF
GND
C9
0.1uF
GND
IIC ADDR Select：
High:0x72;
Low:0x70(默认);
Chip_V18
R4 0R
C28
0.1uF
GND
R3
10K
C30
0.1uF
CHIP_RST
MIPI_D3_N
MIPI_D3_P
MIPI_D2_N
MIPI_D2_P
MIPI_DC_N
MIPI_DC_P
MIPI_D1_N
MIPI_D1_P
MIPI_D0_N
MIPI_D0_P
I
2
C
_
A
D
D
R
T
e
s
t
_
E
N
C
H
I
P
_
R
S
T
GND
OUT_D0_P
OUT_D0_N
OUT_D1_N
OUT_D2_N
OUT_D3_N
OUT_D1_P
OUT_D2_P
OUT_D3_P
G
P
I
O
8
G
P
I
O
4
I
2
C
S
_
S
C
L
I
2
C
S
_
S
D
A
G
P
I
O
5
G
P
I
O
0
G
P
I
O
1
C
h
i
p
_
E
N
D
P
_
H
P
D
E
X
T
_
A
U
X
_
N
E
X
T
_
A
U
X
_
P
VDD18
C12
2.2uF
C13
2.2uF
C29
2.2uF
C7
2.2uF
C6
2.2uF
C5
0.1uF
GND
C10
2.2uF
Y1
25MHz
C33
18pF
C31
18pF
R
1
8
N
A
/
1
M
GND
Chip_V18
V
C
C
1
8
_
R
X
P
L
L
1
S
C
L
2
S
D
A
3
G
P
I
O
5
/
I
R
Q
O
2
4
G
P
I
O
0
5
G
P
I
O
1
6
G
P
I
O
6
_
E
N
7
G
P
I
O
7
_
E
X
T
H
P
D
2
8
V
D
D
9
E
X
T
_
A
U
X
N
1
0
E
X
T
_
A
U
X
P
1
1
V
C
C
1
8
_
A
U
X
1
2
EXT_D3N
13
EXT_D3P
14
NC
15
EXT_D2N
16
EXT_D2P
17
NC
18
EXT_D1N
19
EXT_D1P
20
NC
21
EXT_D0N
22
EXT_D0P
23
VCC18_BGP
24
T
E
S
T
_
E
N
2
5
N
C
2
6
V
C
C
1
8
_
X
T
A
L
2
7
X
T
A
L
_
O
2
8
X
T
A
L
_
I
2
9
V
D
D
3
0
S
_
A
D
R
3
1
G
P
I
O
4
3
2
G
P
I
O
8
3
3
G
P
I
O
9
3
4
R
E
S
E
T
_
N
3
5
V
C
C
1
8
_
M
L
R
X
3
6
MLRX_DA3N
37
MLRX_DA3P
38
NC
39
MLRX_DA2N
40
MLRX_DA2P
41
MLRX_DACN
42
MLRX_DACP
43
MLRX_DA1N
44
MLRX_DA1P
45
NC
46
MLRX_DA0N
47
MLRX_DA0P
48
EPAD
49
U1
CS5523
V
D
D
1
8
V
D
D
1
8
V
D
D
1
8
V
D
D
1
8
V
D
D
1
8
V
D
D
1
8
VDD18
VDD18
VDD18
VDD18VDD18VDD18
VDD18
VDD18
R1
NA/10K
Chip_V18
R2
10K
I2C_ADDR
R
5
1
0
K
GND
Chip Software Work Mode:
Low: Auto Mode(don''t need to cfg register by IIC);
High: Half auto mode(you need to cfg register);
R6
NA/10K
Chip_V18
R8
10K
Chip_EN
TP3 TP4 TP5
TP1
G
P
I
O
9
TP2
BIST Enable：
High: Software Auto mode
enable BIST;
Low:Disable BIST(默认) ;
R7
NA/10K
Chip_V18
R9
10K
GPIO4
Chip Reset;
Layout 注意事项:
1、去耦电容尽量靠近电源管脚；
2、MIPI输入按照100Ω差分布线；
3、DP输出按照100Ω差分布线;
4、芯片Epad尽量多打地孔
CS5523_Referece_Design
Title
Size Document Number Rev
Date: Sheet of 41
A
Page01 Main Chip
1.0CS5523_Ref_Design
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