User
’
s
Manual
www.renesas.com
RZ/A1L Group, RZ/A1LU Group,
RZ/A1LC Group
User’s Manual: Hardware
Renesas Microprocessor
RZ Family / RZ/A Series
Jan 2021
32
Rev.6.00
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
Cover
? 2020 Renesas Electronics Corporation. All rights reserved.
Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products
and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your
product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of
these circuits, software, or information.
2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or
other intellectual property rights of third parties, by or arising from the use of Renesas Electronics products or technical information described in this
document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application examples.
3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
4. You shall be responsible for determining what licenses are required from any third parties, and obtaining such licenses for the lawful import, export,
manufacture, sales, utilization, distribution or other disposal of any products incorporating Renesas Electronics products, if required.
5. You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any
and all liability for any losses or damages incurred by you or third parties arising from such alteration, modification, copying or reverse engineering.
6. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for
each Renesas Electronics product depends on the product’s quality grade, as indicated below.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home
electronic appliances; machine tools; personal electronic equipment; industrial robots; etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key
financial terminal systems; safety control equipment; etc.
Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas
Electronics document, Renesas Electronics products are not intended or authorized for use in products or systems that may pose a direct threat to
human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause serious property damage (space system;
undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims
any and all liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is
inconsistent with any Renesas Electronics data sheet, user’s manual or other Renesas Electronics document.
7. No semiconductor product is absolutely secure. Notwithstanding any security measures or features that may be implemented in Renesas Electronics
hardware or software products, Renesas Electronics shall have absolutely no liability arising out of any vulnerability or security breach, including but not
limited to any unauthorized access to or use of a Renesas Electronics product or a system that uses a Renesas Electronics product. RENESAS
ELECTRONICS DOES NOT WARRANT OR GUARANTEE THAT RENESAS ELECTRONICS PRODUCTS, OR ANY SYSTEMS CREATED USING
RENESAS ELECTRONICS PRODUCTS WILL BE INVULNERABLE OR FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE,
HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (“Vulnerability Issues”). RENESAS ELECTRONICS DISCLAIMS ANY AND
ALL RESPONSIBILITY OR LIABILITY ARISING FROM OR RELATED TO ANY VULNERABILITY ISSUES. FURTHERMORE, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, RENESAS ELECTRONICS DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, WITH
RESPECT TO THIS DOCUMENT AND ANY RELATED OR ACCOMPANYING SOFTWARE OR HARDWARE, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.
8. When using Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application notes, “General Notes for
Handling and Using Semiconductor Devices” in the reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by
Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation characteristics, installation, etc. Renesas
Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such
specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific
characteristics, such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Unless designated as a high reliability
product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products
are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury,
injury or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety
design for hardware and software, including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging
degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult and impractical, you are
responsible for evaluating the safety of the final products or systems manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas
Electronics product. You are responsible for carefully and sufficiently investigating applicable laws and regulations that regulate the inclusion or use of
controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics products in compliance with all these
applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance
with applicable laws and regulations.
11. Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is
prohibited under any applicable domestic or foreign laws or regulations. You shall comply with any applicable export control laws and regulations
promulgated and administered by the governments of any countries asserting jurisdiction over the parties or transactions.
12. It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or otherwise sells or
transfers the product to a third party, to notify such third party in advance of the contents and conditions set forth in this document.
13. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
14. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas
Electronics products.
(Note1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled
subsidiaries.
(Note2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
(Rev.5.0-1 October 2020)
Corporate Headquarters Contact Information
TOYOSU FORESIA, 3-2-24 Toyosu,
Koto-ku, Tokyo 135-0061, Japan
www.renesas.com
For further information on a product, technology, the most up-to-date
version of a document, or your nearest sales office, please visit:
www.renesas.com/contact/
Trademarks
Renesas and the Renesas logo are trademarks of Renesas Electronics
Corporation. All trademarks and registered trademarks are the property
of their respective owners.
General Precautions in the Handling of Microprocessing Unit and Microcontroller
Unit Products
The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage
notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have
been issued for the products.
1. Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps
must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be
adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity.
Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be
touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.
2. Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of
register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset
pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins
in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the
level at which resetting is specified.
3. Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O
pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements.
Follow the guideline for input signal during power-off state as described in your product documentation.
4. Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are
generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of
the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal
become possible.
5. Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program
execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator
during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced
with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
6. Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V
IL
(Max.)
and V
IH
(Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level
is fixed, and also in the transition period when the input level passes through the area between V
IL
(Max.) and V
IH
(Min.).
7. Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these
addresses as the correct operation of the LSI is not guaranteed.
8. Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems.
The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms
of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values,
operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-
evaluation test for the given product.
1. Overview........................................................................................................................................1-1
1.1 Features of This LSI............................................................................................................................1-1
1.2 Product Lineup....................................................................................................................................1-9
1.3 Block Diagram.....................................................................................................................................1-9
1.4 Pin Assignment..................................................................................................................................1-10
1.5 Pin Functions.....................................................................................................................................1-14
1.6 List of Pins.........................................................................................................................................1-20
2. CPU...............................................................................................................................................2-1
2.1 Features...............................................................................................................................................2-1
2.2 Configuration Signals..........................................................................................................................2-2
3. Boot Mode......................................................................................................................................3-1
3.1 Features................................................................................................................................................3-1
3.2 Boot Mode and Pin Function Setting..................................................................................................3-1
3.3 Hardware Used in Each Boot Mode....................................................................................................3-2
3.4 Exception Vector Address at a Reset in Each Boot Mode..................................................................3-3
3.5 Operation.............................................................................................................................................3-4
3.5.1 Boot Mode 0...............................................................................................................................3-4
3.5.2 Boot Mode 1...............................................................................................................................3-4
3.5.3 Boot Mode 2...............................................................................................................................3-5
3.5.4 Boot Mode 3...............................................................................................................................3-7
3.6 Notes....................................................................................................................................................3-9
3.6.1 Boot Related Pins.......................................................................................................................3-9
3.6.2 Operation when an Exception Occurs with the Exception Vector
Set to the High Vector Address..................................................................................................3-9
3.6.3 Notes on Serial Flash Booting (Boot Mode 1) after This LSI is Reset......................................3-9
4. Secondary Cache..........................................................................................................................4-1
4.1 Features................................................................................................................................................4-1
4.2 Configuration Signals..........................................................................................................................4-1
5. LSI Internal Bus.............................................................................................................................5-1
5.1 LSI Internal Bus...................................................................................................................................5-1
5.1.1 Configuration..............................................................................................................................5-1
5.1.2 Operation....................................................................................................................................5-1
5.2 North Main Bus...................................................................................................................................5-2
5.2.1 Configuration..............................................................................................................................5-2
5.2.2 Features.......................................................................................................................................5-2
5.2.3 Peripheral Buses.........................................................................................................................5-3
5.3 South Main Bus...................................................................................................................................5-5
5.3.1 Configuration..............................................................................................................................5-5
5.3.2 Features.......................................................................................................................................5-5
5.3.3 Connected Buses.........................................................................................................................5-6
5.4 Address Map........................................................................................................................................5-7
Contents
5.5 Address Remapping...........................................................................................................................5-10
5.5.1 Overview..................................................................................................................................5-10
5.5.2 Operation..................................................................................................................................5-10
5.6 AXI Interconnect...............................................................................................................................5-11
5.6.1 Configuration............................................................................................................................5-11
5.6.2 Operation..................................................................................................................................5-11
5.7 Bus Bridges........................................................................................................................................5-11
5.8 AXI Protocol Control Signals............................................................................................................5-12
5.8.1 Bus Masters other than Cortex-A9, CoreSight, and the Direct Memory Access Controller....5-12
5.8.2 Cortex-A9.................................................................................................................................5-12
5.8.3 CoreSight..................................................................................................................................5-12
5.8.4 Direct Memory Access Controller............................................................................................5-13
5.8.5 Slave Area.................................................................................................................................5-13
5.9 Write Buffers.....................................................................................................................................5-13
5.10 Register Descriptions.........................................................................................................................5-14
5.10.1 Remap Register (RMPR)..........................................................................................................5-15
5.10.2 AXI Bus Control Register 0 (AXIBUSCTL0).........................................................................5-16
5.10.3 AXI Bus Control Register 2 (AXIBUSCTL2).........................................................................5-17
5.10.4 AXI Bus Control Register 5 (AXIBUSCTL5).........................................................................5-17
5.10.5 AXI Bus Control Register 6 (AXIBUSCTL6).........................................................................5-18
5.10.6 AXI Bus Control Register 7 (AXIBUSCTL7).........................................................................5-19
5.10.7 AXI Bus Response Error Interrupt Control Register 0 (AXIRERRCTL0)..............................5-20
5.10.8 AXI Bus Response Error Interrupt Control Register 2 (AXIRERRCTL2)..............................5-21
5.10.9 AXI Bus Response Error Status Register 0 (AXIRERRST0)..................................................5-22
5.10.10 AXI Bus Response Error Status Register 2 (AXIRERRST2)..................................................5-23
5.10.11 AXI Bus Response Error Clear Register 0 (AXIRERRCLR0)................................................5-24
5.10.12 AXI Bus Response Error Clear Register 2 (AXIRERRCLR2)................................................5-25
5.11 Interrupt Request...............................................................................................................................5-26
6. Clock Pulse Generator...................................................................................................................6-1
6.1 Features................................................................................................................................................6-1
6.2 Input/Output Pins.................................................................................................................................6-4
6.3 Clock Mode.........................................................................................................................................6-5
6.4 Register Descriptions...........................................................................................................................6-7
6.4.1 Frequency Control Register (FRQCR).......................................................................................6-7
6.5 Changing the Frequency......................................................................................................................6-9
6.5.1 Changing the Division Ratio......................................................................................................6-9
6.6 Usage of the Clock Pins.....................................................................................................................6-10
6.6.1 In the Case of Inputting an External Clock..............................................................................6-10
6.6.2 In the Case of Using a Crystal Resonator.................................................................................6-11
6.6.3 In the Case of Not Using the Clock Pin....................................................................................6-11
6.7 Oscillation Stabilizing Time..............................................................................................................6-12
6.7.1 Oscillation Stabilizing Time of the On-chip Crystal Oscillator...............................................6-12
6.7.2 Oscillation Stabilizing Time of the PLL circuit.......................................................................6-12
6.8 Notes on Board Design......................................................................................................................6-13
6.8.1 Note on Using a PLL Oscillation Circuit.................................................................................6-13
6.9 Definition of Modulation Rate and Frequency in the SSCG Specification.......................................6-14
6.10 Clock Signals.....................................................................................................................................6-15
6.10.1 Clock Signals for the System and Realtime Clock...................................................................6-15
6.10.2 Audio and USB Clock Signals.................................................................................................6-16
6.10.3 Video Image Clock Signals......................................................................................................6-16
6.10.4 Other Clock Signals..................................................................................................................6-17
6.10.5 Internal Clock Signals (1).........................................................................................................6-18
6.10.6 Internal Clock Signals (2).........................................................................................................6-19
6.11 Usage Note........................................................................................................................................6-20
6.11.1 Notes on the SSCG...................................................................................................................6-20
7. Interrupt Controller.........................................................................................................................7-1
7.1 Features................................................................................................................................................7-1
7.2 Input/Output Pins.................................................................................................................................7-2
7.3 Register Descriptions...........................................................................................................................7-3
7.3.1 Interrupt Control Register 0 (ICR0).........................................................................................7-13
7.3.2 Interrupt Control Register 1 (ICR1).........................................................................................7-14
7.3.3 IRQ Interrupt Request Register (IRQRR)................................................................................7-15
7.4 Interrupt Sources................................................................................................................................7-16
7.4.1 NMI Interrupt...........................................................................................................................7-16
7.4.2 IRQ Interrupts...........................................................................................................................7-16
7.4.3 On-Chip Peripheral Module Interrupts.....................................................................................7-17
7.4.4 Pin Interrupts............................................................................................................................7-18
7.5 Interrupt IDs......................................................................................................................................7-19
7.6 Operation...........................................................................................................................................7-36
7.6.1 Initial Settings...........................................................................................................................7-36
7.6.2 Flow of Interrupt Operations....................................................................................................7-38
7.7 Data Transfer with Interrupt Request Signals...................................................................................7-39
7.7.1 Handling Interrupt Request Signals as Sources for CPU Interrupt
but Not Direct Memory Access Controller Activating.............................................................7-39
7.7.2 Handling Interrupt Request Signals as Sources for Activating
Direct Memory Access Controller but Not CPU Interrupt.......................................................7-39
7.8 Usage Note........................................................................................................................................7-40
7.8.1 Timing to Clear Interrupt Source..............................................................................................7-40
7.8.2 Notes on Selecting IRQ Interrupt Pin Functions......................................................................7-40
7.8.3 Notes on Reading Interrupt ID Values from Interrupt Acknowledge Register (ICCIAR).......7-40
7.8.4 Notes on Using IRQ Pins as Triggers for Release from Standby
when Software Standby is in Use.............................................................................................7-41
8. Bus State Controller.......................................................................................................................8-1
8.1 Features................................................................................................................................................8-1
8.2 Input/Output Pins.................................................................................................................................8-3
8.3 Area Overview.....................................................................................................................................8-4
8.3.1 Address Map...............................................................................................................................8-4
8.3.2 Data Bus Width and Related Pin Setting for Each Area Depending on Boot Mode..................8-5
8.4 Register Descriptions...........................................................................................................................8-6
8.4.1 Common Control Register (CMNCR)........................................................................................8-7
8.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0 to 5)..........................................................8-8
8.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 to 5)......................................................8-10
8.4.4 SDRAM Control Register (SDCR)..........................................................................................8-27
8.4.5 Refresh Timer Control/Status Register (RTCSR)....................................................................8-29
8.4.6 Refresh Timer Counter (RTCNT)............................................................................................8-30
8.4.7 Refresh Time Constant Register (RTCOR)..............................................................................8-30
8.4.8 Timeout Cycle Constant Register (TOSCORn) (n = 0 to 5)....................................................8-31
8.4.9 Timeout Status Register (TOSTR)...........................................................................................8-32
8.4.10 Timeout Enable Register (TOENR).........................................................................................8-34
8.5 Operation...........................................................................................................................................8-35
8.5.1 Access Size and Data Alignment..............................................................................................8-35
8.5.2 Normal Space Interface............................................................................................................8-37
8.5.3 Access Wait Control.................................................................................................................8-42
8.5.4 CSn Assert Period Expansion...................................................................................................8-44
8.5.5 MPX-I/O Interface....................................................................................................................8-45
8.5.6 SDRAM Interface.....................................................................................................................8-48
8.5.7 Burst ROM (Clocked Asynchronous) Interface.......................................................................8-77
8.5.8 SRAM Interface with Byte Selection.......................................................................................8-78
8.5.9 Burst ROM (Clocked Synchronous) Interface.........................................................................8-83
8.5.10 Wait between Access Cycles....................................................................................................8-84
8.5.11 Others........................................................................................................................................8-87
9. Direct Memory Access Controller..................................................................................................9-1
9.1 Features................................................................................................................................................9-1
9.2 Input/Output Pins.................................................................................................................................9-2
9.3 Register Configuration........................................................................................................................9-2
9.4 Register Descriptions...........................................................................................................................9-4
9.4.1 Next Source Address Register n (N0SA_n, N1SA_n).............................................................9-12
9.4.2 Next Destination Address Register n (N0DA_n, N1DA_n).....................................................9-12
9.4.3 Next Transaction Byte Register n (N0TB_n, N1TB_n)...........................................................9-13
9.4.4 Current Source Address Register (CRSA_n)...........................................................................9-13
9.4.5 Current Destination Address Register (CRDA_n)...................................................................9-14
9.4.6 Current Transaction Byte Register (CRTB_n).........................................................................9-14
9.4.7 Channel Status Register n (CHSTAT_n)..................................................................................9-15
9.4.8 Channel Control Register n (CHCTRL_n)...............................................................................9-18
9.4.9 Channel Configuration Register n (CHCFG_n).......................................................................9-20
9.4.10 Channel Interval Register n (CHITVL_n)................................................................................9-22
9.4.11 Channel Extension Register n (CHEXT_n)..............................................................................9-23
9.4.12 Next Link Address Register n (NXLA_n)................................................................................9-24
9.4.13 Current Link Address Register n (CRLA_n)............................................................................9-24
9.4.14 DMA Control Register (DCTRL_0_7, DCTRL_8_15)...........................................................9-25
9.4.15 DMA Status EN Register (DSTAT_EN_0_7)..........................................................................9-26
9.4.16 DMA Status EN Register (DSTAT_EN_8_15)........................................................................9-26
9.4.17 DMA Status ER Register (DSTAT_ER_0_7)..........................................................................9-27
9.4.18 DMA Status ER Register (DSTAT_ER_8_15)........................................................................9-27
9.4.19 DMA Status END Register (DSTAT_END_0_7)....................................................................9-28
9.4.20 DMA Status END Register (DSTAT_END_8_15)..................................................................9-28
9.4.21 DMA Status TC Register (DSTAT_TC_0_7)..........................................................................9-29
9.4.22 DMA Status TC Register (DSTAT_TC_8_15)........................................................................9-29
9.4.23 DMA Status SUS Register (DSTAT_SUS_0_7)......................................................................9-30
9.4.24 DMA Status SUS Register (DSTAT_SUS_8_15)....................................................................9-30
9.4.25 DMA Extension Resource Selectors 0 to 7 (DMARS0 to DMARS7).....................................9-31
9.5 Operation...........................................................................................................................................9-34
9.5.1 Transfer Flow...........................................................................................................................9-34
9.5.2 DMA Transfer Requests...........................................................................................................9-34
9.6 DMA Mode........................................................................................................................................9-39
9.6.1 Mode Setting.............................................................................................................................9-39
9.6.2 Register Mode...........................................................................................................................9-39
9.6.3 Link Mode................................................................................................................................9-45
9.7 DMA Transfer...................................................................................................................................9-52
9.7.1 Transfer Mode..........................................................................................................................9-52
9.7.2 Priority Control for DMA Channels.........................................................................................9-53
9.7.3 Number of States of an External Bus Cycle.............................................................................9-55
9.7.4 DMA Transfer Request............................................................................................................9-55
9.7.5 DMA Acknowledge Output Function......................................................................................9-57
9.7.6 DMA Transfer End Output Function........................................................................................9-59
9.7.7 DMA Transfer End Interrupt....................................................................................................9-59
9.7.8 DMA Error Interrupt................................................................................................................9-60
9.7.9 Interval Count Function............................................................................................................9-60
9.7.10 Difference in Operation Due to the Transfer Size....................................................................9-61
9.7.11 Transfer Status..........................................................................................................................9-62
9.8 DMA Setting Examples.....................................................................................................................9-66
9.8.1 Setting Example 1 (Register Mode/Hardware Request)...........................................................9-66
9.8.2 Setting Example 2 (Register Mode/Software Request)............................................................9-68
9.8.3 Setting Example 3 (Register Mode/Continuous Execution).....................................................9-70
9.8.4 Setting Example 4 (Link Mode)...............................................................................................9-71
9.8.5 Next Register Set Continuous Execution Setting.....................................................................9-74
9.9 Note...................................................................................................................................................9-76
9.9.1 Divided Output of DACK0 and TEND0..................................................................................9-76
9.9.2 TEND0 Not Output..................................................................................................................9-77
9.9.3 Atomic Access (ARLOCK[1:0] and AWLOCK[1:0]).............................................................9-77
10. Multi-Function Timer Pulse Unit 2................................................................................................10-1
10.1 Features..............................................................................................................................................10-1
10.2 Input/Output Pins...............................................................................................................................10-5
10.3 Register Descriptions.........................................................................................................................10-6
10.3.1 Timer Control Register (TCR).................................................................................................10-8
10.3.2 Timer Mode Register (TMDR)...............................................................................................10-11
10.3.3 Timer I/O Control Register (TIOR)........................................................................................10-13
10.3.4 Timer Interrupt Enable Register (TIER)................................................................................10-31
10.3.5 Timer Status Register (TSR)..................................................................................................10-33
10.3.6 Timer Buffer Operation Transfer Mode Register (TBTM)....................................................10-36
10.3.7 Timer Input Capture Control Register (TICCR)....................................................................10-37
10.3.8 Timer A/D Converter Start Request Control Register (TADCR)..........................................10-38
10.3.9 Timer A/D Converter Start Request Cycle Set Registers
(TADCORA_4 and TADCORB_4).......................................................................................10-40
10.3.10 Timer A/D Converter Start Request Cycle Set Buffer Registers
(TADCOBRA_4 and TADCOBRB_4)..................................................................................10-40
10.3.11 Timer Counter (TCNT)..........................................................................................................10-40
10.3.12 Timer General Register (TGR)...............................................................................................10-41
10.3.13 Timer Start Register (TSTR)..................................................................................................10-42
10.3.14 Timer Synchronous Register (TSYR)....................................................................................10-43
10.3.15 Timer Read/Write Enable Register (TRWER).......................................................................10-44
10.3.16 Timer Output Master Enable Register (TOER)......................................................................10-45
10.3.17 Timer Output Control Register 1 (TOCR1)...........................................................................10-46
10.3.18 Timer Output Control Register 2 (TOCR2)...........................................................................10-48
10.3.19 Timer Output Level Buffer Register (TOLBR)......................................................................10-51
10.3.20 Timer Gate Control Register (TGCR)....................................................................................10-52
10.3.21 Timer Subcounter (TCNTS)...................................................................................................10-53
10.3.22 Timer Dead Time Data Register (TDDR)..............................................................................10-53
10.3.23 Timer Cycle Data Register (TCDR).......................................................................................10-54
10.3.24 Timer Cycle Buffer Register (TCBR)....................................................................................10-54
10.3.25 Timer Interrupt Skipping Set Register (TITCR)....................................................................10-55
10.3.26 Timer Interrupt Skipping Counter (TITCNT)........................................................................10-57
10.3.27 Timer Buffer Transfer Set Register (TBTER)........................................................................10-58
10.3.28 Timer Dead Time Enable Register (TDER)...........................................................................10-59
10.3.29 Timer Waveform Control Register (TWCR)..........................................................................10-60
10.3.30 Bus Master Interface...............................................................................................................10-60
10.4 Operation.........................................................................................................................................10-61
10.4.1 Basic Functions.......................................................................................................................10-61
10.4.2 Synchronous Operation..........................................................................................................10-67
10.4.3 Buffer Operation.....................................................................................................................10-69
10.4.4 Cascaded Operation................................................................................................................10-73
10.4.5 PWM Modes...........................................................................................................................10-78
10.4.6 Phase Counting Mode.............................................................................................................10-82
10.4.7 Reset-Synchronized PWM Mode...........................................................................................10-88
10.4.8 Complementary PWM Mode..................................................................................................10-91
10.4.9 A/D Converter Start Request Delaying Function.................................................................10-126
10.4.10 TCNT Capture at Crest and/or Trough in Complementary PWM Operation......................10-129
10.5 Interrupt Sources............................................................................................................................10-130
10.5.1 Interrupt Sources and Priorities............................................................................................10-130
10.5.2 Activation of Direct Memory Access Controller.................................................................10-131
10.5.3 A/D Converter Activation....................................................................................................10-131
10.6 Operation Timing..........................................................................................................................10-133
10.6.1 Input/Output Timing.............................................................................................................10-133
10.6.2 Interrupt Signal Timing........................................................................................................10-138
10.7 Usage Notes...................................................................................................................................10-141
10.7.1 Module Standby Mode Setting.............................................................................................10-141
10.7.2 Input Clock Restrictions.......................................................................................................10-141
10.7.3 Caution on Period Setting.....................................................................................................10-142
10.7.4 Contention between TCNT Write and Clear Operations......................................................10-142
10.7.5 Contention between TCNT Write and Increment Operations..............................................10-143
10.7.6 Contention between TGR Write and Compare Match.........................................................10-143
10.7.7 Contention between Buffer Register Write and Compare Match.........................................10-144
10.7.8 Contention between Buffer Register Write and TCNT Clear..............................................10-145
10.7.9 Contention between TGR Read and Input Capture..............................................................10-145
10.7.10 Contention between TGR Write and Input Capture.............................................................10-146
10.7.11 Contention between Buffer Register Write and Input Capture............................................10-146
10.7.12 TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection...................10-147
10.7.13 Counter Value during Complementary PWM Mode Stop...................................................10-148
10.7.14 Buffer Operation Setting in Complementary PWM Mode...................................................10-148
10.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag.................................10-149
10.7.16 Overflow Flags in Reset Synchronous PWM Mode............................................................10-150
10.7.17 Contention between Overflow/Underflow and Counter Clearing........................................10-150
10.7.18 Contention between TCNT Write and Overflow/Underflow...............................................10-151
10.7.19 Cautions on Transition from Normal Operation or PWM Mode 1
to Reset-Synchronized PWM Mode.....................................................................................10-151
10.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized PWM Mode........10-151
|
|
