云上大讲堂—最新USB4 规范 解析及 一致性 测试
主讲人：李煜—— 泰克高级应用工程师
2021/4/28
1资深工程师在线“营业”，
与您分享热门主题，共话前沿知识，
每月两期，与您相约泰克直播间！
主题 时间
泰克和新能源直播的那些事儿 3.5
纳米发电机测试难点及解决方法 3.19
更高速率，更高密度，400G PAM4 正出发 4.2
5G CPE 芯片及模块应用测试 4.23
最新USB4 规范解析及一致性测试 4.28
宽禁带半导体器件静态测试规范解读 4.30
新型计算框架及忆阻器、神经元网络 测试 5.14
关注“ 泰克科技” 服务号
汽车雷达模块应用与测试挑战 5.28Agenda
Background
What is USB4?
How to test USB4 products?
What can Tektronix provide for USB4 testing?
28 APRIL 2021 3BackgroundEvolution of Peripheral Interface
We have experienced three ages!
Before USB Before Type-C Wonderful Type-C
28 APRIL 2021 5Std-Series Mini-Series Mirco-Series
Plug Receptacle Plug Receptacle Plug Receptacle
A
B
N.A
C
USB Roadmap and Current Status
USB4: ~ 40 Gbps
USB 2.0: ~ 480 Mbps USB 3.1: ~ 10 Gbps
2000 2013 2019
2008
1996
2017
USB 3.0: ~ 5 Gbps USB 3.2 ~ 20 Gbps
USB 1.x: ~ 12Mbps
28 APRIL 2021 7Quick Reference Table
Dual Speed Total
Mode Name Old Names Encoding Marketing Name Logo
Lane per Lane Speed
USB 3.2 Gen1 x1 USB 3.0, USB 3.1 Gen1 8b/10b No 5 5 SuperSpeed USB 5Gbps
USB 3.2 Gen1 x2 N/A 8b/10b Yes 5 10 N/A
USB 3.2 Gen2 x1 USB 3.1 Gen2 128b/132b No 10 10 SuperSpeed USB 10Gbps
USB 3.2 Gen2 x2 N/A 128b/132b Yes 10 20 SuperSpeed USB 20Gbps
USB4 Gen2 x1 N/A 64b/66b No 10 10 N/A
USB4 Gen2 x2 N/A 64b/66b Yes 10 20 USB4 20Gbps
USB4 Gen3 x1 N/A 128b/132b No 20 20 N/A
USB4 Gen3 x2 N/A 128b/132b Yes 20 40 USB4 40Gbps
28 APRIL 2021 8USB Bus Topology
DFP: Downstream Facing Port
Physical Topology: DFP vs. UFP
UFP: Upstream Facing Port
Hub
DFP Upstream
UFP
Func
Downstream
28 APRIL 2021 9What is USB4?
? USB Type-C
? USB PD
? USB4 Router
? USB4 PHYUSB4 Operation Process
USB Type-C Spec USB PD 3.0 Spec USB4 Spec
Detect a valid Establish an explicit Discovery
Enter_USB
CC
attach power contract Identity
Initial VBUS and Negotiated power
VBUS
VCONN is provided is provided
USB
Data Bus
enumeration
11The Magical Type-CThe Magical Type-C
Full-Featured Type-C Receptacle and Plug
Tx High-speed data path Rx High-speed data path
USB 2.0
(USB, or TBT/DP Alt-Mode)
(USB, or TBT/DP Alt-Mode)
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
Receptacle
GND TX1+ TX1- VBUS CC1 D+ D- SBU1 VBUS RX2- RX2+ GND
(Front View)
GND RX1+ RX1- VBUS SBU2 D- D+ CC2 VBUS TX2- TX2+ GND
B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1
Sideband Use
Plug configuration detection
(used for USB4,
? One is used for USB-PD
and Alt-modes)
communication
? The Other can become
VCONN for cable power
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1
GND RX2+ RX2- VBUS SBU1 D- D+ CC1 VBUS TX1- TX1+ GND
Plug
(Front View)
GND TX2+ TX2- VBUS VCONN SBU2 VBUS RX1- RX1+ GND
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12
28 APRIL 2021 13The Magical Type-C
Mechanism for plug freely
“Within a standard USB Type-C cable, only a single CC pin position within
each plug of the cable is connected through the cable.”
--- from “USB Type-C spec 2.0(p33)”
28 APRIL 2021 14USB Full-Featured Type-C Cable Assembly
Paddle Card with an eMarker IC
eMarker IC
28 APRIL 2021 15USB Full-Featured Type-C Cable Assembly
导线18可能不存在
Wire Schematic with an eMarker IC
Plug Paddle Card Raw Cable Paddle Card Plug
3: CC
CC1(A5) CC1(A5)
18: PWR_VCONN
ISO ISO
CC2(B5) CC2(B5)
6: SDPp1
TX1+(A2) TX1+(A2)
7: SDPn1
TX1-(A3) TX1-(A3)
8: SDPp2
RX1+(B11) RX1+(B11)
9: SDPn2
RX1-(B10) RX1-(B10)
10: SDPp3
TX2+(B2) TX2+(B2)
11: SDPn3
TX2-(B3) TX2-(B3)
12: SDPp4
RX2+(A11) RX2+(A11)
13: SDPn4
RX2-(A10) RX2-(A10)
4: UTP_Dp
D+(A6) D+(A6)
5: UTP_Dn
D-(A7) D-(A7)
D+(B6) D+(B6)
D-(B7) D-(B7)
14: SBU_A
SBU1(A8) SBU1(A8)
15: SBU_B
SBU2(B8) SBU2(B8)
VBUS(A4) VBUS(A4)
2: PWR_VBUS1
VBUS(A9) VBUS(A9)
VBUS(B4) VBUS(B4)
VBUS(B9) VBUS(B9)
GND(A1) GND(A1)
1: GND_PWRrt1
GND(A12) GND(A12)
GND(B1) GND(B1)
GND(B12) GND(B12)
28 APRIL 2021 16The Magical Type-C
Plug Up Orientation
“ pside p”
28 APRIL 2021 17The Magical Type-C
Plug Down Orientation
“ pside own”
28 APRIL 2021 18Single-Lane Configuration
Un-flipped straight through
主机检测到CC1被端接，从而配置TX1/RX1 发 送数据；
设备也检测到CC1 被端接，从而MUX 选通到TX1/RX1 ；
Receptacle Receptacle
TX1 TX1
RX1 RX1
MUX
USB USB
TX2 TX2
chipset chipset
RX2 RX2
(Host) (Device)
USB D+/ USB D+/
CC1 CC1
CC Logic and CC Logic and
VCONN Switch VCONN Switch
CC2 CC2
28 APRIL 2021 19Single-Lane Configuration
Un-flipped twisted through
主机检测到CC1被端接，从而配置TX1/RX1 发 送数据；
设备检测到CC2被端接，从而MUX 选通到TX2/RX2 ；
Receptacle Receptacle
TX1 TX1
RX1 RX1
MUX
USB USB
TX2 TX2
chipset chipset
RX2 RX2
(Host) (Device)
USB D+/ USB D+/
CC1 CC1
CC Logic and CC Logic and
VCONN Switch VCONN Switch
CC2 CC2
28 APRIL 2021 20Single-Lane Configuration
Flipped straight through
主机检测到CC2被端接，从而配置TX2/RX2 发 送数据；
设备也检测到CC2 被端接，从而MUX 选通到TX2/RX2 ；
Receptacle Receptacle
TX1 TX1
RX1 RX1
MUX
USB USB
TX2 TX2
chipset chipset
RX2 RX2
(Host) (Device)
USB D+/ USB D+/
CC1 CC1
CC Logic and CC Logic and
VCONN Switch VCONN Switch
CC2 CC2
28 APRIL 2021 21Single-Lane Configuration
Flipped twisted through
主机检测到CC2被端接，从而配置TX2/RX2 发 送数据；
设备检测到CC1被端接，从而MUX 选通到TX1/RX1 ；
Receptacle Receptacle
TX1 TX1
RX1 RX1
MUX
USB USB
TX2 TX2
chipset chipset
RX2 RX2
(Host) (Device)
USB D+/ USB D+/
CC1 CC1
CC Logic and CC Logic and
VCONN Switch VCONN Switch
CC2 CC2
28 APRIL 2021 22主机检测到CC1 被端接，从而TX1/RX1 为主机侧的
Dual-Lane Configuration
Lane0 ；相应地，TX2/RX2 则为Lane1 ；
Un-flipped straight through
设备检测到CC1 被端接，从而TX1/RX1 通过MUX 选通
到Lane0 ；相应 地，TX2/RX2通过MUX 选通到Lane1 ；
Receptacle Receptacle
L0
Lane 0
TX1 TX1
RX1 RX1
MUX
USB USB
L1
Lane 1
TX2 TX2
chipset chipset
RX2 RX2
(Host) (Device)
USB D+/ USB D+/
CC1 CC1
CC Logic and CC Logic and
VCONN Switch VCONN Switch
CC2 CC2
28 APRIL 2021 23主机检测到CC1 被端接，从而TX1/RX1 为主机侧的
Dual-Lane Configuration
Lane0 ；相应地，TX2/RX2 则为Lane1 ；
Un-flipped twisted through
设备检测到CC2 被端接，从而TX2/RX2 通过MUX 选通
到Lane0 ；相应 地，TX1/RX1通过MUX 选通到Lane1 ；
Receptacle Receptacle
L0
TX1 TX1
RX1 RX1
MUX
USB USB
L1
TX2 TX2
chipset chipset
RX2 RX2
(Host) (Device)
USB D+/ USB D+/
CC1 CC1
CC Logic and CC Logic and
VCONN Switch VCONN Switch
CC2 CC2
28 APRIL 2021 24主机检测到CC2 被端接，从而TX2/RX2 为主机侧的
Dual-Lane Configuration
Lane0 ；相应地，TX1/RX1 则为Lane1 ；
Flipped straight through
设备检测到CC2 被端接，从而TX2/RX2 通过MUX 选通
到Lane0 ；相应 地，TX1/RX1通过MUX 选通到Lane1 ；
Receptacle Receptacle
L0
Lane 1
TX1 TX1
RX1 RX1
MUX
USB USB
L1
Lane 0
TX2 TX2
chipset chipset
RX2 RX2
(Host) (Device)
USB D+/ USB D+/
CC1 CC1
CC Logic and CC Logic and
VCONN Switch VCONN Switch
CC2 CC2
28 APRIL 2021 25主机检测到CC2 被端接，从而TX2/RX2 为主机侧的
Dual-Lane Configuration
Lane0 ；相应地，TX1/RX1 则为Lane1 ；
Flipped twisted through
设备检测到CC1 被端接，从而TX1/RX1 通过MUX 选通
到Lane0 ；相应 地，TX2/RX2通过MUX 选通到Lane1 ；
Receptacle Receptacle
L0
TX1 TX1
RX1 RX1
MUX
USB USB
L1
TX2 TX2
chipset chipset
RX2 RX2
(Host) (Device)
USB D+/ USB D+/
CC1 CC1
CC Logic and CC Logic and
VCONN Switch VCONN Switch
CC2 CC2
28 APRIL 2021 26Summary
USB Type-C Spec USB PD 3.0 Spec USB4 Spec
Detect a valid Establish an explicit Discovery
Enter_USB
CC
attach power contract Identity
After Type-C Process:
1. the plug orientation have been
Initial VBUS and Negotiated power
VBUS
determined
VCONN is provided is provided
2. Initial VBUS and VCONN is provided
USB
Data Bus
enumeration
27USB PDUSB4 Discovery and Entry
Power delivery protocol – Configuration Channel (CC)
? USB PD is used to establish the power contract between
the port partner
? U PD “D s v I t t ” s s b th DFP
(Downstream Facing Port) to identify port and cable
capabilities
? If the cable and port both support USB4 operation, the DFP
ss s U PD “E t _U ” m ssag t b th abl a
port to enter USB4 operation
? If both ports are DRD (Dual Role Data) capable, either the
DFP or UFP can optionally initiate a data role swap in order
to exchange host and device roles
? U PD “Data_R s t” mma a b s t t at a
exit from USB4
28 APRIL 2021 29Summary
Two Keywords in USB
PD Spec ：
? Capability
? Mode
USB Type-C Spec USB PD 3.0 Spec USB4 Spec
After PD Process:
Detect a valid Establish an explicit Discovery
Enter_USB
CC
1. Establish an power contract
attach power contract Identity
2. Discovery modes and enter
modes
Initial VBUS and Negotiated power
VBUS
VCONN is provided is provided
USB
Data Bus
enumeration
30USB4 RouterUSB4 Building Blocks
High Level Overview
Tunneled Protocol Tunneled Protocol
USB3 USB3
USB4
USB4 USB4
DisplayPort DisplayPort
Fabric
Router Router
PCIe PCIe
The Router building block is the key component in USB4 Architecture.
28 APRIL 2021 32USB4 Host as an Example
DP Source
Host I/F
Adapter
DP DN
Adapter
Enhanced
USB 2.0 Host
PCIe DN
SuperSpeed Host
PCIe Controller
Host Router
Adapter
USB3 DN
Adapter
USB4 Lane
Adapter
USB 3.2
Signaling DP
USB4 Signaling Signaling
USB 2.0 Signaling
USB Type-C Receptacle
28 APRIL 2021 33USB 2.0 over Type-C
DP Source
Host I/F
Adapter
DP DN
Adapter
Enhanced
USB 2.0 Host
PCIe DN
SuperSpeed Host
PCIe Controller
Host Router
Adapter
USB3 DN
Adapter
USB4 Lane
Adapter
USB 3.2
Signaling DP
USB4 Signaling Signaling
USB 2.0 Signaling
USB Type-C Receptacle
28 APRIL 2021 34USB 3.2 Over USB4
DP Source
Host I/F
Adapter
DP DN
Adapter
Enhanced
USB 2.0 Host
PCIe DN
SuperSpeed Host
PCIe Controller
Host Router
Adapter
USB3 DN
Adapter
USB4 Lane
USB3 Protocol Adapter
USB 3.2
Tunneling: Used
Signaling DP
by USB4 Device
USB4 Signaling Signaling
Used by Legacy
USB 3.2 Device
USB 2.0 Signaling
USB Type-C Receptacle
28 APRIL 2021 35DP over USB4
DP Source
Host I/F
Adapter
DP DN
Adapter
Enhanced
USB 2.0 Host
PCIe DN
SuperSpeed Host
PCIe Controller
Host Router
Adapter
USB3 DN
Adapter
USB4 Lane
Used by DP Alt
DP Protocol Adapter
USB 3.2
Mode Device
Tunneling: Used
Signaling DP
by USB4 Device
USB4 Signaling Signaling
USB 2.0 Signaling
USB Type-C Receptacle
28 APRIL 2021 36PCIe over USB4
DP Source
Host I/F
Adapter
DP DN
Adapter
Enhanced
USB 2.0 Host
PCIe DN
SuperSpeed Host
PCIe Controller
Host Router
Adapter
USB3 DN
Adapter
USB4 Lane
PCIe Protocol Adapter
USB 3.2
Tunneling: Used
Signaling DP
by USB4 Device
USB4 Signaling Signaling
USB 2.0 Signaling
USB Type-C Receptacle
28 APRIL 2021 37How can an USB4 Router do So Many Things?
PCIe
Signaling
PCIe-Specific
Implementation
PCIe
Traffic
Configuration
PCIe-Protocol
Layer
Adapter Layer
Control
Protocol Protocol
Protocol
PCIe Tunneled Packet
Adapter Adapter
Packet Sequence Sequence
Adapter
USB3 DP
USB3 Tunneled DP Tunneled
Packet Sequence Packet Sequence
Traffic Traffic
DP
USB 3.2
Switch
Signaling
Signaling
Tunneled Packet
Sequence
Transport Layer
Transport Layer Packet
Sequence
Lane
Adapter
Logical Layer
Byte Stream
Electrical Layer
USB4 Signaling
28 APRIL 2021 38
USB3-Specific
Implementation
USB3-Protocol
Adapter Layer
DP-Protocol
Adapter Layer
DP-Specific
ImplementationSummary of USB Router
USB 3.x
Multiple protocol onto a single PHY
Intel VESA
USB 2 USB 3 DP
TBT
? Allows USB, DisplayPort and PCIe Tunneling
(multiple protocol onto a single physical interface)
USB Power Delivery
USB Type-C Connector
? USB4 enables the next generation of USB
performance over existing USB Type-C cables
? Enables automatic allocation (Display vs Data)
USB-IF
? Backward compatibility with USB and
Intel
USB4
Thunderbolt3
TBT
VESA
USB Specification
? USB4 specification is based on Thunderbolt3
PCIe
protocol specification
USB 2 USB 3 USB X DP
PCI-SIG
CIO Transport Layer
? Third party vendors can now build Thunderbolt3
VESA
USB Power Delivery
compatible SOC/Integrated or peripheral silicon
USB Type-C Connector
28 APRIL 2021 39USB4 PHY
Typical SerDes Architecture
? Logical Layer
? Electrical LayerUSB4 Links and Lanes
? USB4 Link = the logical connection between two USB4 ports
? Transports USB4 packets between connected USB4 products
? USB4 Lane
? Two differential signal pairs (Tx/Rx)
? Operates at Gen2 (10 Gbps) or Gen3 (20 Gbps)
? Sideband (SB) Channel
? Two-wire channel
? Used for link initialization and management
28 APRIL 2021 41Signaling Comparison
USB 3.1 vs USB 3.2 vs USB4 vs TBT3.0
28 APRIL 2021 42USB4 Logical Layer
Packet flow
? USB4 data path employs a combination of Forward Error
Correction (FEC) and Pre-Coding for obtaining enhanced data
integrity
? The FEC is based on low-complexity/low-latency Reed-
8
Solomon RS(198,194) over GF(2 ) with two correctable errors
per block
? The Pre-Coder is designed for converting bursts of consecutive
bit-errors into two errors at the beginning and end of the burst
? A high level of protection is obtained for long bursts of errors,
which might be introduced by Decision-Feedback-Equalizers
(DFE)
? Note: USB4 Electrical Tx and Rx tests are performed in stand-
alone mode w/o applying pre-coding and FEC
28 APRIL 2021 43USB4 Electrical Layer
Logical 1 & 0 can be hard to distinguish
Channel loss causes the closed eye at receiver pin
at end of long interconnects; (this is
Clean, open, logical 1 & 0 often called a “closed eye”)
at launch from transmitter
Tx
+ path +
+ +
Rcv
- -
- -
Fast, sharp, edges at Smeared edges at end
transmitter launch of long interconnect.
28 APRIL 2021 44USB4 Electrical Layer
Equalization Implementation in USB4
1-tap for USB4
Transmitter Channel Receiver
3-tap FFE CTLE DFE
C
-1
n-tap
C R R C
O O O O
feedback
-1
Do+ Do-
Z
Di+
C Σ
0 Di-
C
FB Slicer
TP2P
-1
x Σ y
k k
Z
R
FB
I /2 I /2
0 0
Eye Diagram
C
+1
? FFE: Feed Forward Equalization
? CTLE: Continuous Time Linear Equalization
? DFE: Decision Feedback Equalization
28 APRIL 2021 45????????????????????????????????????????????????????????????
USB4 Electrical Layer
Transmitter Equalization
pre-cursor
coefficient
C
-1
-1
Z
cursor
coefficient
C Σ
0
-1
post-cursor
Z
coefficient
C
+1
? + +
? 1 0 + 1
????????? = 20 ? log = 20 ? log
+ +
? 1 0 + 1
+ +
? 1 0 + 1
????? = 20 ? log = 20 ? log
+ ?
? 1 0 + 1
28 APRIL 2021 46USB4 Channel Budget
Insertion loss
Gen2 (10Gbps)@5GHz 5.5dB 12dB 5.5dB
Gen3 (20Gbps)@10GHz 7.5dB 7.5dB 7.5dB
? USB4 Router Assembly (Host/Device) insertion-loss of the physical media is Informative
? Insertion-l ss l s l a , t g at t’s a kag , PC t a , a ta l t g
? The reference point TP2 is defined such that the insertion-loss from the connector pad to compliance points is 0.5dB ±
0.25dB at 5GHz and 1dB ± 0.25dB at 10GHz.
? Compliance Board (Test Fixture) shall be comprised of a USB Type-C Plug or Receptacle and a short PCB trace.
? USB4 Gen2 (10Gbps) and USB3.1/3.2 Gen2 (10Gbps) total channel budget is 23dB @ 5GHz. But the budget allocation
(Host+ Cable+ Device) is different between USB4 Gen2 (5.5dB+12dB+5.5dB) and USB3.2 Gen2 (8.5dB+6dB+8.5dB).
28 APRIL 2021 47USB4 Lane Initialization
Sideband (SBTX/SBRX)
? Phase 1: Determination of Initial Conditions
? Router discovers connection information (USB PD)
? Router continues to Phase 2 only if the Link is USB4
? Phase 2: Router Detection
? Host Router driving SBTX to logic high
? Device Router SBTX to logic high after detecting logic high on its SBRX
? Phase 3: Determination of Port Characteristics
? Deciding on the link parameters
? Enabling – Lanes on each side
? Speed – Adapter and cable support Gen3 or not
? RS-FEC – Enabled of both side request
? Phase 4: Lane Parameters Synchronization and Transmit Start
? Router periodically sends a Broadcast Re-Timer Type (RT) transaction with its decision
? Upon reception of Broadcast RT transaction a Router activates the Transmitter and
start sending the training sequence
28 APRIL 2021 48USB4 Lane Initialization
Sideband (SBTX/SBRX)
? Phase 5: Link Equalization
? Transmitter Feed Forward Equalization (TxFFE) initiated by the receiver & sets
transmitter parameters to improve signal over media
? Parallel execution in each segment, symmetrical for each direction on each lane
1. Tx with default parameters
2. Rx evaluates signal
3. x h ks f ‘Rx L k ’
4. Rx wa ts t t ff t a am t s t ‘N w R q’
5. Tx receives the new request
6. Tx updates the parameters
7. Rx evaluates new signal
8. x h ks f ‘Rx L k ’
9. Rx at s ‘Rx L k ’
10. TxFFE completes
? Sideband is shared for all TxFFE
? When a Re-Timer finishes TxFFE on both lanes, it is ready for Clock
Switch
28 APRIL 2021 49How to test USB4 products?
? This webinar Only focus on Electrical CTS Testing of End Products(not Silicon)Compliance Test Specifications for USB4 Products
Required CTS
USB PD CTS USB 2.0 CTS
USB4 PHY CTS
USB Type-C CTS
28 APRIL 2021 51Compliance Test Specifications for USB4 Products
Optional CTS
USB 3.2 Gen1 CTS Thunderbolt 3.0 CTS
USB 3.2 Gen2 CTS
DisplayPort 1.4a CTS
28 APRIL 2021 52USB4 Certification Requirement
Electrical compliance test
Test Group
Host Hub/Dock Device
USB Type-C Compliance
Yes Yes Yes
USB PD 2.0 Compliance
Yes Yes Yes
Gen2
Yes Yes Yes
USB4 Electrical Compliance
Gen3
If Supported Yes If Supported
USB 3.2 Electrical Compliance
Yes Yes If Supported
USB 2.0 Electrical Compliance
Yes Yes Yes
DP Alt Mode Electrical Compliance
Yes Yes If Supported
TBT Alt Mode Electrical Compliance
If Supported Yes If Supported
Note: We can understand this CTS test matrix requirements well, from the perspective of a
product manager.
28 APRIL 2021 53USB4 Electrical Compliance Testing
Overview of Test Items
Three test sub-groups:
? Router Assembly Transmitter Testing
? Test on TX0+/TX0-, TX1+/TX1-
? Router Assembly Receiver Testing
? Test on RX0+/RX0-, RX1+/RX1-
? Router Assembly Sideband Signal Testing
? Test on SBTX/SBRX
28 APRIL 2021 54USB4 Electrical Compliance Testing
Definition of Test points
? USB4 Router assembly electrical testing is measured at the Type-C connector using a compliance
plug/receptacle fixture.
? TP2: Transmitter Port connector output
? TP3: Receiver Port connector input
? The USB4 Tx waveform are captured at TP2, and the passive cable model will be embedded to make it TP3.
? All measurements at TP3 will be done by applying reference equalization
? USB4 Router assembly can have up to 2 Re-timers between Router and Type-C connector.
55USB4 Electrical Compliance Testing
Tx Measurement Setup
? Some measurements are
performed at TP2; the others
are performed at TP3.
? TP2 and TP3 testing is done
with the same setup. For
TP3 measurement''s, the
passive cable is embedded
over the scope.
28 APRIL 2021 56USB4 Electrical Compliance Testing
Tx Measurements at TP2
Test List Gen2/Gen3 Pattern used Test Objective
Transmitter Equalization SQ128 (64 0’s and 64 1’s) Confirm that the transmitter equalization falls within the limits of all 16 presets.
Transmitter Minimum Unit Interval PRBS31 Checking the Minimum Unit Interval
Transmitter SSC Down Spread Range PRBS31 Checking the Dynamic range of SSC down-spreading during steady-state
Transmitter SSC Down Spread Rate PRBS31 Confirm that the SSC down-spreading modulation rate during steady-state falls within the limits
Transmitter SSC Phase Deviation PRBS31 Confirm that the Phase jitter associated with the SSC modulation during steady-state falls within the limits
Transmitter SSC Slew Rate PRBS31 Confirm that the SSC Slew Rate during steady-state falls within the limits
Transmitter TX Frequency Variation Training PRBS31, SQ128 (64 0’s and 64 1’s), SQ4 Confirm that the Frequency variation during Link training falls within the limits – more details in the coming slides
Transmitter Rise/Fall Time SQ128 (64 0’s and 64 1’s) Confirm that the rise time and fall time (20-80%) on the USB4 differential signals falls within the limits
Transmitter Electrical Idle Voltage Electrical idle mode Confirm that the TX peak voltage during transmit electrical idle do not exceed the spec limit
Transmitter Total Jitter PRBS15, SQ2 Confirm that the transmitter Total Jitter referenced to 1E-13 statistics falls within the limits
Transmitter UJ PRBS15 Confirm that the transmitter Sum of uncorrelated DJ and RJ components falls within the limits. UJ=TJ-DDJ
Transmitter UDJ PRBS15 Confirm that the transmitter Uncorrelated Deterministic Jitter falls within the limits
Transmitter DDJ PRBS15 Confirm that the transmitter Data Dependent jitter falls within the limits
Transmitter Low Frequency UDJ PRBS15 Confirm that the transmitter low frequency Uncorrelated Deterministic Jitter falls within the limits. same as UDJ
but adding 2nd order Low-Pass-Filter (LPF) with 3dB cut-off at 0.5MHz
Transmitter DCD PRBS15 Confirm that the Even-odd jitter associated with Duty-Cycle-Distortion falls within the limits
Transmitter AC Common Mode PRBS31 Confirm that the transmitter common mode falls within the limits
Transmitter Eye Diagram PRBS31 Eye mask test
Transmitter Return Loss common and differential PRBS31 Checking the Differential Return loss, SDD11 and SCC11.
28 APRIL 2021 57USB4 Electrical Compliance Testing
Tx Measurements at TP3
Test List Gen2/Gen3 Pattern used Test Objective
Transmitter Total Jitter PRBS15, SQ2 Confirm that the transmitter Total Jitter referenced to 1E-13 statistics falls within the limits after applying
calibrated reference equalizer (CTLE and DFE)
Transmitter UJ PRBS15 Confirm that the transmitter Sum of uncorrelated DJ and RJ components falls within the limits after applying
calibrated reference equalizer (CTLE and DFE). UJ=TJ-DDJ
Transmitter UDJ PRBS15 Confirm that the transmitter Uncorrelated Deterministic Jitter falls within the limits after applying
calibrated reference equalizer (CTLE and DFE)
Transmitter Eye Diagram PRBS31 Eye mask test after applying calibrated reference equalizer (CTLE and DFE)
Hardware Implementation Software Implementation
Embedding a passive simulating a
DUT Test Fxiture Scope
cable reference receiver
? Gen2: 2m passive cable model(s4p)
multiple-gain CTLE
? Gen3: 0.8m passive cable model(s4p)
+ golden CDR
+ 1-tap DFE
Software TP3
Physical TP2
28 APRIL 2021 58What can Tektronix provide for USB4 testing?
? Compliance Tx
? Debug Tx
? Rx Solutions with Anritsu MP1900AInstrumentations for USB4 Compliance Testing
Scope BW ≥ 21 GHz
Tektronix Scope SX Series:
Wilder Technologies USB4 Test
Up to 70 GHz BW
Fixture Kits
Tektronix Scope DX Series:
Anritsu BERT MP1900A:
Up to 33 GHz BW
Up to 64Gbps
28 APRIL 2021 60USB4 Transmitter Test
TP2 and TP3 Testing
? Tektronix automated solution setup details:
? TekExpress USB4: Automated software solution for
USB4 Tx testing
? The TekExpress USB4 software will run on TekScope
? TekExpress will communicate with Wilder Controller to
configure the DUT into correct test state/mode
? Wilder Controller: Side Band (SBTX/RX) communication
with DUT to enter different test modes
? Wilder Fixture: For accessing the signals
? RF Cable: 1m (or less) Phase Matched cable connected
between fixture and scope
? NOTE: USB4 TX tests require RF cable de-embedding
? The reference CDR model for TP2 and TP3 Jitter
and Eye test
nd
? 2 Order PLL response (Type II)
? Damping Factor 0.94
? Natural Frequency 2.2E7 rad/sec
? JTF BW 5MHz
61TekExpress USB4
Automation Solution
28 APRIL 2021 62TekExpress USB4
Uniform and Beatiful Test Report
28 APRIL 2021 63Debug: Go Beyond Compliance
Virtual Probing: SDLA
? Debug and validate the product at multiple test points
? Embed, De-Embed
? IBIS-AMI Model
? Initial reference design support probing but no connector
? How to embed the fixture and compliance channel?
? Compare two or more test points results at the same
time
? Multiple source selection option in Jitter/Eye measurement
28 APRIL 2021 64Debug: Go Beyond Compliance
Transmitter Characterization: DPOJET
? How does the Receiver see the Transmitted signal?
? USB4 Link w/o Re-Timer (or LRD): USB4 Router Host → Passive Cable
→ USB4 Router Device
Speed Test Point Insertion-Loss EH EW CTLE DFE (mV)
(mV ) (UI ) (dB)
pp pp
TP3 7.5+1dB+8dB 230.95 0.771 -3 31.78
Gen3
TP4 7.5+1dB+8dB+6dB 113.79 0.746 -6 27.24
28 APRIL 2021 65Tektronix Overall USB4 Solution
Receiver
Transmitter
Anritsu MP1900
TekExpress USB4
Debug
GRL Rx Automation
DPOJET Plugin
De-embedding + CTLE/DFE
for Debug
SDLA
Complete USB4
Solution Tx + Rx
28 APRIL 2021 66 |
|
