SDR SDRAM Controller Reference Design
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The single data rate (SDR) synchronous dynamic random access memory (SDRAM)controller provides a simplified interface to industry standard SDR SDRAM.The SDR SDRAM Controller is available in either Verilog HDL or VHDL andis optimized for the Altera?APEX?, Stratix?,and Cyclone?device families. The SDR SDRAM Controllersupports the following features:
- Burst lengths of 1, 2, 4, or 8 data words
- CAS latency of 2 or 3 clock cycles
- 16-bit programmable refresh counter used for automatic refresh
- 2-chip selects for SDRAM devices
- Supports the NOP, READA, WRITEA, AUTO_REFRESH, PRECHARGE, ACTIVATE,BURST_STOP, and LOAD_MR commands
- Support for full-page mode operation
- Data mask line for write operations
- PLL to increase system performance
- Support for data-path widths of 16, 32, and 64 bits
Performance
Table 1 shows the performance results for the SDR SDRAM Controller, which weregenerated with the Quartus II software version 2.1 service Pack 1.
| Table 1: Performance |
|
|
|
| Device |
Internal fMAX(MHz) |
tCO/tSU(ns/ns) |
LEs |
| APEX 20KE EP20K60EBC356-1X |
100 |
3.3/1.25 |
219 |
| APEX II EP2A15B724C7 |
133 |
3.3/1.3 |
219 |
| Stratix EP1S10F780C5 |
133 |
1.6/1.5 |
175 |
| Cyclone EP1C6Q240C6 |
133 |
1.6/1.4 |
173 |
|
