第4阶段 修改适合S3C2440的程序
1)、修改include/configs/2440.h
将 #define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */ 改为: #define CONFIG_S3C2440 2)、将/include/common.h中的 #if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_LH7A40X) 改为: #if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_LH7A40X) || defined(CONFIG_S3C2440) 3)、修改/include/s3c24x0.h,将文件中所有的 #ifdef CONFIG_S3C2410 改为: #if defined(CONFIG_S3C2410) || defined (CONFIG_S3C2440) 还有nand 的处理:
/* NAND FLASH (see S3C2410 manual chapter 6) */
typedef struct { S3C24X0_REG32 NFCONF; #if defined(CONFIG_S3C2440) //modified for 2440 S3C24X0_REG32 NFCONT; #endif S3C24X0_REG32 NFCMD; S3C24X0_REG32 NFADDR; S3C24X0_REG32 NFDATA; S3C24X0_REG32 NFSTAT; S3C24X0_REG32 NFECC; } /*__attribute__((__packed__))*/ S3C2410_NAND; 4)、将/cpu/arm920t/s3c24x0/interrupts.c中的 #if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) 修改为: #if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) || defined (CONFIG_S3C2440) 将 #elif defined(CONFIG_S3C2410) 改为: #elif defined(CONFIG_S3C2410) || defined (CONFIG_S3C2440) 5)、将/cpu/arm920t/s3c24x0/serial.c文件中的 #if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) 改为: #if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) || defined (CONFIG_S3C2440) 将 #elif defined(CONFIG_S3C2410) 改为: #elif defined(CONFIG_S3C2410) || defined (CONFIG_S3C2440) 将函数static int serial_init_dev(const int dev_index)中的 uart->UFCON = 0x07; 改为: uart->UFCON = 0x00; 6)、将/cpu/arm920t/s3c24x0/speed.c中的 #if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) 改为: #if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) || defined (CONFIG_S3C2440) 将 #elif defined(CONFIG_S3C2410) 改为: #elif defined(CONFIG_S3C2410) || defined (CONFIG_S3C2440) 在static ulong get_PLLCLK(int pllreg)中的 m = ((r & 0xFF000) >> 12) + 8; p = ((r & 0x003F0) >> 4) + 2; s = r & 0x3; 后面加上: #if defined(CONFIG_S3C2440) if (pllreg == MPLL) return((CONFIG_SYS_CLK_FREQ * m * 2) / (p << s)); else if (pllreg == UPLL) #endif 将 /* return HCLK frequency */ ulong get_HCLK(void) { S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
} 改为: /* return HCLK frequency */ ulong get_HCLK(void) { S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); if (clk_power->CLKDIVN & 0x6)
{ if ((clk_power->CLKDIVN & 0x6)==2) return(get_FCLK()/2); if ((clk_power->CLKDIVN & 0x6)==6) return((clk_power->CAMDIVN & 0x100) ? get_FCLK()/6 : get_FCLK()/3); if ((clk_power->CLKDIVN & 0x6)==4) return((clk_power->CAMDIVN & 0x200) ? get_FCLK()/8 : get_FCLK()/4); return(get_FCLK()); } else return(get_FCLK()); }
7)、/cpu/arm920t/s3c24x0/usb_ohci.c中的 #elif defined(CONFIG_S3C2410) 改为: #elif defined(CONFIG_S3C2410) || defined (CONFIG_S3C2440) 8)、将drivers/rtc/s3c24x0_rtc.c中的 #elif defined(CONFIG_S3C2410) 改为: #elif defined(CONFIG_S3C2410) || defined (CONFIG_S3C2440) 9)、需要在/include/s3c24x0.h文件中添加CAMDIVN定义,将
/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */ /* (see S3C2410 manual chapter 7) */ typedef struct { S3C24X0_REG32 LOCKTIME; S3C24X0_REG32 MPLLCON; S3C24X0_REG32 UPLLCON; S3C24X0_REG32 CLKCON; S3C24X0_REG32 CLKSLOW; S3C24X0_REG32 CLKDIVN; } /*__attribute__((__packed__))*/ S3C24X0_CLOCK_POWER; 改为: /* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */ /* (see S3C2410 manual chapter 7) */ typedef struct { S3C24X0_REG32 LOCKTIME; S3C24X0_REG32 MPLLCON; S3C24X0_REG32 UPLLCON; S3C24X0_REG32 CLKCON; S3C24X0_REG32 CLKSLOW; S3C24X0_REG32 CLKDIVN; #if defined (CONFIG_S3C2440) S3C24X0_REG32 CAMDIVN; #endif } /*__attribute__((__packed__))*/ S3C24X0_CLOCK_POWER; 到这里,make一下,把u-boot.bin烧到nand flash,重新启动,在串口工具上应该可以看到熟悉的
U-Boot 1.3.4 (Oct 9 2009 - 07:34:33)
DRAM: 64 MB NAND:
第5阶段 修改nand和支持网口芯片DM9000等的驱动
#define DEBUGN printf #else #define DEBUGN(x, args ...) {} #endif #if !defined(CFG_NAND_LEGACY) #include <s3c2410.h> #define __REGi(x) (*(volatile unsigned int *)(x)) #if defined(CONFIG_S3C2410) #define NFCONF __REGi(NF_BASE + 0x0) #define NFCMD __REGb(NF_BASE + 0x4) #define NFADDR __REGb(NF_BASE + 0x8) #define NFDATA __REGb(NF_BASE + 0xc) #define NFSTAT __REGb(NF_BASE + 0x10) #define NFECC0 __REGb(NF_BASE + 0x14) #define NFECC1 __REGb(NF_BASE + 0x15) #define NFECC2 __REGb(NF_BASE + 0x16) #define S3C2410_NFCONF_512BYTE (1<<14) #define S3C2410_NFCONF_4STEP (1<<13) #define S3C2410_NFCONF_INITECC (1<<12) #define S3C2410_NFCONF_nFCE (1<<11) #define S3C2410_NFCONF_TACLS(x) ((x)<<8) #define S3C2410_NFCONF_TWRPH0(x) ((x)<<4) #define S3C2410_NFCONF_TWRPH1(x) ((x)<<0) #define NFCONT __REGi(NF_BASE + 0x4) #define NFCMD __REGb(NF_BASE + 0x8) #define NFADDR __REGb(NF_BASE + 0xc) #define NFDATA __REGb(NF_BASE + 0x10) #define NFMECCD0 __REGi(NF_BASE + 0x14) #define NFMECCD1 __REGi(NF_BASE + 0x18) #define NFSECCD __REGi(NF_BASE + 0x1C) #define NFSTAT __REGb(NF_BASE + 0x20) #define NFSTAT0 __REGi(NF_BASE + 0x24) #define NFSTAT1 __REGi(NF_BASE + 0x28) #define NFMECC0 __REGi(NF_BASE + 0x2C) #define NFMECC1 __REGi(NF_BASE + 0x30) #define NFSECC __REGi(NF_BASE + 0x34) #define NFSBLK __REGi(NF_BASE + 0x38) #define NFEBLK __REGi(NF_BASE + 0x3c) #define S3C2440_ADDR_NALE 0x0c #define S3C2440_ADDR_NCLE 0x08 #endif static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd) { struct nand_chip *chip = mtd->priv; switch (cmd) { case NAND_CTL_SETNCE: NFCONF &= ~S3C2410_NFCONF_nFCE; DEBUGN("NFCONF=0x%08x\n", NFCONF); break; case NAND_CTL_CLRNCE: NFCONF |= S3C2410_NFCONF_nFCE; DEBUGN("NFCONF=0x%08x\n", NFCONF); break; case NAND_CTL_SETALE: chip->IO_ADDR_W = NF_BASE + 0x8; DEBUGN("SETALE\n"); break; case NAND_CTL_SETCLE: chip->IO_ADDR_W = NF_BASE + 0x4; DEBUGN("SETCLE\n"); break; default: chip->IO_ADDR_W = NF_BASE + 0xc; break; } #elif defined(CONFIG_S3C2440) switch (cmd) { case NAND_CTL_SETNCE: NFCONF &= ~S3C2440_NFCONT_nCE; DEBUGN("NFCONF=0x%08x\n", NFCONF); break; case NAND_CTL_CLRNCE: NFCONF |= S3C2440_NFCONT_nCE; DEBUGN("NFCONF=0x%08x\n", NFCONF); break; case NAND_CTL_SETALE: chip->IO_ADDR_W = NF_BASE + S3C2440_ADDR_NALE; DEBUGN("SETALE\n"); break; case NAND_CTL_SETCLE: chip->IO_ADDR_W = NF_BASE + S3C2440_ADDR_NCLE; DEBUGN("SETCLE\n"); break; default: chip->IO_ADDR_W = NF_BASE + 0x10; //注意是0x10 break; } #endif return; } { DEBUGN("dev_ready\n"); return (NFSTAT & 0x01); } void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) { DEBUGN("s3c2410_nand_enable_hwecc(%p, %d)\n", mtd ,mode); NFCONF |= S3C2410_NFCONF_INITECC; } u_char *ecc_code) { ecc_code[0] = NFECC0; ecc_code[1] = NFECC1; ecc_code[2] = NFECC2; DEBUGN("s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n", mtd , ecc_code[0], ecc_code[1], ecc_code[2]); } u_char *read_ecc, u_char *calc_ecc) { if (read_ecc[0] == calc_ecc[0] && read_ecc[1] == calc_ecc[1] && read_ecc[2] == calc_ecc[2]) return 0; return -1; } #endif { u_int32_t cfg; u_int8_t tacls, twrph0, twrph1; S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); /* initialize hardware */ twrph0 = 3; twrph1 = 0; tacls = 0; cfg |= S3C2410_NFCONF_TACLS(tacls - 1); cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); nand->IO_ADDR_R = nand->IO_ADDR_W = 0x4e00000c; /* read_byte and write_byte are default */ nand->hwcontrol = s3c2410_hwcontrol; nand->enable_hwecc = s3c2410_nand_enable_hwecc; nand->calculate_ecc = s3c2410_nand_calculate_ecc; nand->correct_data = s3c2410_nand_correct_data; nand->eccmode = NAND_ECC_HW3_512; #else //nand->eccmode = NAND_ECC_SOFT; #endif nand->options = NAND_USE_FLASH_BBT; #else nand->options = 0; #endif twrph0 = 6; twrph1 = 2; tacls = 0; cfg = (tacls<<12)|(twrph0<<8)|(twrph1<<4); NFCONF = cfg; cfg = (1<<6)|(1<<4)|(0<<1)|(1<<0); NFCONT = cfg; nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)0x4e000010; /* read_byte and write_byte are default */ nand->hwcontrol = s3c2410_hwcontrol; nand->dev_ready = s3c2410_dev_ready; #ifdef CONFIG_S3C2440_NAND_HWECC nand->enable_hwecc = s3c2410_nand_enable_hwecc; nand->calculate_ecc = s3c2410_nand_calculate_ecc; nand->correct_data = s3c2410_nand_correct_data; nand->eccmode = NAND_ECC_HW3_512; #else // nand->eccmode = NAND_ECC_SOFT; nand->options = NAND_USE_FLASH_BBT; #else nand->options = 0; #endif } #error "U-Boot legacy NAND support not available for S3C2410" #endif #endif #define CFG_ENV_OFFSET 0X40000 /* u-boot:0x00000--0x40000,param:0x40000--0x60000,kernel:0x60000--0x260000 128K block*/ #define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ //#define CONFIG_SETUP_MEMORY_TAGS 1 //#define CONFIG_CMDLINE_TAG 1 #if defined(CONFIG_CMD_NAND) #define CFG_MAX_NAND_DEVICE 1 //just one nand flash chip on board #define CFG_NAND_BASE 0x4e000000 //nand flash base address /* one page size*/ #define NAND_SECTOR_SIZE SECTORSIZE #define NAND_BLOCK_MASK (SECTORSIZE - 1) * Nandflash Boot */ #define CONFIG_S3C2440_NAND_BOOT 1 #endif * Hardware drivers */ //#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ //#define CS8900_BASE 0x19000300 //#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ #define CONFIG_DRIVER_DM9000 1 #define CONFIG_DM9000_BASE 0x20000300 #define DM9000_IO CONFIG_DM9000_BASE #define DM9000_DATA (CONFIG_DM9000_BASE+4) #define CONFIG_DM9000_USE_16BIT #define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200n81" #define CONFIG_ETHADDR 08:00:3e:26:0a:5b #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_IPADDR 192.168.1.250 #define CONFIG_SERVERIP 192.168.1.100 #define CONFIG_BOOTFILE "zImage.img" /*#define CONFIG_BOOTCOMMAND "tftp; bootm"*/ #define CONFIG_BOOTCOMMAND "tftp 0x30008000 zImage.img\; bootm 30008000" #================================================= |
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