verilog 及Xilinx_FPGA入门（二）

三种状态机：

状态机（一）： 直接型，跳转快，省资源。

reg[5:0] state=6'b000001;

always@(posedge clk)
begin

case(state)
6'b000001:begin
                .......

                 state<=6'b000010;

               end

6'b00010:begin
                .......

 

                 state<=6'b000100;

                end

......

endcase

 

end

 

状态机（二）： buf型，缓冲一级。

reg[5:0] state=6'b000001;

reg[5:0] next_state=6'b000001;

always@(posedge clk)
begin

case(state)
6'b000001:begin
                .......

                 next_state<=6'b000010;

               end

6'b00010:begin
                .......

 

                 next_state<=6'b000100;

                end

......

endcase

 

end

always@(posedge clk)

begin
state<=next_state;

end

状态机（三）：设置控制信号，该缓冲时缓冲，该直接时直接，且省资源

reg[5:0] state=6'b000001;

reg jump=0;

always@(posedge clk)
begin

case(state)
6'b000001:begin
                .......

                jump<=1;
                 if(jump==1)

                 state<=6'b000010;
                

               end

 

6'b00010:begin
                .......

                jump<=0;

                 state<=6'b000100;

                end

......

endcase

 

end