(1)quartus II的各种警告

1.Verilog HDL information at xxx.v:always construct contains both blocking and non-blocking assignments
在一个always块中同时使用了阻塞和非阻塞赋值。

2.Warning: Parallel compilation is not licensed and has been disabled
并行编译未获得许可，已经终止。

3.Warning (10227): Verilog HDL Port Declaration warning at v_led.v(4): data type declaration for "out" declares packed dimensions but the port declaration declaration does not
应该在声明引脚输入输出时就写明位宽，否在之后声明就会出现以上错误。如output out；reg[7:0] out；就会报警告，应该写成output reg[7:0] out;才正确。

4.Warning (10230): Verilog HDL assignment warning at v_led.v(13): truncated value with size 32 to match size of target (8)
原因:在HDL设计中对目标的位数进行了设定,如:reg[4:0] a;而默认为32位,将位数裁定到合适的大小
措施:如果结果正确,无须加以修正,如果不想看到这个警告,可以改变设定的位数

5.Warning: Found 9 output pins without output pin load capacitance assignment
 输出引脚没用输出引脚负载电容。

6.Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
警告：保留所有未使用引脚的设置还没有被指定，并且将默认“作为驱动输出的‘地’”。

7.Warning: Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER
警告：跳过模块“PowerPlay功耗分析仪”，由于分配FLOW_ENABLE_POWER_ANALYZER

8.Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
这个是比较诡异的警告，在网上搜了半天，没有确切的解决办法，这个信息大致的意思是未定义管脚设置接地，其实无关紧要，但是放在那不管很影响我的0warning记录，于是在setting里面找，后来发现在device里有个对话框device and pin options，打开后里面有个unused pins，把里面的选项由原来的接地改成三态，再仿真警告就没了，但奇怪的是，后来我又改了回来，再仿真，警告还是没有出现，不知何故。

9.Warning: Expected ENABLE_CLOCK_LATENCY to be set to ON but is set to OFF
这个是说时钟延迟的一个设置应该设置为ON，网上都说没什么影响，貌似与时序仿真有关，不太清楚，设置在Classic Timing Analyzer中有个more setting，里面下拉菜单中就有ENABLE_CLOCK_LATENCY，设置为ON就OK。
PS：问题

How do I run the PowerPlay Power Analyzer automatically during compilation?
解决方案

In the Quartus? II software, you can enable the PowerPlay Power Analyzer to run automatically during compilation by adding the following assignment to your Quartus II Settings File (.qsf):

set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
This assignment is scheduled to be available in the Settings dialog box in a future release of the Quartus II software.

10.在Nios II中编译时有如下提示warning: no newline at end of file
在最后的一个大括号外再加一个回车。