module bcd_water( clk , rst_n , din , din_vld , dout , dout_vld ); input clk ; input rst_n ; input [ 7:0] din ; input din_vld ; output [11:0] dout ; wire [11:0] dout ; output dout_vld ; wire dout_vld ; reg [19:0] din_temp ; reg [19:0] din_temp_ff0 ; reg [19:0] din_temp_ff1 ; reg [19:0] din_temp_ff2 ; reg [19:0] din_temp_ff3 ; reg [19:0] din_temp_ff4 ; wire [20:0] din_shift_temp ; wire [20:0] din_shift_temp_ff0 ; wire [20:0] din_shift_temp_ff1 ; wire [20:0] din_shift_temp_ff2 ; wire [20:0] din_shift_temp_ff3 ; wire [ 7:0] din_a_temp ; wire [ 3:0] din_b_temp ; wire [ 3:0] din_c_temp ; wire [ 3:0] din_d_temp ; wire [ 7:0] din_add_a_temp ; wire [ 3:0] din_add_b_temp ; wire [ 3:0] din_add_c_temp ; wire [ 3:0] din_add_d_temp ; wire [ 7:0] din_a_temp_ff0 ; wire [ 3:0] din_b_temp_ff0 ; wire [ 3:0] din_c_temp_ff0 ; wire [ 3:0] din_d_temp_ff0 ; wire [ 7:0] din_a_temp_ff1 ; wire [ 3:0] din_b_temp_ff1 ; wire [ 3:0] din_c_temp_ff1 ; wire [ 3:0] din_d_temp_ff1 ; wire [ 7:0] din_a_temp_ff2 ; wire [ 3:0] din_b_temp_ff2 ; wire [ 3:0] din_c_temp_ff2 ; wire [ 3:0] din_d_temp_ff2 ; wire [ 7:0] din_a_temp_ff3 ; wire [ 3:0] din_b_temp_ff3 ; wire [ 3:0] din_c_temp_ff3 ; wire [ 3:0] din_d_temp_ff3 ; wire [ 7:0] din_add_a_temp_ff0 ; wire [ 3:0] din_add_b_temp_ff0 ; wire [ 3:0] din_add_c_temp_ff0 ; wire [ 3:0] din_add_d_temp_ff0 ; wire [ 7:0] din_add_a_temp_ff1 ; wire [ 3:0] din_add_b_temp_ff1 ; wire [ 3:0] din_add_c_temp_ff1 ; wire [ 3:0] din_add_d_temp_ff1 ; wire [ 7:0] din_add_a_temp_ff2 ; wire [ 3:0] din_add_b_temp_ff2 ; wire [ 3:0] din_add_c_temp_ff2 ; wire [ 3:0] din_add_d_temp_ff2 ; wire [ 7:0] din_add_a_temp_ff3 ; wire [ 3:0] din_add_b_temp_ff3 ; wire [ 3:0] din_add_c_temp_ff3 ; wire [ 3:0] din_add_d_temp_ff3 ; reg dout_vld_temp ; reg dout_vld_temp_ff0 ; reg dout_vld_temp_ff1 ; reg dout_vld_temp_ff2 ; reg dout_vld_temp_ff3 ; reg dout_vld_temp_ff4 ; always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin din_temp <= 20'b0; end else if(din_vld)begin din_temp <= {9'b0,din,3'b0}; end end always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin dout_vld_temp <= 1'b0; end else if(din_vld)begin dout_vld_temp <= 1'b1; end else begin dout_vld_temp <= 1'b0; end end assigndin_a_temp = din_temp[7: 0] ; assign din_b_temp = din_temp[11: 8] ; assign din_c_temp = din_temp[15:12] ; assign din_d_temp = din_temp[19:16; assign din_add_a_temp = din_a_temp ; assign din_add_b_temp = din_b_temp + ((din_b_temp>=5)?4'd3:4'd0) ; assign din_add_c_temp = din_c_temp + ((din_c_temp>=5)?4'd3:4'd0) ; assign din_add_d_temp = din_d_temp + ((din_d_temp>=5)?4'd3:4'd0) ; assign din_shift_temp = {din_add_d_temp,din_add_c_temp, din_add_b_temp,din_add_a_temp,1'b0} ; always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin din_temp_ff0 <= 20'b0; end else begin din_temp_ff0 <= din_shift_temp[19:0]; end end always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin dout_vld_temp_ff0 <= 1'b0 ; end else begin dout_vld_temp_ff0 <= dout_vld_temp; end end assign din_a_temp_ff0 = din_temp_ff0[ 7: 0] ; assign din_b_temp_ff0 = din_temp_ff0[11: 8] ; assign din_c_temp_ff0 = din_temp_ff0[15:12] ; assign din_d_temp_ff0 = din_temp_ff0[19:16]; assign din_add_a_temp_ff0 = din_a_temp_ff0 ; assign din_add_b_temp_ff0 = din_b_temp_ff0 + ((din_b_temp_ff0>=5)?4'd3:4'd0) ; assign din_add_c_temp_ff0 = din_c_temp_ff0 + ((din_c_temp_ff0>=5)?4'd3:4'd0) ; assign din_add_d_temp_ff0 = din_d_temp_ff0 + ((din_d_temp_ff0>=5)?4'd3:4'd0); assign din_shift_temp_ff0 = {din_add_d_temp_ff0,din_add_c_temp_ff0, din_add_b_temp_ff0,din_add_a_temp_ff0,1'b0}; always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin din_temp_ff1 <= 20'b0; end else begin din_temp_ff1 <= din_shift_temp_ff0[19:0]; end end always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin dout_vld_temp_ff1 <= 1'b0; end else begin dout_vld_temp_ff1 <= dout_vld_temp_ff0; end end assign din_a_temp_ff1 = din_temp_ff1[ 7: 0] ; assign din_b_temp_ff1 = din_temp_ff1[11: 8] ; assign din_c_temp_ff1 = din_temp_ff1[15:12] ; assign din_d_temp_ff1 = din_temp_ff1[19:16] ; assign din_add_a_temp_ff1 = din_a_temp_ff1 ; assign din_add_b_temp_ff1 = din_b_temp_ff1 + ((din_b_temp_ff1>=5)?4'd3:4'd0) ; assign din_add_c_temp_ff1 = din_c_temp_ff1 + ((din_c_temp_ff1>=5)?4'd3:4'd0); assign din_add_d_temp_ff1 = din_d_temp_ff1 + ((din_d_temp_ff1>=5)?4'd3:4'd0); assign din_shift_temp_ff1 ={din_add_d_temp_ff1,din_add_c_temp_ff1, din_add_b_temp_ff1,din_add_a_temp_ff1,1'b0}; always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin din_temp_ff2 <= 20'b0; end else begin din_temp_ff2 <= din_shift_temp_ff1[19:0]; end end always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin dout_vld_temp_ff2 <= 1'b0; end else begin dout_vld_temp_ff2 <= dout_vld_temp_ff1; end end assign din_a_temp_ff2 = din_temp_ff2[ 7: 0]; assign din_b_temp_ff2 = din_temp_ff2[11: 8] ; assign din_c_temp_ff2 = din_temp_ff2[15:12] ; assign din_d_temp_ff2 = din_temp_ff2[19:16] ; assign din_add_a_temp_ff2 = din_a_temp_ff2 ; assign din_add_b_temp_ff2 = din_b_temp_ff2 + ((din_b_temp_ff2>=5)?4'd3:4'd0); assign din_add_c_temp_ff2 = din_c_temp_ff2 + ((din_c_temp_ff2>=5)?4'd3:4'd0); assign din_add_d_temp_ff2 = din_d_temp_ff2 + ((din_d_temp_ff2>=5)?4'd3:4'd0); assign din_shift_temp_ff2 ={din_add_d_temp_ff2,din_add_c_temp_ff2, din_add_b_temp_ff2,din_add_a_temp_ff2,1'b0}; always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin din_temp_ff3 <= 20'b0; end else begin din_temp_ff3 <= din_shift_temp_ff2[19:0]; end end always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin dout_vld_temp_ff3 <= 1'b0; end else begin dout_vld_temp_ff3 <= dout_vld_temp_ff2; end end assign din_a_temp_ff3 = din_temp_ff3[ 7: 0] ; assign din_b_temp_ff3 = din_temp_ff3[11: 8] ; assign din_c_temp_ff3 = din_temp_ff3[15:12] ; assign din_d_temp_ff3 = din_temp_ff3[19:16] ; assign din_add_a_temp_ff3 = din_a_temp_ff3 ; assign din_add_b_temp_ff3 = din_b_temp_ff3 + ((din_b_temp_ff3>=5)?4'd3:4'd0); assign din_add_c_temp_ff3 = din_c_temp_ff3 + ((din_c_temp_ff3>=5)?4'd3:4'd0); assign din_add_d_temp_ff3 = din_d_temp_ff3 + ((din_d_temp_ff3>=5)?4'd3:4'd0); assign din_shift_temp_ff3 ={din_add_d_temp_ff3,din_add_c_temp_ff3, din_add_b_temp_ff3,din_add_a_temp_ff3,1'b0}; always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin din_temp_ff4 <= 20'b0; end else begin din_temp_ff4 <= din_shift_temp_ff3[19:0]; end end always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin dout_vld_temp_ff4 <= 1'b0; end else begin dout_vld_temp_ff4 <= dout_vld_temp_ff3; end end assign dout = din_temp_ff4[19:8]; assign dout_vld = dout_vld_temp_ff4 ; endmodule |