RDL and Flip-Chip Design

Abstract—This paper mainly outlines RDL and Flip-Chip design method in one project. RDL is abbreviation for Redistribution Layer, involves making a layer on the chip active side, for the chip pins redistribution. Flip-Chip is a new type of micro-assembly technology for IC dies.

RDL can rearrange chip pins to any reasonable position on the chip. Use RDL technology, die Pad located in the chip peripheral to support traditional Wire Bond technology can be reassigned to the whole surface RDL Pin of the IC die.

This paper presents the Bare Die Cell and Die pad creation, RDL Cell and RDL Pin creation, and then describes the optimization of net connections, RDL layout and Flip-Chip layout in detail, as well as the relationship of the two layouts.

Index Terms— RDL, Flip-Chip, Die Cell, RDL Cell, net optimization, BGA Cell.

  I     Introduction

Today, Flip-Chip isbecoming a widely used packaging technology. The requirement of such technologyincreases, puts forward a series of new severe challenges to design andproduction, designers need to face these challenges and solve the relatedproblems, provide reliable support of design, assembly, testing and the wholeprocess for this complex technology.

In traditional packaging technology, chip activeface is upward, back side is stuck to the substrate, and then through WireBonding or TAB technology for electrical interconnection. While Flip-Chipactive face is downward to substrate, through solder bumps array to realize thechip and the substrate interconnection, chip or die directly connect to packageor SiP substrate.

On one hand, Flip-Chip greatly shortens the lengthof the signal interconnection, reduces the delay, and effectively improves theperformance that is important for high-speed design. On the other hand, becauseof the using of planar array connection, Flip-Chip interconnection can providehigher I/O density. At the same time, Flip-Chip occupies very small area,almost is consistent with the chip size. Comparing with Wire Bond and TAB, Flip-Chipcan achieve the smallest, the thinnest encapsulation.

Flip-Chip has distinct advantages. ① Flip-Chip pin length is short,with minimal parasitic parameters. ② Flip-Chip pins are connected by array, greatly improve theperformance, and reduce the packaging area. ③ Flip-Chip can support more pin numbers, meet the I/O number growingdemand.

If the IC chip is not specially designed for Flip-Chip,it needs SiP or Package designer to design and process RDL layer.

RDL can rearrange chip pins toany reasonable position on the chip. Use RDL technology, Die Pad located in thechip peripheral to support traditional Wire Bond technology can be reassignedto the whole surface “Redistribution Pin” of the chip, hereinafter referred to as RDL Pin.

Please see Fig. 1. The relationship of Die padsand RDL pin. The figure above is the top view of the die pad and RDL Pin, the figurebelow is the side view of the two. Usually, RDL use single layer aluminum,single layer copper or multi-layer copper. For most of the RDL design, we canchoose single layer, as shown in Fig. 1.

Fig. 1. The relationship of Die pad and RDL pin

Through such redistribution, the location of thepin changed, designer can be more flexible to consider the chip placement in thewhole SiP design.

The advantage of RDL also is embodied in the cost control of IC, thechip lifecycle can be extension through RDL technology. Instead of expensive ICchip re-design, RDL is usually available to minimize the cost of IC overhead.

 II   Die cell and RDL cell creation

Through a practical project, we introduce thedesign method of RDL and Flip-Chip in the design environment.

Here, we use Mentor Xpedition Enterprise design environment,in it, Bare Die, RDL, Flip-Chip and the BGA Package all need to createcorresponding Cell.

Look at the whole package structure, Bare Die Celland RDL Cell are placed on the top of the substrate, BGA Cell is placed on thebottom side of the substrate, signal path flow from Die Pad →RDL layer trace →RDL Pin →package substrate trace →BGA Pad, as shown in Fig. 2 below.

The Fig. 2 above is 3D view of the three cells,the Fig. 2 below is the side view and the signal path.

Fig. 2. Die cell, RDL cell and BGA Cell 

First, we need to define the RDL Pin size, it is based on the number of Die Pad, Bare Die chip area and the technic process ability of manufacture. Here, we use 150 um square Pad as RDL Pin.

For Bare Die itself, it also need to create a SMD type Pad. Here, we create 62um square Pad for the Die Pad.

After RDL Pin and Die Pad created, we can create the Die Cell and RDL Cell, as shown in Fig. 3.

Here to note that the Bare Die Underside space should be bigger than RDL Cell Height, here we set 30um for Bare Die Cell Underside space and 20um for RDL Cell Height, so that Bare Die Cell and RDL Cell can be placed in the same position, and no DRC conflict.

Fig. 3. Bare Die cell and RDL Cell

 III   RDL layout

In layout designenvironment, the first thing we should do is to setup the RDL layer stackup, becausethe RDL design only need one layer in this case, so we set one signal layer in thelayer stackup setting.

The thicknessand the parameters of signal layer and dielectric layer can be adjustedaccording to actual condition, normally, the setting here have no impact onproduction and processing, but will affect the transmission line impedancecalculation, and will also affect the result of subsequent software simulation.

Then, carry onthe device layout, Bare Die Cell and RDL Cell are both placed on the top layer.in the Cell creation process, we have set Bare Die Cell Underside space value(30um) greater than the RDL Cell Height value (20um), so we can place them inthe same position, even if the two cells overlap together, there will be noconflict, as shown in Fig. 4. 

Fig. 4. Bare Die cell and RDL Cell placement

A.   Net optimization

After the cell placement, we need to assign thenets connection, for time saving, we can assign the connection randomly at first,and then use the net optimization to adjust the connection.

Because we did not consider the position of thepins in layout, so the net connections were crossed so much, as shown in Fig. 5,it is now necessary to optimize the net connections.

Fig. 5. Net connections before optimization

Nets optimization in reality is to swap the RDL Pins. All the  RDL pins can be set swappable.

Fig. 6. Swap RDL pins to optimize net connection

We can use automatic optimization and  manual optimization.

According to the size and the pin numbers of the chip, the time of automatic optimization will be different. Usually a few minutes later, the automatic optimization will be complete.

Normally, after automatic optimization, the net connections become more smoothly, but it is difficult to achieve the perfection, it need designer to do manual optimization according to the actual design situation.

Comparing the results of automatic optimization and manual optimization, it can be seen that, after the completion of automatic optimization, the net connections have had very big improvement comparing with initial connections, but there are still some nets cross. Using both automatic optimization and manual optimization by pin swap, optimal net connections can be achieved, please see Fig. 7.

Fig. 7. The results of auto swap and manual swap

B.   RDL layout.

After the completion of net optimization, setthe routing rules, including RDL layer line width and clearance. Here, we setthe line width 15um, the clearance 20um.

 Then wecan start routing automatically or manually, the effect of manual routingusually can get better and more reasonable result.

Either in manual or automatic routing, the 45° routingfunction can be opened or closed.

By toggling Allow 45° corners Options to realizedifferent routing result.

After setup, routing automatically or manually,we can get the following two results of two different routing options, as shownin Fig. 8.

Fig. 8. The results of the two routing options

From Fig. 9, we can see the Die pads and RDL Pins were connected by the RDL trace.

Fig. 9. RDL traces connect Die pads to RDL pins

After routing, we need do DRC check, AfterDRC check, we can output the files for RDL production processing. According theRDL manufactures demand, the production data format can be GDSII, DXF, Gerber,ODB , Neutral File, and etc.

 IV  Flip-Chip Layout

After thecompletion of RDL design, we can toggle to Flip-Chip design.

In RDLdesign, Bare Die pads have been lead to RDL Cell pins, in Flip-Chip design, weneed to lead RDL Cell pins to BGA Cell pins.

Here, Flip-Chip and the BGA Package both need tocreate corresponding Cell. Flip-Chip Cell is the RDL Cell flip, so its size and pin position arethe same with RDL Cell, while its pin definition is the mirror of RDL Cell.

We need tocreate a new layout inside the same project. In the new layout, the first thingis to do the layer stackup and via settings, here we set Flip-Chip substrate to4 layers, with layer stackup 1 2 1, it means 1 buildup layer 2 laminatelayers 1 buildup layer. As shown in Fig. 10.

Then, weset 150um via for buildup layer and 250um via for laminate layers.

Generally,in High Density Interconnection design, we use Laminate process and Buildupprocess together. Laminate process is suitable for the internal layers whichcan strengthen the substrate, while buildup process is suitable for the surfacelayer which can support higher density routing.

Fig. 10.  The layer stackup and via setting for Flip-Chip substrate

After the layer stackup and viasetting, adjust the board size the same with BGA Cell size, and change theBoard Origin to the center of substrate, and then to place parts. Because thereare only two parts, it is very simple, place the Flip-Chip cell at the top ofsubstrate, BGA cell to the bottom side of the substrate, the origin of bothcell set to (0, 0). After the completion of placement, the result is shown in Fig.11.

Fig. 11. Flip-Chip Cell and BGA Package Cell placement

After placement, we need to set up therelated design rules, such as physical rules: line width, clearance and electricalrules: delay, differential nets etc.

Before routing, we also need do net optimization, the method is thesame as RDL layout optimization: using auto-swap and manual swap.

Sets all the Pins of BGA swappable. Please note at this time the Flip-Chippins need to be non-swappable. Then, start pins automatic optimization.

According to the pin numbers and the computer performance, the timeof net auto optimization would be different. After the completion of autooptimization, the net connection will be smoother, but it is also difficult toachieve perfection, the crossover remainders need manual optimization accordingto the actual design situation.

As shown in Fig. 12. Thecomparison of before and after auto optimization. It can be seen that most ofthe crossover have been optimized, but there is still room for improvement.

Fig. 12. The effect of auto optimization 

If autooptimization result is not satisfied, use manual optimization, designer canswap BGA pins according to the local net connections and manual routingstrategies. About the detailed method of swapping pins, please refer RDL designcontent of this paper.

To begin routingafter completion of net optimization, we can choose automatic routing or manualrouting, usually the manual routing result will be better and more reasonable.Both in manual and automatic routing, we can open or close 45° routing option,the operation method is the same as RDL design. In this case, we use automaticrouting with 45° routing allowed.

According to thecomplexity of the design, auto routing time will be different. In the processof the auto routing, the information of open net numbers, routing percentageand use of via will be updated in real time by Xpedition software.

Fig. 13. 2D and 3D view of the Flip-Chip Substrate after routing

After the completion of the auto  routing, the percentage of  routing,  routed nets and the via numbers are no longerupdated, if there is no 100% complete  routing, indicates the net connection alsoneed to be further optimized.

After furtheroptimization, rerouting the design, if still can’t finish 100%, it needs to bedone by manual routing, until the completion rate reachs 100%.

Here, the Flip-Chipdesign has almost completed. Subsequent DRC check is needed, as well as theoutput of production file.

The same with RDL design, we can output GDSII, DXF, Gerber, ODB , Neutral File, and etc. data format tosupport different kinds of manufacture processes.

 V   From Bare Die to PCB board

Because BGA package will be applied to PCB design, or placed on PCBtesting board finally. In the same project, we create a new PCB Board and placethe BGA Package cell to the PCB Board, then add related testing circuit tofinish the testing PCB board design, as shown in Fig 14.

Fig. 14. Add testing PCB_board in the same project

In the end, let’s seethe whole system structure of the Flip-Chip design application.

The signal path flowfrom the Die Pad→RDL layer trace→RDLPin→Package substrate trace→BGA Pad→PCBboard, as shown in Fig. 15.

Fig. 15. Diagramfor IC bare Die→RDL→BGA Package→PCB board

 VI   Conclusion

From the above design process and results, wecan get the following conclusions: For 3D SiP, it is feasible to design two orthree or more substrate layouts in one project.

For RDL and Flip-Chipdesign, generally we need to create Bare Die Cell, RDL Cell, Flip-ChipCell and BGA package Cell, here the Flip-Chip Cell size is the same with RDLCell, and its pin definition is the mirror of RDL Cell.

First, through RDL layout, we can transform bondwire bare die to Flip-Chip die with one layer layout data.

Then, we placethe Flip-Chip Cell to package substrate, we create another layout data, transmitthe signal from Flip-Chip cell to BGA cell.

Finally, weplace the BGA package to PCB, the signals were transmitted to other deviceswith the connection traces in PCB board.

With multi-layoutin one project, we can adjust the mapping of each cell consistently,

For example,if the signal definition in RDL pin changed, it also influence the Flip-Chippin definition and thus influence the BGA package pin definition.  

This kind ofdesign method also is suitable for PoP (Package on Package) design, TSV (ThoroughSilicon Via) interposer design and the design with multiple PCB boards sharingone baseboard.

 About the Author

Suny Li (Li Yang) is a SiP/PCB Technical Specialist in China; he now works in AcconSys Technology Co. Ltd, (a Mentor Authorized Distributor for China). Suny has guided and consulted on dozens of key SiP projects in China, accumulating plentiful experience in SiP design and simulation.

Based on these projects Suny has published technical book “SiP System-in-package design and simulation Mentor Expedition Enterprise Flow advanced design guide” PHEI 2012, China.

This book had gotten very good feedbacks in china, it was selected to the Export Authorization Scheme to USA and British, and translated to English version. WILEY (John Wiley & Sons Inc.) select it in many recommended technical books.

Suny spent about two year’s spare time to rewrite the book in English, and also updated some contents of it. This book has been published by WILEY in July 2017.

It covers an array of issues of vital concern for SiP design and fabrication electronics engineers, as well as SiP users, including:  Cavity and stacked dies design, Flip-Chip and RDL design, Embedded Passive, RF design, Concurrent design, Routing and coppering, 3D Real-Time DRC check, SiP simulation technology, Mentor SiP Design and Simulation Platform and etc.

Suny is a senior member of the Chinese Institute of Electronics (CIE), a senior member of the China Graphic Society (CGS) and a member of the IEEE.

Suny graduated from Beijing University of Aeronautics & Astronautics (BUAA) in 2000, receiving Master's and Bachelor's degrees in Science and Technology of Aeronautics & Astronautics.