from CAST, Inc.Features
Block DiagramFigure 1 shows the block diagram for the nflashctrl NAND Flash Memory Controller DescriptionThe NFlashCtrl megafunction implements a flexible controller for NAND flash memory. The full-featured megafunction manages the read/write interactions between a master host system and up to eight NAND Flash memory units. It uses the standard AMBA AHB for easy integration with these systems (other standard interfaces are also available). Configurable features and internal configuration registers make it easy to model timing and adapt the megafunction for efficient operation with a variety memory device types. An internal ECC calculator helps detect errors, and a power-save mode makes the NFlashCtrl megafunction suitable for low-power applications. The megafunction has been rigorously verified and provides competitive speed and area results, for example, with a 0.18μ ASIC process it uses just 5,817 gates and runs at 333 MHz. The NFlashCtrl megafunction is developed for reuse in ASICs and FPGAs. It is fully synchronous with positive-edge clocking, has no internal three-state buses, and uses a synchronous re-set, so scan insertion is straightforward. The included verification package features bus models for the AHB master and NAND flash devices to help designers verify the functioning and compliance of the megafunction. Device Utilization ExampleTable 1 lists the typical device utilization results for the megafunction.
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