4选1多路选择器(case-when实现):
LIBRARY IEEE;
USE IEEE.STD_LOGICD_1164.ALL;
ENTITY chooes IS
PORT( S1,S0: IN STD_LOGIC;
a,b,c,d: IN STD_LOGIC);
Z: OUT STD_LOGIC
);
END chooes;
ARCHITECTURE art1 OF chooes IS
SIGNAL s: STD_LOGICVECTOR(1 DOWNTO 0);
BEGIN
PROCESS(S1,S0,a,b,c,d)
BEGIN
s<=S1 & S0;
CASE S IS
WHEN "00" => Z<=a;
WHEN "01" => Z<=b;
WHEN "10" => Z<=c;
WHEN "11" => Z<=d;
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
END art1; |
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来自: BUPT-BYR > 《VHDL简单例子》