testbench顾名思义就是一个测试台,它对外没有接口,所以实体部分为空,但它要对要测试的器件提供激励信号,这其实就是最简单的testbench,以下是具体的操作步骤: 1.首先基于QuartusII建立的一个新的工程,编译通过,这其实就是我们要测试的源文件DUT(design under test)counter.vhd. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port(clk: in std_logic; reset: in std_logic; en: in std_logic; q: out std_logic_vector(3 downto 0)); end counter; architecture behave of counter is signal q_n: std_logic_vector(3 downto 0); begin process(clk, reset, en, q_n) begin if (reset = '1') then q_n <= (others => '0');--?????? elsif rising_edge(clk) then if en = '1' then q_n <= q_n + 1; end if; end if; end process; q <= q_n; end behave; 2.打开ModelSim,指定路径为Quartus工程所在目录;建立新的仿真工程,添加文件(DUT)。 3.编译DUT文件到仿真库中(右键DUT,选择compile). 4.写testbench文件(counter_tb.vhd)。首先选择view-source-show language templates,然后选择file-new-source-vhdl,双击creat testbench,选择Design Unit Name为DUT文件,点击finish,模板创建完成,然后右键取消read only ,自己添加测试信号。 LIBRARY ieee ; USE ieee.std_logic_unsigned.all ; USE ieee.std_logic_1164.all ; ENTITY counter_tb IS constant ClockPeriod: time := 40 ns; END ;
ARCHITECTURE counter_tb_arch OF counter_tb IS component counter is port(clk: in std_logic; reset: in std_logic; en: in std_logic; q: out std_logic_vector(3 downto 0)); end component counter;
signal clock, rst, en: std_logic; signal q: std_logic_vector(3 downto 0); begin CounterInstance: counter port map(clock, rst, en, q);
simProcess: process begin rst <= '1'; wait for 50 ns; rst <= '0' ; wait for 1000 ns; rst <= '0' ; end process simprocess;
en <= '0' after 0 ns, '1' after 50 ns, '0' after 850 ns, '1' after 900 ns;
ClockProcess: process(clock, rst) begin if (rst = '1') then clock <= '0'; else clock <= not clock after ClockPeriod; end if; end process ClockProcess; END ; 5.同样把testbench文件编译到仿真库中。 6.点击simulate-start simulation,选中design标签work库下testbench文件,点击ok。 7.workspace窗口出现sim标签,右键testbench文件,选择add to wave ,然后点击开始仿真按钮即可。
|