|
Flow: ◆ Pre-Study and Market Analyze ◆ ASIC Function Specification ◆ Top-Level Architecture Design ◆ Identify needed IP and Select team members ◆ Estimate Silicon area,pin-out,cost and power ◆ Module Detail Specification ◆ Module Implementation, RTL Code and Initial trial synthesis ◆ Subsystem Simulation with Feature lists ◆ Familiar with Simulation Environment and write Testcase ◆ System Simulation and Top-Level Logic Synthesis ◆ Pre-STA and Pre-netlist Simulation ◆ RTL To Pre-netlist Formality ◆ Code coverage analyze ◆ Final Pre-netlist delivered ◆ Layout and Backend ◆ Device pin lists and Package ◆ DFT and ATPG ◆ Layout Floorplan,Place and Route ◆ Preparation for Testing of the Silicon ◆ Pre-netlist To Post-netlist Formality ◆ Post-nelist simulation and statice timing analyze ◆ Test vectors (IDDQ,scan and functional) prepare ◆ ASIC Sign-Off ◆ Tape-out and manufacture ◆ Testing of the Sample Silicon |
|
|
