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By John H. Lau [ASM PacificTechnology Ltd.] Redistribution layers (RDLs) [1-2] are the most integral part of wafer-level packaging (WLP). In this study, various methods for the fabrication of RDLs for fan-out wafer/panel-level packaging(FOW/ PLP) are presented. Emphasis is placed on four different methods in making the RDLs for FOWLP, and the other four for FOPLP. Some recommendations are also provided. Finally, the critical issues of panel-level technology are presented. FOWLP RDL methods As noted in the introduction, there are four methods for making RDLs used in FOWLP. This section discusses them. FOWLP RDLs by polymer and ECD Cu etching. This is the oldest method to make RDLs for fan-in WLP—for examples, see [3,4]. The RDL consists of two layers, the dielectric layer and the Cu conducting layer. The dielectric layer is made of a polymer, e.g.,polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO) and the conductor layer is made by electrochemical deposition (ECD) of Cu and etching.The key process steps are described as follows: 1) First, spin coat a polymeron the whole wafer; 2) That step is followed by spin coating a photoresist; 3)Then the photoresist is opened with a mask aligner or stepper. 4) The polymeris then etched, and the resist is stripped off; 5) Next, the adhesive/ seedlayer (Ti/Cu) is sputtered using physical vapor deposition (PVD); 6) The photoresist is then spin coated, and then the photoresist is opened with a mask aligner or stepper; and 7) Next comes electroplating the Cu. After the resistis stripped off and the TiCu is etched off, we have the first RDL. If one repeats the processes, you get the other RDLs. For example, Figure 1 shows the schematic of the chip and the RDL, the PCB assembly, and the cross section of the fan-in WLP[3]. Today, most out sourced semiconductor assembly and test suppliers(OSATS) use this method to make RDLs for FOWLP with chip-first and chip-last processing. Figure1: Fan-in WLP. FOWLP RDLs by photosensitive polymer and ECD Cu etching. A better and simpler process is shown in Figure 2 [5]. It can be seen that for the PI(polyimide) development, the whole reconstituted wafer is spin-coated with a photosensitive PI. It is followed by applying a stepper and then using photolithography techniques to align, expose, and develop the vias of the PI.Finally, the PI is cured at 200°C for one hour—this will form a 5µm-thick PI layer. It is followed by sputtering Ti and Cu by PVD at 175°C over the entire reconstituted wafer. Then, apply a photoresist and a stepper and use photolithography techniques to open the redistribution trace’s locations. Next,electroplate the Cu by ECD at room temperature on the Ti/Cu in the photoresist openings. These steps are followed by stripping off the photoresist and etching off the Ti/Cu; RDL1 is thereby obtained. Finally, repeat all the above steps toobtain other RDLs. Figure 3 shows the cross section of a FOWLP with 2 RDLs. This can be used for FOWLP with chip-first and chip-last processing. The RDLs made by the polymer (eitherphotosensitive or not) and ECD Cu etching are called organic RDLs. Figure2: FOWLP RDLs process flow using photosensitive polymer and ECD Cu etching. Figure3: Cross section of FOWLP RDLs using photosensitive polymer and ECD Cu etching. FOWLP RDLs by PECVD and Cu-Damascene CMP. This is the oldest back-end semiconductor process. This process uses SiO2 or SiN for the dielectric layer and ECD to deposit the Cu on the whole wafer. That is followed by using CMP to remove the overburden Cu and seedlayer to make the Cu conductor layer of the RDLs. The key process steps are shown in Figure 4. First, use PECVD to form a thin layer of SiO2 (orSiN) on a full thickness bare silicon wafer and then use a spin coater to laminate the photoresist. These steps are followed by using a stepper to open the resist and a reactive ion etch (RIE) to remove the SiO2. Then, a stepper is used to open the resist wider and RIE to etch more of the SiO2. Next, strip off the resist, sputter the TiCu, and ECD the Cu on the whole wafer. These steps are followed by CMP to remove the overburden Cu and the TiCu, and then we have the first RDL1 and V01 (the via connecting the Si and RDL1) as shown in Figure 5 [2]. This is called the dual Cu-damascene method [2]. Finally,repeat all the processes to get the other RDLs. This method can be applied to FOWLP with chip-first and chip-last processing. The RDLs made by PECVD and Cu-damascene CMP are called in organic RDLs. Figure4: FOWLP RDLs process flow usingPECVD and Cu-damascene CMP. Figure5: Cross section of RDLs usingPECVD and Cu-damascene CMP. FOWLP RDLs by hybrid-RDL. As of today, this hybrid-RDL method only applies to chip-last or RDL-first, i.e., wafer bumping and chip-to-wafer bonding are necessary. The key process steps for chip-last by hybrid RDLs are shown in Figure 6. It can be seen that a glass carrier-1 is coated with a sacrificial layer (Figure 6a). The contact pad and the first RDL (RDL1) are then fabricated by the PECVD for the SiO2 dielectric layer and dual Cu-damascene CMP for the conductor layer (Figure 6b). The remaining RDLs are fabricated by the ordinary polymer (or photosensitive polymer) and Cu-plating etching method. Another carrier-2 is then attached to the otherside of the reconstituted wafer (Figure 6c). That step is followed by debonding of the carrier-1 as shown in Figure 6d. That, in turn,is followed by fluxing, chip-to-wafer bonding, cleaning, underfill dispensing and curing as shown in Figure 6e. Then, the reconstituted wafer is molded with EMC (epoxy molding compound) by the compression method (Figure 6f). Next comes debonding of the carrier-2 and solder ball mounting as shown in Figure 6g. Figure 7 shows the cross section of a FOWLP with hybrid RDLs published by SPIL in ECTC2016 [6]. Figure 8 shows the cross section of a FOWLP with hybrid RDLs published by Amkor in ECTC2017 [7,8]. The two cross sections are very similar. Figure 6: FOWLP RDLs process flow for hybrid-RDLs. Figure 7: SPIL’s cross sections ofhybrid RDLs. Figure 8: Amkor’s cross sections ofhybrid RDLs. FOPLP RDL methods There are also four methods for fabricating RDLs used in FOPLP;they are discussed below. FOPLP RDLs by PCB SAP. The structure of J-Devices’ WFOP™ is shown in Figure9.It can be seen that there is not an EMC. However, there is a metal plate to support the whole package. The RDLs are fabricated by a printed circuit board(PCB) technology using a semi-additive process (SAP) [9-11]. First, the KGD isplaced face-up with adhesive on a metal panel carrier (320mm x 320mm) (Figure 10). Then, photosensitive resin is coated(as the dielectric layer of the RDL) on top of the KGDs on the whole panel.This is followed by exposing and developing the opens of the KGD’s window and direct current (DC) sputtering aseed layer for Cu plating. Next comes the application (coat) of a photoresist and then pattern the redistributed inter connections by photolithography techniques.Then, Cu-plating, photoresist stripping, and seed layer etching are done. Those steps are followed by solder mask coating, contact pad patterning, surface finishing, and solder ball mounting. Then, the panel and resin (dielectric)layer are diced into individual units (packages) (Figure 9). Basically, J-Devices’ (20µm line width andspacing) RDLs are fabricated by a PCB technology and SAP [9-11]. Figure 9: J-Devices’ WFOP. Figure 10: J-Devices’ WFOP process flow. FOPLP RDLs by PCB LDI. Fraunhofer’s FOPLP key process steps are very similar to the embedded wafer-level ball grid array (eWLB) technology proposed by Infineon. However, Fraunhofer’s RDL key process steps are different [12-14]. The Fraunhofer process begins with laminating a resin coated copper (RCC) on the reconstituted panel (610mm x457mm) (Figure 11). Then, a mechanical or laser drill is used to make holes in the RCC. That process is followed by PCB Cu plating to fill the holes and connect to the Al or Cu pads.Next, a dry-film photoresist is laminated, and then an LDI is used to removethe resist. Next comes accomplishing Cu etching and stripping off the resist.Fraunhofer then has the first RDL1 and can repeat all the processes to get the other RDLs. The final RDL can be used as a contact pad. The next processes include lamination, photolithography, and curing of the solder mask (in either a solder mask defined or a non-solder mask defined format) before mounting the solder balls. Figure 12a shows the 610mm x 457mm panel and Figure 12b shows the x-ray image of the 8mm x 8mm package, which is housing two chips with dimensions of 2mm x 3mm. Basically,Fraunhofer’s RDLs are fabricated by a PCB and LDI technology [12-14].
Figure 11: Fraunhofer’s FOPLP processflow.
Figure 12: Fraunhofer’s panel andpackage. FOPLP RDLs by PCB TFT-LCD. Based on a PCB technology, TFT-LCD (thin-film transistor liquid-crystal display) 2.5G(generation) technology (panel dimensions = 370mm x 470mm), and backend technology, SPIL developed its P-FO technology [15,16]. The chip is embedded ina dry film and currently, there is only one layer of RDL. The key process steps in making the P-FO package are as follows. First, an adhesive on top of a glass panel carrier-1 is applied (Figure 13a).The next step is to pick and place the known good dies (KGDs) face-down on the glass carrier-1 (Figure 13b).PCB technology is then used to laminate a dry film on top of the whole panel as shown in Figure 13c. It is followed by attaching another carrier-2 on the other side of the reconstituted panel and debonding the glass carrier-1 as shown in Figure 13d. Then, TFTLCD 2.5G processing technology is used to fabricate the RDL on top of the Al or Cu contact pads and dry film (Figure 13e). It is followed by solder ball mounting (Figure 13f) and dicing of the reconstituted panel as shown in Figure 13g.A test package (9mm x 9mm) that has an embedded chip (6mm x 6mm) with only one-RDL has been demonstrated and is shown in Figure 14.
Figure 13: SPIL’s P-FO process flow.
Figure 14: SPIL’s panel and package. FOPLP RDLs by PCB/ABF/SAP LDI. The dielectric and conductor layers ofthe RDLs fabricated by the Fraunhofer RCC method are too thick.Figure 15 shows a new process flow for fabricating the RDLs on a 340mm x340mm panel published in [17]. It starts off by laminating an Ajinomoto buildupfilm (ABF) on the reconstituted EMC molded panel. It is followed by laser drilling and electroless Cu seed layer plating as shown in Figure 15. Then, follow those steps with dry-film lamination, LDI lithography, dry film developing, and PCB Cu plating for RDL1. Follow those steps with stripping off the dry film and etching off the seed layer. These steps are then repeated to get the other RDLs. The final RDL can be used as a contact pad. The next steps are laminating, photolithography, and curing the solder mask (in either a soldermask defined, or a non-solder mask defined format) before mounting the solderballs. In this case, the dielectric layer thickness can be as little as 10µm and the conductor layer thickness can be as little as 5µm. Figure 16 shows the panel(340mm x 340mm) and the package (10mm x 10mm) with four chips, and the crosssection of the PCB assembly of a package made by the presented method, where RDL1 and RDL2 are shown.
Figure 15: FOPLP process flow byPCB/ABF/SAP LDI.
Figure16: Panel size, individual package, and PCB assembly of the FOPLP PCB/ABF/SAP LDI. Summary Eight methods forfabricating RDLs for FOW/PLP have been presented. Some important results and recommendations are summarized as follows: → For the four methods, namely a) polymerand ECD Cu etching, b) photosensitive polymer and ECD Cu etching, c) PECVD and Cu-damascene CMP, and d) hybrid RDL, in fabricating the RDLs for FOWLP,the photosensitive polymer and ECD Cu etching is recommended. → By viewing the change of the line width and spacing (from 5µm to 10µm) of the RDLs of the application processor chipsets (from A10 of iPhone 7 to A11 of iPhone 8), the chance of using PECVD and Cu- damascene CMP in fabricating the RDLs for FOWLP is very slim (may be only for niche applications). Also, it is very expensive and can only be afforded by very-high density and performance applications. On the other hand, for high-density and high performance applications, why insist on the FOWLP technology because there are many packaging alternatives? → For the four methods, namely a) PCB SAP, b) PCB LDI, c) PCB TFTLCD, and d) PCB/ABF/SAP LDI used infabricating RDLs for FOPLP, the PCB/ABF/SAP LDI is recommended. → The oretically speaking, FOPLP will potentially increase throughput and reduce cost. However, in order to achieve these goals, the following issues [18,19] for FOPLP need to be noted and/or resolved
References 1. P. Garrou, C. Huffman, “RDL: an integral part oftoday’s advanced packaging technologies,” Solid State Technology, Vol.54, No. 5, May 2011, pp. 18-20. 2. J. H. Lau, P. Tzeng, C. Lee, C. Zhan, M. Li, J. Cline, et al., “Redistribution layers (RDLs) for 2.5D/3D IC integration,” Proc.of IMAPS Symp., 2013, pp. 434-441. Also,published in IMAPS Trans., Jour. Of Microelectronic Pkging., 2014, pp. 16-24. 3. J. H. Lau, T. Chung, R. Lee, C. Chang, C. Chen, “Anovel and reliable wafer-level chip-scale package (WLCSP),” Proc. of the ChipScale Inter. Conf., SEMI, Sept. 1999, pp. H1-8. 4. J. H. Lau, S. W. R. Lee, Chip Scale Package,McGraw-Hi ll Book Company, 1999. 5. J. H. Lau, M. Li, Q. Li, I. Xu, T. Chen,Z. Li, et al., “Design, materials, process, fabrication, and reliability offan-out wafer-level packaging,” to be published in IEEE Trans. on CPMT. 6. M. Ma, S. Chen, P. I. Wu, A. Huang, C. H.Lu, A. Chen, et al., “The development and the integration of the 5μm to 1μmhalf pitches wafer level Cu redistribution layers,” IEEE/ECTC Proc., 2016, pp.1509-1614. 7. Y. Kim, J. Bae, M. Chang, A. Jo, J. Kim,S. Park, et al., “SLIM™, high density wafer-level fan-out package developmentwith sub-micron RDL,” IEEE/ECTC Proc., 2017, pp. 18-13. 8. D. Hiner, M. Kolbehdari, M. Kelly,Y. Kim,W. Do, J. Bae, “SLIM™ advanced fan-out packaging for high performance multi-diesolutions,” IEEE/ECTC Proc., 2017, pp. 575-580. 9. N. Hayashi, T. Takahashi, N. Shintani, T.Kondo, H. Marutani, Y. Takehara, et al., “A novel wafer level fan-out package(WFOP™) applicable to 50μm pad pitch interconnects,” IEEE/EPTC Proc., Dec.2011, pp. 730-733. 10. N. Hayashi, H. Machida, N. Shintani, N.Masuda, K. Hashimoto, A. Furuno, et al.,“A new embedded s t r uct ur e packagefor next - generation, WFOP™ (Wide Strip Fan-Out Package),” Pan Pacific Symp.Conf. Proc., Feb. 2014, pp. 1-7. 11. N. Hayashi, M. Nakashima, H. Demachi, S.Nakamura, T. Chikai, Y. Imaizumi, et al., “Advanced embedded packaging forpower devices,” IEEE/ECTC Proc., 2017, pp. 696-703. 12. T. Braun, K.-F. Becker, S. Voges, T.Thomas, R. Kahle, J. Bauer, etal., “From wafer-level to panel-level moldembedding,” IEEE/ECTC Proc., 2013, pp. 1235-1242. 13. T. Braun, K.-F. Becker, S. Voges, J.Bauer, R. Kahle, V. Bader, et al., “24”x18” fan-out panel-level packing,”IEEE/ECTC Proc., 2014, pp. 940-946. 14. T. Braun, S. Raatz, S. Voges, R. Kahle,V. Bader, J. Bauer, et al.,“Large area compression molding for fan-out panel-levelpackaging,” IEEE/ECTC Proc., 2015, pp. 1077-1083. 15. H. Chang, D. Chang, K. Liu, H. Hsu, R.Tai, H. Huang, “Development and characterization of new generation panelfan-out (PFO) packaging technology,” IEEE/ECTC Proc., 2014, pp. 947-951. 16. H. Liu, Y. Liu, J. Ji, J. Liao, A. Chen,“Warpage characterization of panel fan-out (P-FO) package,” IEEE/ECTC Proc.,2014, pp. 1750-1754. 17. C. Ko, H. Yang, J. H. Lau, M. Li, Q. Li,C. Lin, et al., “Chip-first fan-out panel-level packaging for heterogeneousintegration,” IEEE/ECTC Proc., May 2018. 18. Extracted from the 2017 IEEE/ECTC panelsession: “Panel Fanout Manufacturing: Why, When, and How?” 19. J. H. L au , Fan -Out Wafer -LevelPackaging, Springer Book Company, 2018. Biography John H. Laureceived his PhD degree from the U. of Illinois, Urbana, and is a SeniorTechnical Advisor at ASM Pacific Technology Ltd.; email john.lau@asmpt.com 封装技术千人群 1.仅限封测人员，不重复加群 2.先加群主，验证后邀请加入 3.需要注明：单位 岗位/方向 学习,交流,分享IC封测技术,包括但不限于设计,仿真,工艺,可靠性...业界主要IC,封测,载板厂商都已到齐.已加入厂商（部分）： 长电、华天、通富、晶方、芯健......越亚、深南、兴森、康源…… 华为、中兴、展讯、联芯、全志、联想、国科、芯源、灿芯、锐迪科、瑞芯微、景嘉微、汉天下、新岸线、国民技术…… ASE, Amkor, PTI, SPIL, UTAC, STATS ChipPAC, Unisem, Sandisk, Shunsin, Qorvo, Micron, Ramaxel, MTK, Synaptics, Goodix, Intel, AMD…...Ansys, Keysight, Cadence…… |
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