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Fan-out wafer-level packaging (FOWLP) is a key enabler in the industry shift from transistor scaling to system scaling and integration. The design fans out the chip interconnects through a redistribution layer instead of a substrate. Compared to flip-chip ball grid array (FCBGA) or wire bonds, it creates lower thermal resistance, a slimmer package, and potentially lower costs. Yet, if the hope is to reduce costs through eliminating substrates, the reality is that a lack of substrates can cause die shifts and warpage, undercutting the savings. Engineers are addressing die shift through improvements in lithography, pick-and-place, and molding operations — either thermocompression or laser bonding. “It’s a great technology for one or two die,” said John Park, product management director for IC packaging at Cadence Design Systems. “But once you get to half a dozen chiplets or more, the limiting factor is die shift. Obviously, the more die you have, each one gets slightly shifted by a degree or two, and then you put six together and nothing connects anymore.” Nevertheless, issues such as long lead times for package substrates are accelerating FOWLP adoption. “Mobile and high performance computing/networking are a few areas where we see growing adoption beyond the low pin count, power management fan-out wafer level structure that has been traditionally the main FOLWP application,” said Mark Gerber, senior director, engineering and technical marketing at ASE. On balance, FOWLP is advancing as a solution. In Apple’s M1 Ultra chip, TSMC’s InFO fan-out process was chosen over a substrate-based process for its latest application processors (see figure 1). This is part of a broader trend. The market for fan-out packaging is expected to grow at a 15% compound annual growth rate, reaching $3.4B in 2026, according to Yole Développement. Yole analysts expect 93% of that capacity to be wafer-level packaging in 2025, and 7% to be processed at the panel level.
Fig. 1: State-of-the-art RDL connecting to via in TSMC’s InFO and Deca’s M-Series. Source: Deca Other products in volume production today include RF devices, power management ICs (PMICs), baseband processors, and high-end server chips. 5G should further boost the adoption of fan-out packaging because the shorter interconnects and lower inductance lead to superior RF and millimeter-wave performance. “There’s been a lot of discussion and modeling of FOWLP for millimeter wave antenna and millimeter wave packaging,” said Dr. Monita Pau, strategic marketing director for advanced packaging at Onto Innovation. “That makes the dielectric material a very important element. You must have very good mechanical properties and very low loss dielectric properties, because you’re integrating a millimeter wave antenna together with the fan-out packages. Additionally, low copper RDL roughness and lithographic techniques that adapt to topography are needed to achieve good CD uniformity of the redistribution layer, which is critical to achieving high gain and low loss transfer.” Fan out’s roots 扇出根部 While cell phones have been the canonical use case ever since the iPhone 7, the FOWLP design also can scale up for devices like supercomputers. Newer applications include network switching products, PMICs for phones and smart watches, and AI chips. For assembly in high-end applications, OSATs and foundries are coupling fan-out packaging together with a substrate. “Before people used to say you didn’t need to use a substrate, you can just directly attach it to the board, but now because of the high-density requirements, they need a substrate before it can be attached to the PCB board,” said Pau. Today’s FOWLP designs also enable a more flexible design. Gerber said, “Our Fan Out Chip on Substrate Bridge (FOCoS-B) pillar can integrate one or more die in between redistribution layers, integrating deep trench capacitors, voltage regulators, etc., in very close proximity to the active silicon circuitry. This minimizes system level loss for higher performance.” Process 过程
Fig. 2: Process flows for chip first (mold first) configuration and RDL first. Source: Fraunhofer IZM In die first, thermal release tape is applied to a carrier wafer, then the known good die (KGD) are picked and placed on the carrier. Next, overmolding is followed by carrier release, RDL formation, solder bumping, then singulation. In RDL first, the release layer again is deposited first, then the RDL, KGD positioning is followed by overmold, carrier release, solder ball deposition, and singulation. While fan-out starts with classic assembly techniques, it also requires non-traditional processes. “It adds things that you don’t normally see, like compression molding onto the reconstituted wafer to fill in areas, and then grinding the plastic material mold compound as opposed to backgrinding a wafer,” said Chip Greely, vice president of engineering at Promex Industries, the parent company of QP Technologies. “Then you deposit a copper redistribution layer on top of that, which gets you three factors away from what some assembly houses are comfortable with. Typically, when you’re backgrinding silicon or any of those crystal materials, they tend to granulate and wash out very easily. Mold compound tends to gum and ball up, so your grinding wheel gets loaded up with plastic, requiring a secret sauce to remove it.” Nevertheless, he says, with enough devices, the economies of scale work. The reason fan-out has gained such popularity relative to fan-in WLP is because it accommodates more I/O connections. The state-of-the-art fan out package today features RDLs of up to five-layers (see figure 3), with down to 2µm lines and spaces (the width and pitch of metal traces). Scaling to the micron interconnect range means the RDL process is beginning to look more like on-chip dual damascene integration.
Fig. 3: Redistribution layers consist of copper traces in polyimide dielectric. Source: Lam Research For example, Amkor recently revealed an embedded trace RDL (ETR) for its S-SWIFT fan-out technology that enables scaling to less than 2/1 line/space and vias.[1] The new process integrates an ASIC with two high-bandwidth memory (HBM) chips. Innovations include a through-mold copper pillar, high-density RDL, uniform dielectric coating, optimized copper plating, CMP, and wet etch to enable a simpler, more extendible process than its process of record (POR). Amkor Vice President SangHyun Jin and his team improved on the POR, a semi-additive process (see figure 4a). Process changes were explored to overcome potential for high AR trace collapse, photoresist residue in vias and sidewall etch issues. The Amkor team first developed a dual-damascene process (figure 4b) that embeds the copper trace in a polymer layer. This change improves adhesion of the RDL to substrate and by depositing barrier layer on three sides of the trench, reliability is enhanced. The team noted that the vias and RDL were separately formed by a two-pass lithography process using spin coat of an organic dielectric. After curing, the seed layer and copper were plated, followed by CMP and wet etch. The final process (figure 4c) combines the via and RDL patterning into one mask, reducing process steps by 40%. This change also eliminated misalignment between the via and capture pad. The three-step CMP process was changed to single CMP, followed by wet etch. CMP ensured flatter profiles for each RDL and 2μm line with 1μm spaces were fabricated on a four-layer RDL, with extendibility to six layers. Following assembly, the engineers performed reliability testing on the heterogenous devices.
Fig. 4: An RDL semi-additive process (a), was modified to dual damascene (b) and then simplified damascene (c) process that is extendible to 2/1μm line/space traces. Source: Amkor Also at ECTC, Lihong Cao, director of engineering at ASE, and her team showed how fan out to RDLs can be used to reduce the complexity and cost of ASICs on multilayer organic interposer (ABF) substrates. [2] ASE was able to convert a 14-layer substrate to 8 layers with 2 RDLs. A second test device showed a 10-layer substrate was reduced to 4 layers using 1 RDL. Such changes will reduce the cost and yield loss associated with increasingly complex substrates. Die shift 模具移位 Die shift can be reduced by using laser assisted bonding or thermocompression bonding in place of conventional mass flow. Another method is Adaptive Patterning, created by Deca and built into Cadence’s EDA tools. It will soon be available for Synopsys and Siemens EDA tools. In adaptive patterning (see figure 5), the process engineer measures the die and interconnect positions precisely on the lithography tool, then the deposited RDL pattern is adapted to those positions.
Fig. 5: Adaptive Patterning aligns the vias and RDL contacts with the actual location of the die. Source: Deca “In the design process you determine which AP techniques will most optimally help you to scale to higher density or adjust the manufacturing process capability to achieve 100% yield, or very close to it,” said Tim Olson, CEO of Deca Technologies. “So there are decisions you make in the design process regarding which manufacturing factory is going to be used. Once you release the design to manufacturing, the patterning engine at our licensees in Taiwan, the Philippines, and Korea have servers whereby on each wafer, or each panel, we do high-speed optical scans to locate the I/Os. The engine takes the design instructions on one of those EDA systems, and then it executes per RDL layer, doing either alignment or optimization. In some cases, it’s redrawn to accommodate shift.” Finally, the GDSII file is converted into a digital bitmap and used by a compatible maskless lithography tool to print the aligned connections. “We have a new approach that eliminates capture pads,” Olson noted. “Capture pads were invented to take up overlay tolerances. With adaptive patterning, we can achieve breakthrough density without the use of capture pads.” He added that the specification on pick-and-place only needs to be 15µm, whereas much higher accuracy is needed without adaptive patterning, which lowers tool throughput significantly. Die shift is also addressed by refining the choice of bonding material, as Brewer Science explains: “In order for bonding materials to maintain minimal vertical deformation during die placement and minimal die shift during over-molding, they have to have high melt viscosity and high thermal stability. This is particularly important due to the mismatch between the coefficients of thermal expansion (CTEs) of the carrier and substrate material. Bonding materials have to also be customized in a way that minimizes stress effects in stacked wafers, where warpage might occur, resulting in issues of alignment and handling. They should have sufficient adhesion to the substrate material to be able to tolerate such stresses.” Stress and warpage “Warpage is definitely a problem. That’s why a lot of the individuals are moving to the compression molding and the bottom gated, compression molding versus the top system,” said Greely. Another way to reduce stress and warping is by selecting better dielectric material with lower cure temperatures. Going to panels? 去面板？ Though these companies appear to be moving forward, FOPLP is largely on hold until volumes dictate the need for a massive conversion from wafer carriers to panel-level processing. It’s unclear when that will change. “If they say five years is a window of opportunity, I would at least triple it,” said Greely. “Panelization is such a great idea, but there are challenges when you get into the details. It’s like telling people that we’re going to have a standardized chiplet.” Design 设计 However, packages are a different world from laminates, cautions Park. For example, packages come with unique types of design rules, such as “zigzag insertion,” which is the need for a break in a lateral line to improve yield. “Traditional packaging tools output Gerber file formats (.grb), which are manufacturing formats for laminate substrates, not wafers,” said Park. “When you build a laminate, there is no formal sign off process, like DRC and LBF, as there is when building a wafer.” To address this problem, Cadence has created an extension that links IC verification tools with package physical design tools. “If someone is new to the IC world, they can just pick the rules they want to check against in a GUI, and the tool will do the LBS and DRC. And then, any results from that run will be presented back to the user inside the layout tool,” said Park. There are additional issues that can challenge engineers, regardless of their prior experience. “The requirements for ultra-high density RDLs, such as are found in TSMC’s inFO, are much more stringent than anything package designers have had to deal with in the past,” he said. Design tools are now taking into account metal balancing, with such issues as voiding pads and vias and degassing copper fill areas. Finally, there’s conductivity verification, which can be extremely complex when multiple chiplets are involved. “It may come at the last stage of production,” said Park, “But you have to think about it early on, because that net list that drives the LVS has to be built in the early stages of the design.” Conclusion 结论 Vardaman sees both chip first and chip last schemes being required going forward. “Everything is about picking the right package and the right structure for what you’re trying to do.” References 参考 [2] L. Cao, et., al., “Advanced Fanout Packaging Technology for Hybrid Substrate Integration,” IEEE 71st Electronic Components and Technology Conference (ECTC), 2022, doi: 10.1109/ECTC51906.2022.00219 |
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