这是集成电路物理设计的第一个系列【physical cell】的第二篇文章,本文主要讲TAP Cell相关知识: 1,什么是TAP Cell? TAP Cell只有两个连接关系:nWell连接VDD,pSub连接VSS。 TAP Cell没有 input pin和output pin,内部没有任何逻辑功能。 早期的standard cell内部包含tap cell (taped standard cell),新工艺的standard cell内部一般不包含tap cell,而是使用单独的tap cell (tapless standard cell)。
2,为什么要加入TAP Cell?
3,如何Insert TAP Cell?
实际上并不需要每个standard cell的nWell/pSub都需要连接VDD/VSS,只需要Row上隔一段距离连接就可以。 tap cell在摆放好macro之后,在摆放standard cell之前放置。 两个tap cell之间的摆放距离需要根据DRC rule来设置。 FC/ICC2 cmd: >create_tap_cells -lib_cell */TAPCELL -distance $distance -minn_horizontal_periphery_spacing 1 -pattern stagger -no_abutment -no_abutment_horizontal_spacing 1 -no_abutment_corner_spacing 3 -skip_fixed_cells.Innovus cmd:
>set_well_tap_mode -rule $welltap_D -bottom_tap_cells $bottom tap_cell -top_tap_cell $top_tap_cells -cell $tap_cells>set_well_tap_mode -insert_cells {{TAPCELL1 rule $distance1} {TAPCELL2 rule $distance2}} >addWellTap -cell $tap_cells -cellInterval [expr 4*$welltap_D] -checkerBoard -incr *
4,什么是Latch Up?
Latch Up是CMOS电路的一种寄生现象,当Latch Up发生时,会形成一条从VDD到GND的低电阻通路,这会产生大电流,对芯片造成不可逆的损伤。 在CMOS电路中,两个寄生的BJT结构(PNPN)会形成Latch Up结构。 PNPN寄生结构一般是不会处于开启状态,但当其达到触发条件时,会瞬态开启并形成一个从VDD到VSS的低电阻通路,且该状态发生后便不再需要触发条件也可以自己维持触发状态。
下图是常见的CMOS电路中PNPN结构寄生产生的Latch Up结构,为避免触发该Latch Up 结构,需要将寄生的两个PN二极管反偏防止其导通,即p-substrate连接GND,nWell连接VSS(这也是tap cell的作用)。
5,如何预防Latch Up的发生? Guard rings
provides a better way to collect the minority carriers.Guard ring consist of a P+ ring on Psubstrate and N+ ring on Nwell all around the nMOS and pMOS.These rings contains as many as contacts as per design rules.N+ rings connected to VDD and P+ ring connected to GND.There rings will collect the minority carriers and avoid the development of potential difference between body and source which activate the BJTsWell isolatioon by trench Isolate the NMOS and PMOS using oxide trench and Buried oxide
Epitaxial layer This is called P on P+. provides a low impedance path for minority carriers.
Retrograde well doping In retrograde well doping, peak concentration is in deep inside the nWell, no in surface.
Combination of epitaxial layer and retrograde well doping ESD circuit SOI technology No Latch Up Issue. Less parasitic capacitance, leads to less leakage current. Self heating problem.
6,参考资料
https://www./channel/UCVWaC1gXZfHNqwdl6jovsjQ
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